sysreg.h revision 272209
1230557Sjimharris/*- 2230557Sjimharris * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3230557Sjimharris * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4230557Sjimharris * All rights reserved. 5230557Sjimharris * 6230557Sjimharris * Redistribution and use in source and binary forms, with or without 7230557Sjimharris * modification, are permitted provided that the following conditions 8230557Sjimharris * are met: 9230557Sjimharris * 1. Redistributions of source code must retain the above copyright 10230557Sjimharris * notice, this list of conditions and the following disclaimer. 11230557Sjimharris * 2. Redistributions in binary form must reproduce the above copyright 12230557Sjimharris * notice, this list of conditions and the following disclaimer in the 13230557Sjimharris * documentation and/or other materials provided with the distribution. 14230557Sjimharris * 15230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16230557Sjimharris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17230557Sjimharris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18230557Sjimharris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19230557Sjimharris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20230557Sjimharris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21230557Sjimharris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22230557Sjimharris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23230557Sjimharris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24230557Sjimharris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25230557Sjimharris * SUCH DAMAGE. 26230557Sjimharris * 27230557Sjimharris * $FreeBSD: head/sys/arm/include/sysreg.h 272209 2014-09-27 09:57:34Z andrew $ 28230557Sjimharris */ 29230557Sjimharris 30230557Sjimharris/* 31230557Sjimharris * Macros to make working with the System Control Registers simpler. 32230557Sjimharris */ 33230557Sjimharris 34230557Sjimharris#ifndef MACHINE_SYSREG_H 35230557Sjimharris#define MACHINE_SYSREG_H 36230557Sjimharris 37230557Sjimharris/* 38230557Sjimharris * CP15 C0 registers 39230557Sjimharris */ 40230557Sjimharris#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 41230557Sjimharris#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 42230557Sjimharris#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 43230557Sjimharris#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 44230557Sjimharris#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 45230557Sjimharris#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 46230557Sjimharris 47230557Sjimharris#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 48230557Sjimharris#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 49230557Sjimharris#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 50230557Sjimharris#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ 51230557Sjimharris#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ 52230557Sjimharris#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ 53230557Sjimharris#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ 54230557Sjimharris#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ 55230557Sjimharris 56230557Sjimharris#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ 57230557Sjimharris#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ 58230557Sjimharris#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ 59230557Sjimharris#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ 60230557Sjimharris#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ 61230557Sjimharris#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ 62230557Sjimharris 63230557Sjimharris#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ 64230557Sjimharris#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ 65230557Sjimharris#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ 66230557Sjimharris 67230557Sjimharris#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ 68230557Sjimharris 69230557Sjimharris/* 70230557Sjimharris * CP15 C1 registers 71230557Sjimharris */ 72230557Sjimharris#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ 73230557Sjimharris#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ 74230557Sjimharris#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ 75230557Sjimharris 76230557Sjimharris#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 77230557Sjimharris#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 78230557Sjimharris#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 79230557Sjimharris 80230557Sjimharris/* 81230557Sjimharris * CP15 C2 registers 82230557Sjimharris */ 83230557Sjimharris#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ 84230557Sjimharris#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ 85230557Sjimharris#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ 86230557Sjimharris 87230557Sjimharris/* 88230557Sjimharris * CP15 C3 registers 89230557Sjimharris */ 90230557Sjimharris#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ 91230557Sjimharris 92230557Sjimharris/* 93230557Sjimharris * CP15 C5 registers 94230557Sjimharris */ 95230557Sjimharris#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ 96230557Sjimharris 97230557Sjimharris#if __ARM_ARCH >= 6 98230557Sjimharris/* From ARMv6: */ 99230557Sjimharris#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ 100230557Sjimharris/* From ARMv7: */ 101230557Sjimharris#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ 102230557Sjimharris#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ 103230557Sjimharris#endif 104230557Sjimharris 105230557Sjimharris 106230557Sjimharris/* 107230557Sjimharris * CP15 C6 registers 108230557Sjimharris */ 109230557Sjimharris#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ 110230557Sjimharris 111230557Sjimharris#if __ARM_ARCH >= 6 112230557Sjimharris/* From ARMv6k: */ 113230557Sjimharris#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ 114230557Sjimharris#endif 115230557Sjimharris 116230557Sjimharris/* 117230557Sjimharris * CP15 C7 registers 118230557Sjimharris */ 119230557Sjimharris#if __ARM_ARCH >= 6 120230557Sjimharris/* From ARMv7: */ 121230557Sjimharris#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ 122230557Sjimharris#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ 123230557Sjimharris#endif 124230557Sjimharris 125230557Sjimharris#define CP15_PAR p15, 0, r0, c7, c4, 0 /* Physical Address Register */ 126230557Sjimharris 127230557Sjimharris#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ 128230557Sjimharris#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ 129230557Sjimharris#if __ARM_ARCH >= 6 130230557Sjimharris/* Deprecated in ARMv7 */ 131230557Sjimharris#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ 132230557Sjimharris#endif 133230557Sjimharris#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ 134230557Sjimharris#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ 135230557Sjimharris 136230557Sjimharris#if __ARM_ARCH >= 6 137230557Sjimharris/* Only ARMv6: */ 138230557Sjimharris#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ 139230557Sjimharris#endif 140230557Sjimharris#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ 141230557Sjimharris#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ 142230557Sjimharris 143230557Sjimharris#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ 144230557Sjimharris#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ 145230557Sjimharris#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ 146230557Sjimharris#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ 147230557Sjimharris 148230557Sjimharris#if __ARM_ARCH >= 6 149230557Sjimharris/* From ARMv7: */ 150230557Sjimharris#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 151230557Sjimharris#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 152230557Sjimharris#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ 153230557Sjimharris#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ 154230557Sjimharris#endif 155230557Sjimharris 156230557Sjimharris#if __ARM_ARCH >= 6 157230557Sjimharris/* Only ARMv6: */ 158230557Sjimharris#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 159230557Sjimharris#endif 160230557Sjimharris#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 161230557Sjimharris#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 162230557Sjimharris#if __ARM_ARCH >= 6 163230557Sjimharris/* Only ARMv6: */ 164230557Sjimharris#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 165230557Sjimharris#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ 166230557Sjimharris#endif 167230557Sjimharris 168230557Sjimharris#if __ARM_ARCH >= 6 169230557Sjimharris/* From ARMv7: */ 170230557Sjimharris#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 171230557Sjimharris#endif 172230557Sjimharris 173230557Sjimharris#if __ARM_ARCH >= 6 174230557Sjimharris/* Only ARMv6: */ 175230557Sjimharris#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ 176230557Sjimharris#endif 177230557Sjimharris#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ 178230557Sjimharris#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ 179230557Sjimharris 180230557Sjimharris/* 181230557Sjimharris * CP15 C8 registers 182230557Sjimharris */ 183230557Sjimharris#if __ARM_ARCH >= 6 184230557Sjimharris/* From ARMv7: */ 185230557Sjimharris#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ 186230557Sjimharris#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ 187230557Sjimharris#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ 188230557Sjimharris#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ 189230557Sjimharris#endif 190230557Sjimharris 191230557Sjimharris#define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ 192230557Sjimharris#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ 193230557Sjimharris#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 194230557Sjimharris 195230557Sjimharris#if __ARM_ARCH >= 6 196230557Sjimharris/* From ARMv6: */ 197230557Sjimharris#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 198230557Sjimharris#endif 199230557Sjimharris 200230557Sjimharris/* 201230557Sjimharris * CP15 C10 registers 202230557Sjimharris */ 203230557Sjimharris/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 204230557Sjimharris#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 205230557Sjimharris#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 206230557Sjimharris/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 207230557Sjimharris#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 208230557Sjimharris#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ 209230557Sjimharris 210230557Sjimharris#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ 211230557Sjimharris#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ 212230557Sjimharris 213230557Sjimharris/* 214230557Sjimharris * CP15 C12 registers 215230557Sjimharris */ 216230557Sjimharris#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ 217230557Sjimharris#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ 218230557Sjimharris 219230557Sjimharris#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ 220230557Sjimharris 221230557Sjimharris/* 222230557Sjimharris * CP15 C13 registers 223230557Sjimharris */ 224230557Sjimharris#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ 225230557Sjimharris#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ 226230557Sjimharris#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ 227230557Sjimharris#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ 228230557Sjimharris#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ 229230557Sjimharris 230230557Sjimharris#endif /* !MACHINE_SYSREG_H */ 231230557Sjimharris