1129198Scognet/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 2002 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet * 37129198Scognet * $FreeBSD: releng/10.3/sys/arm/include/cpuconf.h 276312 2014-12-27 17:36:49Z ian $ 38129198Scognet * 39129198Scognet */ 40129198Scognet 41129198Scognet#ifndef _MACHINE_CPUCONF_H_ 42129198Scognet#define _MACHINE_CPUCONF_H_ 43129198Scognet 44129198Scognet/* 45129198Scognet * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46129198Scognet * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47129198Scognet * YOU ARE ADDING SUPPORT FOR. 48129198Scognet */ 49129198Scognet 50129198Scognet/* 51129198Scognet * Step 1: Count the number of CPU types configured into the kernel. 52129198Scognet */ 53266311Sian#define CPU_NTYPES (defined(CPU_ARM9) + \ 54172738Simp defined(CPU_ARM9E) + \ 55172738Simp defined(CPU_ARM10) + \ 56244480Sgonzo defined(CPU_ARM1136) + \ 57244480Sgonzo defined(CPU_ARM1176) + \ 58172738Simp defined(CPU_XSCALE_80200) + \ 59172738Simp defined(CPU_XSCALE_80321) + \ 60173249Skevlo defined(CPU_XSCALE_PXA2X0) + \ 61201468Srpaulo defined(CPU_FA526) + \ 62207611Skevlo defined(CPU_FA626TE) + \ 63239268Sgonzo defined(CPU_XSCALE_IXP425)) + \ 64239268Sgonzo defined(CPU_CORTEXA) + \ 65266058Sian defined(CPU_KRAIT) + \ 66239268Sgonzo defined(CPU_MV_PJ4B) 67129198Scognet 68129198Scognet/* 69129198Scognet * Step 2: Determine which ARM architecture versions are configured. 70129198Scognet */ 71266311Sian#if defined(CPU_ARM9) || defined(CPU_FA526) 72129198Scognet#define ARM_ARCH_4 1 73129198Scognet#else 74129198Scognet#define ARM_ARCH_4 0 75129198Scognet#endif 76129198Scognet 77172738Simp#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 78172738Simp defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 79172738Simp defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ 80214972Skevlo defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 81214972Skevlo defined(CPU_FA626TE)) 82129198Scognet#define ARM_ARCH_5 1 83129198Scognet#else 84129198Scognet#define ARM_ARCH_5 0 85129198Scognet#endif 86129198Scognet 87239268Sgonzo#if !defined(ARM_ARCH_6) 88276284Sian#if defined(CPU_ARM1136) || defined(CPU_ARM1176) 89172738Simp#define ARM_ARCH_6 1 90172738Simp#else 91172738Simp#define ARM_ARCH_6 0 92172738Simp#endif 93239268Sgonzo#endif 94172738Simp 95276284Sian#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) 96239268Sgonzo#define ARM_ARCH_7A 1 97239268Sgonzo#else 98239268Sgonzo#define ARM_ARCH_7A 0 99239268Sgonzo#endif 100239268Sgonzo 101239268Sgonzo#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) 102276312Sian 103276312Sian/* 104276312Sian * Compatibility for userland builds that have no CPUTYPE defined. Use the ARCH 105276312Sian * constants predefined by the compiler to define our old-school arch constants. 106276312Sian * This is a stopgap measure to tide us over until the conversion of all code 107276312Sian * to the newer ACLE constants defined by ARM (see acle-compat.h). 108276312Sian */ 109276312Sian#if ARM_NARCH == 0 110276312Sian#if defined(__ARM_ARCH_4T__) 111276312Sian#undef ARM_ARCH_4 112276312Sian#undef ARM_NARCH 113276312Sian#define ARM_ARCH_4 1 114276312Sian#define ARM_NARCH 1 115276312Sian#define CPU_ARM9 1 116276312Sian#elif defined(__ARM_ARCH_6ZK__) 117276312Sian#undef ARM_ARCH_6 118276312Sian#undef ARM_NARCH 119276312Sian#define ARM_ARCH_6 1 120276312Sian#define ARM_NARCH 1 121276312Sian#define CPU_ARM1176 1 122276312Sian#endif 123276312Sian#endif 124276312Sian 125159167Scognet#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 126129198Scognet#error ARM_NARCH is 0 127129198Scognet#endif 128129198Scognet 129239268Sgonzo#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A 130129198Scognet/* 131172738Simp * We could support Thumb code on v4T, but the lack of clean interworking 132172738Simp * makes that hard. 133172738Simp */ 134172738Simp#define THUMB_CODE 135172738Simp#endif 136172738Simp 137172738Simp/* 138129198Scognet * Step 3: Define which MMU classes are configured: 139129198Scognet * 140129198Scognet * ARM_MMU_MEMC Prehistoric, external memory controller 141129198Scognet * and MMU for ARMv2 CPUs. 142129198Scognet * 143266311Sian * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARMv4 and v5. 144129198Scognet * 145239268Sgonzo * ARM_MMU_V6 ARMv6 MMU. 146239268Sgonzo * 147239268Sgonzo * ARM_MMU_V7 ARMv7 MMU. 148239268Sgonzo * 149129198Scognet * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 150129198Scognet * MMU, but also has several extensions which 151129198Scognet * require different PTE layout to use. 152129198Scognet */ 153266311Sian#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 154239268Sgonzo defined(CPU_ARM10) || defined(CPU_FA526) || \ 155207611Skevlo defined(CPU_FA626TE)) 156129198Scognet#define ARM_MMU_GENERIC 1 157129198Scognet#else 158129198Scognet#define ARM_MMU_GENERIC 0 159129198Scognet#endif 160129198Scognet 161271327Sian#if defined(CPU_ARM1136) || defined(CPU_ARM1176) 162239268Sgonzo#define ARM_MMU_V6 1 163239268Sgonzo#else 164239268Sgonzo#define ARM_MMU_V6 0 165239268Sgonzo#endif 166239268Sgonzo 167271327Sian#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) 168239268Sgonzo#define ARM_MMU_V7 1 169239268Sgonzo#else 170239268Sgonzo#define ARM_MMU_V7 0 171239268Sgonzo#endif 172239268Sgonzo 173215031Skevlo#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 174215031Skevlo defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 175215031Skevlo defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 176129198Scognet#define ARM_MMU_XSCALE 1 177129198Scognet#else 178129198Scognet#define ARM_MMU_XSCALE 0 179129198Scognet#endif 180129198Scognet 181266311Sian#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_V6 + \ 182266311Sian ARM_MMU_V7 + ARM_MMU_XSCALE) 183159167Scognet#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 184129198Scognet#error ARM_NMMUS is 0 185129198Scognet#endif 186129198Scognet 187129198Scognet/* 188129198Scognet * Step 4: Define features that may be present on a subset of CPUs 189129198Scognet * 190129198Scognet * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 191129198Scognet */ 192129198Scognet 193161592Scognet#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 194215031Skevlo defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 195129198Scognet#define ARM_XSCALE_PMU 1 196129198Scognet#else 197129198Scognet#define ARM_XSCALE_PMU 0 198129198Scognet#endif 199129198Scognet 200164777Scognet#if defined(CPU_XSCALE_81342) 201164777Scognet#define CPU_XSCALE_CORE3 202164777Scognet#endif 203129198Scognet#endif /* _MACHINE_CPUCONF_H_ */ 204