cpu-v6.h revision 276333
1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/arm/include/cpu-v6.h 276333 2014-12-28 18:12:56Z ian $ 28 */ 29#ifndef MACHINE_CPU_V6_H 30#define MACHINE_CPU_V6_H 31 32#include "machine/atomic.h" 33#include "machine/cpufunc.h" 34#include "machine/cpuinfo.h" 35#include "machine/sysreg.h" 36 37 38#define CPU_ASID_KERNEL 0 39 40/* 41 * Macros to generate CP15 (system control processor) read/write functions. 42 */ 43#define _FX(s...) #s 44 45#define _RF0(fname, aname...) \ 46static __inline register_t \ 47fname(void) \ 48{ \ 49 register_t reg; \ 50 __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ 51 return(reg); \ 52} 53 54#define _WF0(fname, aname...) \ 55static __inline void \ 56fname(void) \ 57{ \ 58 __asm __volatile("mcr\t" _FX(aname)); \ 59} 60 61#define _WF1(fname, aname...) \ 62static __inline void \ 63fname(register_t reg) \ 64{ \ 65 __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ 66} 67 68/* 69 * Raw CP15 maintenance operations 70 * !!! not for external use !!! 71 */ 72 73/* TLB */ 74 75_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */ 76#if __ARM_ARCH >= 7 && defined SMP 77_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */ 78#endif 79_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */ 80#if __ARM_ARCH >= 7 && defined SMP 81_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */ 82#endif 83_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */ 84#if __ARM_ARCH >= 7 && defined SMP 85_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */ 86#endif 87_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */ 88 89_WF1(_CP15_TTB_SET, CP15_TTBR0(%0)) 90 91/* Cache and Branch predictor */ 92 93_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */ 94#if __ARM_ARCH >= 7 && defined SMP 95_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */ 96#endif 97_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */ 98_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */ 99_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */ 100_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */ 101#if __ARM_ARCH >= 7 102_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */ 103#endif 104_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */ 105_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */ 106_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */ 107_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */ 108#if __ARM_ARCH >= 7 && defined SMP 109_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */ 110#endif 111_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */ 112 113/* 114 * Publicly accessible functions 115 */ 116 117/* Various control registers */ 118 119_RF0(cp15_dfsr_get, CP15_DFSR(%0)) 120_RF0(cp15_ifsr_get, CP15_IFSR(%0)) 121_WF1(cp15_prrr_set, CP15_PRRR(%0)) 122_WF1(cp15_nmrr_set, CP15_NMRR(%0)) 123_RF0(cp15_ttbr_get, CP15_TTBR0(%0)) 124_RF0(cp15_dfar_get, CP15_DFAR(%0)) 125#if __ARM_ARCH >= 7 126_RF0(cp15_ifar_get, CP15_IFAR(%0)) 127#endif 128 129/*CPU id registers */ 130_RF0(cp15_midr_get, CP15_MIDR(%0)) 131_RF0(cp15_ctr_get, CP15_CTR(%0)) 132_RF0(cp15_tcmtr_get, CP15_TCMTR(%0)) 133_RF0(cp15_tlbtr_get, CP15_TLBTR(%0)) 134_RF0(cp15_mpidr_get, CP15_MPIDR(%0)) 135_RF0(cp15_revidr_get, CP15_REVIDR(%0)) 136_RF0(cp15_aidr_get, CP15_AIDR(%0)) 137_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0)) 138_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0)) 139_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0)) 140_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0)) 141_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0)) 142_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0)) 143_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0)) 144_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0)) 145_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0)) 146_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0)) 147_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0)) 148_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0)) 149_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0)) 150_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0)) 151_RF0(cp15_cbar_get, CP15_CBAR(%0)) 152 153#undef _FX 154#undef _RF0 155#undef _WF0 156#undef _WF1 157 158#endif /* !MACHINE_CPU_V6_H */ 159