armreg.h revision 249999
1193156Snwhitehorn/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2193156Snwhitehorn 3193156Snwhitehorn/*- 4193156Snwhitehorn * Copyright (c) 1998, 2001 Ben Harris 5193156Snwhitehorn * Copyright (c) 1994-1996 Mark Brinicombe. 6193156Snwhitehorn * Copyright (c) 1994 Brini. 7193156Snwhitehorn * All rights reserved. 8193156Snwhitehorn * 9193156Snwhitehorn * This code is derived from software written for Brini by Mark Brinicombe 10193156Snwhitehorn * 11193156Snwhitehorn * Redistribution and use in source and binary forms, with or without 12193156Snwhitehorn * modification, are permitted provided that the following conditions 13193156Snwhitehorn * are met: 14275815Semaste * 1. Redistributions of source code must retain the above copyright 15275815Semaste * notice, this list of conditions and the following disclaimer. 16275815Semaste * 2. Redistributions in binary form must reproduce the above copyright 17275815Semaste * notice, this list of conditions and the following disclaimer in the 18275815Semaste * documentation and/or other materials provided with the distribution. 19275815Semaste * 3. All advertising materials mentioning features or use of this software 20275815Semaste * must display the following acknowledgement: 21275815Semaste * This product includes software developed by Brini. 22275815Semaste * 4. The name of the company nor the name of the author may be used to 23275815Semaste * endorse or promote products derived from this software without specific 24275815Semaste * prior written permission. 25193156Snwhitehorn * 26193156Snwhitehorn * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27227843Smarius * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28227843Smarius * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29227843Smarius * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30193156Snwhitehorn * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31193156Snwhitehorn * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32193156Snwhitehorn * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33193156Snwhitehorn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34193156Snwhitehorn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35193156Snwhitehorn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36193156Snwhitehorn * SUCH DAMAGE. 37193156Snwhitehorn * 38193156Snwhitehorn * $FreeBSD: head/sys/arm/include/armreg.h 249999 2013-04-27 23:07:49Z wkoszek $ 39193156Snwhitehorn */ 40193156Snwhitehorn 41193156Snwhitehorn#ifndef MACHINE_ARMREG_H 42193156Snwhitehorn#define MACHINE_ARMREG_H 43193156Snwhitehorn 44193156Snwhitehorn#define INSN_SIZE 4 45193156Snwhitehorn#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46193156Snwhitehorn#define PSR_MODE 0x0000001f /* mode mask */ 47193156Snwhitehorn#define PSR_USR26_MODE 0x00000000 48193156Snwhitehorn#define PSR_FIQ26_MODE 0x00000001 49193156Snwhitehorn#define PSR_IRQ26_MODE 0x00000002 50193156Snwhitehorn#define PSR_SVC26_MODE 0x00000003 51193156Snwhitehorn#define PSR_USR32_MODE 0x00000010 52193156Snwhitehorn#define PSR_FIQ32_MODE 0x00000011 53193156Snwhitehorn#define PSR_IRQ32_MODE 0x00000012 54193156Snwhitehorn#define PSR_SVC32_MODE 0x00000013 55193156Snwhitehorn#define PSR_ABT32_MODE 0x00000017 56193156Snwhitehorn#define PSR_UND32_MODE 0x0000001b 57193156Snwhitehorn#define PSR_SYS32_MODE 0x0000001f 58193156Snwhitehorn#define PSR_32_MODE 0x00000010 59193156Snwhitehorn#define PSR_FLAGS 0xf0000000 /* flags */ 60193156Snwhitehorn 61193156Snwhitehorn#define PSR_C_bit (1 << 29) /* carry */ 62193156Snwhitehorn 63193156Snwhitehorn/* The high-order byte is always the implementor */ 64193156Snwhitehorn#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65193156Snwhitehorn#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66193156Snwhitehorn#define CPU_ID_DEC 0x44000000 /* 'D' */ 67227843Smarius#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68193156Snwhitehorn#define CPU_ID_TI 0x54000000 /* 'T' */ 69193156Snwhitehorn#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70193156Snwhitehorn 71193156Snwhitehorn/* How to decide what format the CPUID is in. */ 72193156Snwhitehorn#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73193156Snwhitehorn#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74193156Snwhitehorn#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75193156Snwhitehorn 76193156Snwhitehorn/* On ARM3 and ARM6, this byte holds the foundry ID. */ 77193156Snwhitehorn#define CPU_ID_FOUNDRY_MASK 0x00ff0000 78261513Snwhitehorn#define CPU_ID_FOUNDRY_VLSI 0x00560000 79193156Snwhitehorn 80193156Snwhitehorn/* On ARM7 it holds the architecture and variant (sub-model) */ 81193156Snwhitehorn#define CPU_ID_7ARCH_MASK 0x00800000 82193156Snwhitehorn#define CPU_ID_7ARCH_V3 0x00000000 83193156Snwhitehorn#define CPU_ID_7ARCH_V4T 0x00800000 84193156Snwhitehorn#define CPU_ID_7VARIANT_MASK 0x007f0000 85193156Snwhitehorn 86193156Snwhitehorn/* On more recent ARMs, it does the same, but in a different format */ 87193156Snwhitehorn#define CPU_ID_ARCH_MASK 0x000f0000 88193156Snwhitehorn#define CPU_ID_ARCH_V3 0x00000000 89193156Snwhitehorn#define CPU_ID_ARCH_V4 0x00010000 90193156Snwhitehorn#define CPU_ID_ARCH_V4T 0x00020000 91193156Snwhitehorn#define CPU_ID_ARCH_V5 0x00030000 92193156Snwhitehorn#define CPU_ID_ARCH_V5T 0x00040000 93193156Snwhitehorn#define CPU_ID_ARCH_V5TE 0x00050000 94193156Snwhitehorn#define CPU_ID_ARCH_V5TEJ 0x00060000 95193156Snwhitehorn#define CPU_ID_ARCH_V6 0x00070000 96193156Snwhitehorn#define CPU_ID_CPUID_SCHEME 0x000f0000 97193156Snwhitehorn#define CPU_ID_VARIANT_MASK 0x00f00000 98193156Snwhitehorn 99193156Snwhitehorn/* Next three nybbles are part number */ 100193156Snwhitehorn#define CPU_ID_PARTNO_MASK 0x0000fff0 101193156Snwhitehorn 102193156Snwhitehorn/* Intel XScale has sub fields in part number */ 103193156Snwhitehorn#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104193156Snwhitehorn#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105193156Snwhitehorn#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106193156Snwhitehorn 107193156Snwhitehorn/* And finally, the revision number. */ 108193156Snwhitehorn#define CPU_ID_REVISION_MASK 0x0000000f 109193156Snwhitehorn 110193156Snwhitehorn/* Individual CPUs are probably best IDed by everything but the revision. */ 111193156Snwhitehorn#define CPU_ID_CPU_MASK 0xfffffff0 112193156Snwhitehorn 113193156Snwhitehorn/* Fake CPU IDs for ARMs without CP15 */ 114193156Snwhitehorn#define CPU_ID_ARM2 0x41560200 115193156Snwhitehorn#define CPU_ID_ARM250 0x41560250 116193156Snwhitehorn 117193156Snwhitehorn/* Pre-ARM7 CPUs -- [15:12] == 0 */ 118193156Snwhitehorn#define CPU_ID_ARM3 0x41560300 119193156Snwhitehorn#define CPU_ID_ARM600 0x41560600 120193156Snwhitehorn#define CPU_ID_ARM610 0x41560610 121193156Snwhitehorn#define CPU_ID_ARM620 0x41560620 122193156Snwhitehorn 123193156Snwhitehorn/* ARM7 CPUs -- [15:12] == 7 */ 124193156Snwhitehorn#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 125193156Snwhitehorn#define CPU_ID_ARM710 0x41007100 126193156Snwhitehorn#define CPU_ID_ARM7500 0x41027100 127193156Snwhitehorn#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 128193156Snwhitehorn#define CPU_ID_ARM7500FE 0x41077100 129193156Snwhitehorn#define CPU_ID_ARM710T 0x41807100 130193156Snwhitehorn#define CPU_ID_ARM720T 0x41807200 131193156Snwhitehorn#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 132193156Snwhitehorn#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 133193156Snwhitehorn 134193156Snwhitehorn/* Post-ARM7 CPUs */ 135193156Snwhitehorn#define CPU_ID_ARM810 0x41018100 136193156Snwhitehorn#define CPU_ID_ARM920T 0x41129200 137252115Sjhibbits#define CPU_ID_ARM920T_ALT 0x41009200 138252115Sjhibbits#define CPU_ID_ARM922T 0x41029220 139252115Sjhibbits#define CPU_ID_ARM926EJS 0x41069260 140252115Sjhibbits#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 141252115Sjhibbits#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 142193156Snwhitehorn#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 143193156Snwhitehorn#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 144193156Snwhitehorn#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 145193156Snwhitehorn#define CPU_ID_ARM1022ES 0x4105a220 146193156Snwhitehorn#define CPU_ID_ARM1026EJS 0x4106a260 147193156Snwhitehorn#define CPU_ID_ARM1136JS 0x4107b360 148193156Snwhitehorn#define CPU_ID_ARM1136JSR1 0x4117b360 149193156Snwhitehorn#define CPU_ID_ARM1176JZS 0x410fb760 150193156Snwhitehorn#define CPU_ID_CORTEXA8R1 0x411fc080 151193156Snwhitehorn#define CPU_ID_CORTEXA8R2 0x412fc080 152193156Snwhitehorn#define CPU_ID_CORTEXA8R3 0x413fc080 153193156Snwhitehorn#define CPU_ID_CORTEXA9R1 0x411fc090 154193156Snwhitehorn#define CPU_ID_CORTEXA9R2 0x412fc090 155193156Snwhitehorn#define CPU_ID_CORTEXA9R3 0x413fc090 156227843Smarius#define CPU_ID_SA110 0x4401a100 157193156Snwhitehorn#define CPU_ID_SA1100 0x4401a110 158193156Snwhitehorn#define CPU_ID_TI925T 0x54029250 159193156Snwhitehorn#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 160193156Snwhitehorn#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 161193156Snwhitehorn#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 162255378Snwhitehorn 163193156Snwhitehorn/* 164193156Snwhitehorn * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 165193156Snwhitehorn * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 166193156Snwhitehorn */ 167193156Snwhitehorn#ifdef SOC_MV_LOKIPLUS 168193156Snwhitehorn#define CPU_ID_MV88FR571_41 0x00000000 169193156Snwhitehorn#else 170193156Snwhitehorn#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 171193156Snwhitehorn#endif 172193156Snwhitehorn 173193156Snwhitehorn#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ 174276162Sian#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 175193156Snwhitehorn#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ 176193156Snwhitehorn#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 177193156Snwhitehorn/* Marvell's CPUIDs with ARM ID in implementor field */ 178193156Snwhitehorn#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 179193156Snwhitehorn#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 180193156Snwhitehorn#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ 181193156Snwhitehorn 182193156Snwhitehorn#define CPU_ID_FA526 0x66015260 183193156Snwhitehorn#define CPU_ID_FA626TE 0x66056260 184252115Sjhibbits#define CPU_ID_SA1110 0x6901b110 185276162Sian#define CPU_ID_IXP1200 0x6901c120 186252115Sjhibbits#define CPU_ID_80200 0x69052000 187252115Sjhibbits#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 188252115Sjhibbits#define CPU_ID_PXA210 0x69052120 189276162Sian#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 190276162Sian#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 191276162Sian#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 192276162Sian#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 193276162Sian#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 194252115Sjhibbits#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 195276162Sian#define CPU_ID_PXA27X 0x69054110 196276162Sian#define CPU_ID_80321_400 0x69052420 197276162Sian#define CPU_ID_80321_600 0x69052430 198276162Sian#define CPU_ID_80321_400_B0 0x69052c20 199252115Sjhibbits#define CPU_ID_80321_600_B0 0x69052c30 200252115Sjhibbits#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 201193156Snwhitehorn#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 202193156Snwhitehorn#define CPU_ID_81342 0x69056810 203193156Snwhitehorn#define CPU_ID_IXP425 0x690541c0 204193156Snwhitehorn#define CPU_ID_IXP425_533 0x690541c0 205193156Snwhitehorn#define CPU_ID_IXP425_400 0x690541d0 206193156Snwhitehorn#define CPU_ID_IXP425_266 0x690541f0 207193156Snwhitehorn#define CPU_ID_IXP435 0x69054040 208252115Sjhibbits#define CPU_ID_IXP465 0x69054200 209193156Snwhitehorn 210252115Sjhibbits/* ARM3-specific coprocessor 15 registers */ 211252115Sjhibbits#define ARM3_CP15_FLUSH 1 212193156Snwhitehorn#define ARM3_CP15_CONTROL 2 213193156Snwhitehorn#define ARM3_CP15_CACHEABLE 3 214252115Sjhibbits#define ARM3_CP15_UPDATEABLE 4 215193156Snwhitehorn#define ARM3_CP15_DISRUPTIVE 5 216193156Snwhitehorn 217252115Sjhibbits/* ARM3 Control register bits */ 218193156Snwhitehorn#define ARM3_CTL_CACHE_ON 0x00000001 219193156Snwhitehorn#define ARM3_CTL_SHARED 0x00000002 220193156Snwhitehorn#define ARM3_CTL_MONITOR 0x00000004 221193156Snwhitehorn 222193156Snwhitehorn/* CPUID registers */ 223193156Snwhitehorn#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 224 225#define ARM_PFR0_THUMB_MASK 0x000000f0 226#define ARM_PFR0_THUMB 0x10 227#define ARM_PFR0_THUMB2 0x30 228 229#define ARM_PFR0_JAZELLE_MASK 0x00000f00 230#define ARM_PFR0_THUMBEE_MASK 0x0000f000 231 232#define ARM_PFR1_ARMV4_MASK 0x0000000f 233#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 234#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 235 236/* 237 * Post-ARM3 CP15 registers: 238 * 239 * 1 Control register 240 * 241 * 2 Translation Table Base 242 * 243 * 3 Domain Access Control 244 * 245 * 4 Reserved 246 * 247 * 5 Fault Status 248 * 249 * 6 Fault Address 250 * 251 * 7 Cache/write-buffer Control 252 * 253 * 8 TLB Control 254 * 255 * 9 Cache Lockdown 256 * 257 * 10 TLB Lockdown 258 * 259 * 11 Reserved 260 * 261 * 12 Reserved 262 * 263 * 13 Process ID (for FCSE) 264 * 265 * 14 Reserved 266 * 267 * 15 Implementation Dependent 268 */ 269 270/* Some of the definitions below need cleaning up for V3/V4 architectures */ 271 272/* CPU control register (CP15 register 1) */ 273#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 274#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 275#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 276#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 277#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 278#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 279#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 280#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 281#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 282#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 283#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 284#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 285#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 286#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 287#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 288#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 289#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 290#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 291#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 292#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 293 294#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 295 296/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 297#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 298#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 299#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 300#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 301#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 302#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 303#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 304#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 305 306/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 307#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 308 /* This is an undocumented flag 309 * used to work around a cache bug 310 * in r0 steppings. See errata 311 * 364296. 312 */ 313/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 314#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 315#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 316#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 317#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 318 319/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 320#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 321#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 322/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 323#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 324#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 325#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 326#define XSCALE_AUXCTL_MD_MASK 0x00000030 327 328/* Xscale Core 3 only */ 329#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 330 331/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 332#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 333#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 334#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 335#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 336#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 337#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 338#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 339#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 340#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 341#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 342 343/* Cache type register definitions */ 344#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 345#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 346#define CPU_CT_S (1U << 24) /* split cache */ 347#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 348#define CPU_CT_FORMAT(x) ((x) >> 29) 349 350#define CPU_CT_CTYPE_WT 0 /* write-through */ 351#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 352#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 353#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 354#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 355 356#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 357#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 358#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 359#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 360 361#define CPU_CT_ARMV7 0x4 362/* ARM v7 Cache type definitions */ 363#define CPUV7_CT_CTYPE_WT (1 << 31) 364#define CPUV7_CT_CTYPE_WB (1 << 30) 365#define CPUV7_CT_CTYPE_RA (1 << 29) 366#define CPUV7_CT_CTYPE_WA (1 << 28) 367 368#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 369#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 370#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 371 372#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 373#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 374#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 375#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 376 377#define CACHE_ICACHE 1 378#define CACHE_DCACHE 2 379#define CACHE_SEP_CACHE 3 380#define CACHE_UNI_CACHE 4 381 382/* Fault status register definitions */ 383 384#define FAULT_TYPE_MASK 0x0f 385#define FAULT_USER 0x10 386 387#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 388#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 389#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 390#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 391#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 392#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 393#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 394#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 395#define FAULT_ALIGN_0 0x01 /* Alignment */ 396#define FAULT_ALIGN_1 0x03 /* Alignment */ 397#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 398#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 399#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 400#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 401#define FAULT_PERM_S 0x0d /* Permission -- Section */ 402#define FAULT_PERM_P 0x0f /* Permission -- Page */ 403 404#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 405 406/* 407 * Address of the vector page, low and high versions. 408 */ 409#ifndef __ASSEMBLER__ 410#define ARM_VECTORS_LOW 0x00000000U 411#define ARM_VECTORS_HIGH 0xffff0000U 412#else 413#define ARM_VECTORS_LOW 0 414#define ARM_VECTORS_HIGH 0xffff0000 415#endif 416 417/* 418 * ARM Instructions 419 * 420 * 3 3 2 2 2 421 * 1 0 9 8 7 0 422 * +-------+-------------------------------------------------------+ 423 * | cond | instruction dependant | 424 * |c c c c| | 425 * +-------+-------------------------------------------------------+ 426 */ 427 428#define INSN_SIZE 4 /* Always 4 bytes */ 429#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 430#define INSN_COND_AL 0xe0000000 /* Always condition */ 431 432#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 433 434#endif /* !MACHINE_ARMREG_H */ 435