armreg.h revision 161592
1259268Spfg/* $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $ */ 2255107Spfg 3259268Spfg/*- 4259268Spfg * Copyright (c) 1998, 2001 Ben Harris 5259268Spfg * Copyright (c) 1994-1996 Mark Brinicombe. 6259268Spfg * Copyright (c) 1994 Brini. 7259694Spfg * All rights reserved. 8259694Spfg * 9259694Spfg * This code is derived from software written for Brini by Mark Brinicombe 10259694Spfg * 11259694Spfg * Redistribution and use in source and binary forms, with or without 12259694Spfg * modification, are permitted provided that the following conditions 13259694Spfg * are met: 14259694Spfg * 1. Redistributions of source code must retain the above copyright 15259694Spfg * notice, this list of conditions and the following disclaimer. 16259694Spfg * 2. Redistributions in binary form must reproduce the above copyright 17259694Spfg * notice, this list of conditions and the following disclaimer in the 18259694Spfg * documentation and/or other materials provided with the distribution. 19259694Spfg * 3. All advertising materials mentioning features or use of this software 20259694Spfg * must display the following acknowledgement: 21259694Spfg * This product includes software developed by Brini. 22259694Spfg * 4. The name of the company nor the name of the author may be used to 23259694Spfg * endorse or promote products derived from this software without specific 24259694Spfg * prior written permission. 25259694Spfg * 26259694Spfg * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27259694Spfg * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28259694Spfg * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29259694Spfg * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30259694Spfg * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31259694Spfg * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32259694Spfg * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33259694Spfg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34259694Spfg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35259694Spfg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36259694Spfg * SUCH DAMAGE. 37259694Spfg * 38259694Spfg * $FreeBSD: head/sys/arm/include/armreg.h 161592 2006-08-24 23:51:28Z cognet $ 39259694Spfg */ 40259694Spfg 41259694Spfg#ifndef MACHINE_ARMREG_H 42259694Spfg#define MACHINE_ARMREG_H 43259694Spfg#define INSN_SIZE 4 44259694Spfg#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 45259694Spfg#define PSR_MODE 0x0000001f /* mode mask */ 46259694Spfg#define PSR_USR26_MODE 0x00000000 47259694Spfg#define PSR_FIQ26_MODE 0x00000001 48260139Spfg#define PSR_IRQ26_MODE 0x00000002 49260139Spfg#define PSR_SVC26_MODE 0x00000003 50260139Spfg#define PSR_USR32_MODE 0x00000010 51260139Spfg#define PSR_FIQ32_MODE 0x00000011 52260139Spfg#define PSR_IRQ32_MODE 0x00000012 53260139Spfg#define PSR_SVC32_MODE 0x00000013 54260139Spfg#define PSR_ABT32_MODE 0x00000017 55260139Spfg#define PSR_UND32_MODE 0x0000001b 56260139Spfg#define PSR_SYS32_MODE 0x0000001f 57260139Spfg#define PSR_32_MODE 0x00000010 58260139Spfg#define PSR_FLAGS 0xf0000000 /* flags */ 59260139Spfg 60260139Spfg#define PSR_C_bit (1 << 29) /* carry */ 61260139Spfg 62260074Spfg/* The high-order byte is always the implementor */ 63260074Spfg#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 64260074Spfg#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 65260074Spfg#define CPU_ID_DEC 0x44000000 /* 'D' */ 66260074Spfg#define CPU_ID_INTEL 0x69000000 /* 'i' */ 67260074Spfg#define CPU_ID_TI 0x54000000 /* 'T' */ 68260455Spfg 69260455Spfg/* How to decide what format the CPUID is in. */ 70260455Spfg#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 71260455Spfg#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 72260455Spfg#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 73260455Spfg 74259268Spfg/* On ARM3 and ARM6, this byte holds the foundry ID. */ 75259268Spfg#define CPU_ID_FOUNDRY_MASK 0x00ff0000 76255107Spfg#define CPU_ID_FOUNDRY_VLSI 0x00560000 77255107Spfg 78255107Spfg/* On ARM7 it holds the architecture and variant (sub-model) */ 79255107Spfg#define CPU_ID_7ARCH_MASK 0x00800000 80259583Spfg#define CPU_ID_7ARCH_V3 0x00000000 81259563Spfg#define CPU_ID_7ARCH_V4T 0x00800000 82259563Spfg#define CPU_ID_7VARIANT_MASK 0x007f0000 83259563Spfg 84259563Spfg/* On more recent ARMs, it does the same, but in a different format */ 85259563Spfg#define CPU_ID_ARCH_MASK 0x000f0000 86259947Spfg#define CPU_ID_ARCH_V3 0x00000000 87259947Spfg#define CPU_ID_ARCH_V4 0x00010000 88259947Spfg#define CPU_ID_ARCH_V4T 0x00020000 89259947Spfg#define CPU_ID_ARCH_V5 0x00030000 90259947Spfg#define CPU_ID_ARCH_V5T 0x00040000 91259947Spfg#define CPU_ID_ARCH_V5TE 0x00050000 92259947Spfg#define CPU_ID_VARIANT_MASK 0x00f00000 93259947Spfg 94259583Spfg/* Next three nybbles are part number */ 95259583Spfg#define CPU_ID_PARTNO_MASK 0x0000fff0 96259583Spfg 97259583Spfg/* Intel XScale has sub fields in part number */ 98259583Spfg#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 99259583Spfg#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 100259583Spfg#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 101259583Spfg 102259268Spfg/* And finally, the revision number. */ 103259268Spfg#define CPU_ID_REVISION_MASK 0x0000000f 104259268Spfg 105259268Spfg/* Individual CPUs are probably best IDed by everything but the revision. */ 106259268Spfg#define CPU_ID_CPU_MASK 0xfffffff0 107259268Spfg 108259268Spfg/* Fake CPU IDs for ARMs without CP15 */ 109259268Spfg#define CPU_ID_ARM2 0x41560200 110259268Spfg#define CPU_ID_ARM250 0x41560250 111259268Spfg 112259268Spfg/* Pre-ARM7 CPUs -- [15:12] == 0 */ 113259268Spfg#define CPU_ID_ARM3 0x41560300 114259268Spfg#define CPU_ID_ARM600 0x41560600 115259268Spfg#define CPU_ID_ARM610 0x41560610 116259268Spfg#define CPU_ID_ARM620 0x41560620 117259947Spfg 118259947Spfg/* ARM7 CPUs -- [15:12] == 7 */ 119259947Spfg#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 120259947Spfg#define CPU_ID_ARM710 0x41007100 121259947Spfg#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ 122259947Spfg#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 123259947Spfg#define CPU_ID_ARM7500FE 0x41077100 124259947Spfg#define CPU_ID_ARM710T 0x41807100 125259583Spfg#define CPU_ID_ARM720T 0x41807200 126259583Spfg#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 127259583Spfg#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 128259583Spfg 129259583Spfg/* Post-ARM7 CPUs */ 130259583Spfg#define CPU_ID_ARM810 0x41018100 131259268Spfg#define CPU_ID_ARM920T 0x41129200 132259268Spfg#define CPU_ID_ARM920T_ALT 0x41009200 133259268Spfg#define CPU_ID_ARM922T 0x41029220 134259268Spfg#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 135259268Spfg#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 136251212Spfg#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 137251212Spfg#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 138251212Spfg#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 139251212Spfg#define CPU_ID_ARM1022ES 0x4105a220 140251212Spfg#define CPU_ID_SA110 0x4401a100 141221282Smm#define CPU_ID_SA1100 0x4401a110 142221282Smm#define CPU_ID_TI925T 0x54029250 143221282Smm#define CPU_ID_SA1110 0x6901b110 144221282Smm#define CPU_ID_IXP1200 0x6901c120 145221282Smm#define CPU_ID_80200 0x69052000 146221282Smm#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 147221282Smm#define CPU_ID_PXA210 0x69052120 148251212Spfg#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 149251212Spfg#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 150251212Spfg#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 151251212Spfg#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 152251212Spfg#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 153251212Spfg#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 154260230Spfg#define CPU_ID_80321_400 0x69052420 155260230Spfg#define CPU_ID_80321_600 0x69052430 156260230Spfg#define CPU_ID_80321_400_B0 0x69052c20 157260230Spfg#define CPU_ID_80321_600_B0 0x69052c30 158260230Spfg#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 159259694Spfg#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 160259268Spfg#define CPU_ID_IXP425_533 0x690541c0 161259268Spfg#define CPU_ID_IXP425_400 0x690541d0 162259268Spfg#define CPU_ID_IXP425_266 0x690541f0 163259268Spfg 164259268Spfg/* ARM3-specific coprocessor 15 registers */ 165259268Spfg#define ARM3_CP15_FLUSH 1 166259268Spfg#define ARM3_CP15_CONTROL 2 167259268Spfg#define ARM3_CP15_CACHEABLE 3 168259268Spfg#define ARM3_CP15_UPDATEABLE 4 169259268Spfg#define ARM3_CP15_DISRUPTIVE 5 170259268Spfg 171259268Spfg/* ARM3 Control register bits */ 172259268Spfg#define ARM3_CTL_CACHE_ON 0x00000001 173259268Spfg#define ARM3_CTL_SHARED 0x00000002 174259268Spfg#define ARM3_CTL_MONITOR 0x00000004 175259268Spfg 176259268Spfg/* 177259268Spfg * Post-ARM3 CP15 registers: 178259268Spfg * 179259268Spfg * 1 Control register 180259268Spfg * 181259268Spfg * 2 Translation Table Base 182259268Spfg * 183259268Spfg * 3 Domain Access Control 184259268Spfg * 185259268Spfg * 4 Reserved 186259268Spfg * 187259268Spfg * 5 Fault Status 188259268Spfg * 189259268Spfg * 6 Fault Address 190259268Spfg * 191259268Spfg * 7 Cache/write-buffer Control 192259268Spfg * 193259268Spfg * 8 TLB Control 194259268Spfg * 195259268Spfg * 9 Cache Lockdown 196259268Spfg * 197259268Spfg * 10 TLB Lockdown 198259268Spfg * 199259268Spfg * 11 Reserved 200259268Spfg * 201259268Spfg * 12 Reserved 202259268Spfg * 203259268Spfg * 13 Process ID (for FCSE) 204259268Spfg * 205259268Spfg * 14 Reserved 206259268Spfg * 207259268Spfg * 15 Implementation Dependent 208259268Spfg */ 209259268Spfg 210259563Spfg/* Some of the definitions below need cleaning up for V3/V4 architectures */ 211259563Spfg 212259563Spfg/* CPU control register (CP15 register 1) */ 213259563Spfg#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 214259563Spfg#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 215259563Spfg#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 216237406Spfg#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 217237406Spfg#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 218237406Spfg#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 219237406Spfg#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 220237406Spfg#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 221237406Spfg#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 222237406Spfg#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 223237406Spfg#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 224237406Spfg#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 225237406Spfg#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 226237406Spfg#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 227237406Spfg#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 228221282Smm#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 229221282Smm 230221282Smm#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 231221282Smm 232251212Spfg/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 233251212Spfg#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 234251212Spfg#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 235251212Spfg#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 236251212Spfg#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 237251212Spfg#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 238259694Spfg#define XSCALE_AUXCTL_MD_MASK 0x00000030 239259268Spfg 240259268Spfg/* Cache type register definitions */ 241259268Spfg#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 242259268Spfg#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 243259268Spfg#define CPU_CT_S (1U << 24) /* split cache */ 244259268Spfg#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 245259268Spfg 246259268Spfg#define CPU_CT_CTYPE_WT 0 /* write-through */ 247259268Spfg#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 248259268Spfg#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 249259268Spfg#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 250259268Spfg#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 251251212Spfg 252251212Spfg#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 253251212Spfg#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 254251212Spfg#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 255251212Spfg#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 256221282Smm 257221282Smm/* Fault status register definitions */ 258221282Smm 259221282Smm#define FAULT_TYPE_MASK 0x0f 260221282Smm#define FAULT_USER 0x10 261221282Smm 262221282Smm#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 263221282Smm#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 264221282Smm#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 265221282Smm#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 266221282Smm#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 267221282Smm#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 268221282Smm#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 269221282Smm#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 270221282Smm#define FAULT_ALIGN_0 0x01 /* Alignment */ 271221282Smm#define FAULT_ALIGN_1 0x03 /* Alignment */ 272221282Smm#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 273251212Spfg#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 274251212Spfg#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 275251212Spfg#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 276251212Spfg#define FAULT_PERM_S 0x0d /* Permission -- Section */ 277251212Spfg#define FAULT_PERM_P 0x0f /* Permission -- Page */ 278251212Spfg 279251212Spfg#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 280251212Spfg 281251212Spfg/* 282251212Spfg * Address of the vector page, low and high versions. 283251212Spfg */ 284251212Spfg#define ARM_VECTORS_LOW 0x00000000U 285251212Spfg#define ARM_VECTORS_HIGH 0xffff0000U 286251212Spfg 287251212Spfg/* 288251212Spfg * ARM Instructions 289251212Spfg * 290251212Spfg * 3 3 2 2 2 291251212Spfg * 1 0 9 8 7 0 292251212Spfg * +-------+-------------------------------------------------------+ 293251212Spfg * | cond | instruction dependant | 294251212Spfg * |c c c c| | 295251212Spfg * +-------+-------------------------------------------------------+ 296251212Spfg */ 297251212Spfg 298251212Spfg#define INSN_SIZE 4 /* Always 4 bytes */ 299251212Spfg#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 300251212Spfg#define INSN_COND_AL 0xe0000000 /* Always condition */ 301251212Spfg 302251212Spfg#endif /* !MACHINE_ARMREG_H */ 303251212Spfg