1242711Ssjg/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2242711Ssjg 3264483Sjmmv/*- 4264483Sjmmv * Copyright (c) 1998, 2001 Ben Harris 5259962Sjmmv * Copyright (c) 1994-1996 Mark Brinicombe. 6259962Sjmmv * Copyright (c) 1994 Brini. 7242711Ssjg * All rights reserved. 8264483Sjmmv * 9264483Sjmmv * This code is derived from software written for Brini by Mark Brinicombe 10264483Sjmmv * 11242711Ssjg * Redistribution and use in source and binary forms, with or without 12259962Sjmmv * modification, are permitted provided that the following conditions 13259962Sjmmv * are met: 14259962Sjmmv * 1. Redistributions of source code must retain the above copyright 15259962Sjmmv * notice, this list of conditions and the following disclaimer. 16259962Sjmmv * 2. Redistributions in binary form must reproduce the above copyright 17259962Sjmmv * notice, this list of conditions and the following disclaimer in the 18259962Sjmmv * documentation and/or other materials provided with the distribution. 19259962Sjmmv * 3. All advertising materials mentioning features or use of this software 20259962Sjmmv * must display the following acknowledgement: 21259962Sjmmv * This product includes software developed by Brini. 22259962Sjmmv * 4. The name of the company nor the name of the author may be used to 23259962Sjmmv * endorse or promote products derived from this software without specific 24242711Ssjg * prior written permission. 25259962Sjmmv * 26259962Sjmmv * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27259962Sjmmv * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28259962Sjmmv * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29259962Sjmmv * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30242711Ssjg * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31259962Sjmmv * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32259962Sjmmv * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33259962Sjmmv * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34259962Sjmmv * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35259962Sjmmv * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36259962Sjmmv * SUCH DAMAGE. 37259962Sjmmv * 38259962Sjmmv * $FreeBSD: releng/10.3/sys/arm/include/armreg.h 283335 2015-05-23 22:48:54Z ian $ 39259962Sjmmv */ 40259962Sjmmv 41259962Sjmmv#ifndef MACHINE_ARMREG_H 42242711Ssjg#define MACHINE_ARMREG_H 43259962Sjmmv 44259962Sjmmv#include <machine/acle-compat.h> 45259962Sjmmv 46259962Sjmmv#define INSN_SIZE 4 47259962Sjmmv#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 48259962Sjmmv#define PSR_MODE 0x0000001f /* mode mask */ 49242711Ssjg#define PSR_USR32_MODE 0x00000010 50259962Sjmmv#define PSR_FIQ32_MODE 0x00000011 51259962Sjmmv#define PSR_IRQ32_MODE 0x00000012 52259962Sjmmv#define PSR_SVC32_MODE 0x00000013 53259962Sjmmv#define PSR_MON32_MODE 0x00000016 54259962Sjmmv#define PSR_ABT32_MODE 0x00000017 55259962Sjmmv#define PSR_HYP32_MODE 0x0000001a 56259962Sjmmv#define PSR_UND32_MODE 0x0000001b 57259962Sjmmv#define PSR_SYS32_MODE 0x0000001f 58259962Sjmmv#define PSR_32_MODE 0x00000010 59259962Sjmmv#define PSR_T 0x00000020 /* Instruction set bit */ 60259962Sjmmv#define PSR_F 0x00000040 /* FIQ disable bit */ 61259962Sjmmv#define PSR_I 0x00000080 /* IRQ disable bit */ 62259962Sjmmv#define PSR_A 0x00000100 /* Imprecise abort bit */ 63259962Sjmmv#define PSR_E 0x00000200 /* Data endianess bit */ 64259962Sjmmv#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 65259962Sjmmv#define PSR_J 0x01000000 /* Java bit */ 66259962Sjmmv#define PSR_Q 0x08000000 /* Sticky overflow bit */ 67259962Sjmmv#define PSR_V 0x10000000 /* Overflow bit */ 68259962Sjmmv#define PSR_C 0x20000000 /* Carry bit */ 69259962Sjmmv#define PSR_Z 0x40000000 /* Zero bit */ 70259962Sjmmv#define PSR_N 0x80000000 /* Negative bit */ 71259962Sjmmv#define PSR_FLAGS 0xf0000000 /* Flags mask. */ 72242711Ssjg 73242711Ssjg/* The high-order byte is always the implementor */ 74242711Ssjg#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 75270905Sngie#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 76259962Sjmmv#define CPU_ID_DEC 0x44000000 /* 'D' */ 77242711Ssjg#define CPU_ID_INTEL 0x69000000 /* 'i' */ 78242711Ssjg#define CPU_ID_TI 0x54000000 /* 'T' */ 79242711Ssjg#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 80259962Sjmmv 81259962Sjmmv/* How to decide what format the CPUID is in. */ 82259962Sjmmv#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 83259962Sjmmv#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 84259962Sjmmv#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 85259962Sjmmv 86242711Ssjg/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 87242711Ssjg#define CPU_ID_ARCH_MASK 0x000f0000 88242711Ssjg#define CPU_ID_ARCH_V3 0x00000000 89270905Sngie#define CPU_ID_ARCH_V4 0x00010000 90259962Sjmmv#define CPU_ID_ARCH_V4T 0x00020000 91242711Ssjg#define CPU_ID_ARCH_V5 0x00030000 92242711Ssjg#define CPU_ID_ARCH_V5T 0x00040000 93242711Ssjg#define CPU_ID_ARCH_V5TE 0x00050000 94259962Sjmmv#define CPU_ID_ARCH_V5TEJ 0x00060000 95259962Sjmmv#define CPU_ID_ARCH_V6 0x00070000 96259962Sjmmv#define CPU_ID_CPUID_SCHEME 0x000f0000 97259962Sjmmv#define CPU_ID_VARIANT_MASK 0x00f00000 98259962Sjmmv 99259962Sjmmv/* Next three nybbles are part number */ 100242711Ssjg#define CPU_ID_PARTNO_MASK 0x0000fff0 101271298Sngie 102271298Sngie/* Intel XScale has sub fields in part number */ 103271298Sngie#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104271298Sngie#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105259962Sjmmv#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106259962Sjmmv 107271298Sngie/* And finally, the revision number. */ 108271298Sngie#define CPU_ID_REVISION_MASK 0x0000000f 109271298Sngie 110242711Ssjg/* Individual CPUs are probably best IDed by everything but the revision. */ 111242711Ssjg#define CPU_ID_CPU_MASK 0xfffffff0 112242711Ssjg 113242711Ssjg/* ARM9 and later CPUs */ 114242711Ssjg#define CPU_ID_ARM920T 0x41129200 115259962Sjmmv#define CPU_ID_ARM920T_ALT 0x41009200 116259962Sjmmv#define CPU_ID_ARM922T 0x41029220 117259962Sjmmv#define CPU_ID_ARM926EJS 0x41069260 118259962Sjmmv#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 119259962Sjmmv#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 120259962Sjmmv#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 121259962Sjmmv#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 122259962Sjmmv#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 123259962Sjmmv#define CPU_ID_ARM1022ES 0x4105a220 124259962Sjmmv#define CPU_ID_ARM1026EJS 0x4106a260 125259962Sjmmv#define CPU_ID_ARM1136JS 0x4107b360 126259962Sjmmv#define CPU_ID_ARM1136JSR1 0x4117b360 127259962Sjmmv#define CPU_ID_ARM1176JZS 0x410fb760 128259962Sjmmv#define CPU_ID_CORTEXA7 0x410fc070 129259962Sjmmv#define CPU_ID_CORTEXA8R1 0x411fc080 130259962Sjmmv#define CPU_ID_CORTEXA8R2 0x412fc080 131259962Sjmmv#define CPU_ID_CORTEXA8R3 0x413fc080 132259962Sjmmv#define CPU_ID_CORTEXA9R1 0x411fc090 133259962Sjmmv#define CPU_ID_CORTEXA9R2 0x412fc090 134259962Sjmmv#define CPU_ID_CORTEXA9R3 0x413fc090 135259962Sjmmv#define CPU_ID_CORTEXA15R0 0x410fc0f0 136259962Sjmmv#define CPU_ID_CORTEXA15R1 0x411fc0f0 137259962Sjmmv#define CPU_ID_CORTEXA15R2 0x412fc0f0 138259962Sjmmv#define CPU_ID_CORTEXA15R3 0x413fc0f0 139259962Sjmmv#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ 140259962Sjmmv#define CPU_ID_TI925T 0x54029250 141259962Sjmmv#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 142259962Sjmmv#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 143259962Sjmmv#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 144259962Sjmmv 145259962Sjmmv/* 146259962Sjmmv * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 147259962Sjmmv * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 148259962Sjmmv */ 149259962Sjmmv#ifdef SOC_MV_LOKIPLUS 150259962Sjmmv#define CPU_ID_MV88FR571_41 0x00000000 151259962Sjmmv#else 152259962Sjmmv#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 153259962Sjmmv#endif 154259962Sjmmv 155259962Sjmmv#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 156259962Sjmmv#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 157259962Sjmmv/* Marvell's CPUIDs with ARM ID in implementor field */ 158259962Sjmmv#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 159259962Sjmmv 160259962Sjmmv#define CPU_ID_FA526 0x66015260 161259962Sjmmv#define CPU_ID_FA626TE 0x66056260 162259962Sjmmv#define CPU_ID_80200 0x69052000 163259962Sjmmv#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 164259962Sjmmv#define CPU_ID_PXA210 0x69052120 165259962Sjmmv#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 166259962Sjmmv#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 167259962Sjmmv#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 168259962Sjmmv#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 169259962Sjmmv#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 170259962Sjmmv#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 171259962Sjmmv#define CPU_ID_PXA27X 0x69054110 172259962Sjmmv#define CPU_ID_80321_400 0x69052420 173259962Sjmmv#define CPU_ID_80321_600 0x69052430 174259962Sjmmv#define CPU_ID_80321_400_B0 0x69052c20 175259962Sjmmv#define CPU_ID_80321_600_B0 0x69052c30 176259962Sjmmv#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 177259962Sjmmv#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 178#define CPU_ID_81342 0x69056810 179#define CPU_ID_IXP425 0x690541c0 180#define CPU_ID_IXP425_533 0x690541c0 181#define CPU_ID_IXP425_400 0x690541d0 182#define CPU_ID_IXP425_266 0x690541f0 183#define CPU_ID_IXP435 0x69054040 184#define CPU_ID_IXP465 0x69054200 185 186/* CPUID registers */ 187#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 188 189#define ARM_PFR0_THUMB_MASK 0x000000f0 190#define ARM_PFR0_THUMB 0x10 191#define ARM_PFR0_THUMB2 0x30 192 193#define ARM_PFR0_JAZELLE_MASK 0x00000f00 194#define ARM_PFR0_THUMBEE_MASK 0x0000f000 195 196#define ARM_PFR1_ARMV4_MASK 0x0000000f 197#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 198#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 199 200/* 201 * Post-ARM3 CP15 registers: 202 * 203 * 1 Control register 204 * 205 * 2 Translation Table Base 206 * 207 * 3 Domain Access Control 208 * 209 * 4 Reserved 210 * 211 * 5 Fault Status 212 * 213 * 6 Fault Address 214 * 215 * 7 Cache/write-buffer Control 216 * 217 * 8 TLB Control 218 * 219 * 9 Cache Lockdown 220 * 221 * 10 TLB Lockdown 222 * 223 * 11 Reserved 224 * 225 * 12 Reserved 226 * 227 * 13 Process ID (for FCSE) 228 * 229 * 14 Reserved 230 * 231 * 15 Implementation Dependent 232 */ 233 234/* Some of the definitions below need cleaning up for V3/V4 architectures */ 235 236/* CPU control register (CP15 register 1) */ 237#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 238#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 239#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 240#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 241#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 242#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 243#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 244#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 245#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 246#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 247#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 248#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ 249#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 250#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 251#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 252#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 253#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 254#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ 255#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 256#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 257#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 258#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 259#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 260#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 261#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 262#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 263#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 264#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 265 266#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 267 268/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 269#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 270#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 271#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 272#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 273#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 274#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 275#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 276#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 277 278/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 279#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 280 /* This is an undocumented flag 281 * used to work around a cache bug 282 * in r0 steppings. See errata 283 * 364296. 284 */ 285/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 286#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 287#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 288#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 289#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 290 291/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 292#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 293#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 294/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 295#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 296#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 297#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 298#define XSCALE_AUXCTL_MD_MASK 0x00000030 299 300/* Xscale Core 3 only */ 301#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 302 303/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 304#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 305#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 306#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 307#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 308#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 309#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 310#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 311#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 312#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 313#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 314 315/* Cache type register definitions */ 316#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 317#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 318#define CPU_CT_S (1U << 24) /* split cache */ 319#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 320#define CPU_CT_FORMAT(x) ((x) >> 29) 321/* Cache type register definitions for ARM v7 */ 322#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 323#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 324 325#define CPU_CT_CTYPE_WT 0 /* write-through */ 326#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 327#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 328#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 329#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 330 331#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 332#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 333#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 334#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 335 336#define CPU_CT_ARMV7 0x4 337/* ARM v7 Cache type definitions */ 338#define CPUV7_CT_CTYPE_WT (1U << 31) 339#define CPUV7_CT_CTYPE_WB (1 << 30) 340#define CPUV7_CT_CTYPE_RA (1 << 29) 341#define CPUV7_CT_CTYPE_WA (1 << 28) 342 343#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 344#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 345#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 346 347#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 348#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 349#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 350#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 351 352#define CACHE_ICACHE 1 353#define CACHE_DCACHE 2 354#define CACHE_SEP_CACHE 3 355#define CACHE_UNI_CACHE 4 356 357/* Fault status register definitions */ 358#define FAULT_USER 0x10 359 360#if __ARM_ARCH < 6 361#define FAULT_TYPE_MASK 0x0f 362#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 363#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 364#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 365#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 366#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 367#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 368#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 369#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 370#define FAULT_ALIGN_0 0x01 /* Alignment */ 371#define FAULT_ALIGN_1 0x03 /* Alignment */ 372#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 373#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 374#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 375#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 376#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 377#define FAULT_PERM_S 0x0d /* Permission -- Section */ 378#define FAULT_PERM_P 0x0f /* Permission -- Page */ 379 380#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 381#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 382#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 383 384#else /* __ARM_ARCH < 6 */ 385 386#define FAULT_ALIGN 0x001 /* Alignment Fault */ 387#define FAULT_DEBUG 0x002 /* Debug Event */ 388#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ 389#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ 390#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ 391#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ 392#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ 393#define FAULT_EA_PREC 0x008 /* External Abort */ 394#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ 395#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ 396#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ 397#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ 398#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ 399#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ 400#define FAULT_TLB_CONFLICT 0x010 /* Permission Fault (L2) */ 401#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ 402#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ 403#define FAULT_PARITY 0x019 /* Parity Error */ 404#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ 405#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ 406 407#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ 408 ((((fsr) & (1 << 10)) >> (10 - 4)))) 409#define FSR_LPAE (1 << 9) /* LPAE indicator */ 410#define FSR_WNR (1 << 11) /* Write-not-Read access */ 411#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 412#define FSR_CM (1 << 13) /* Cache maintenance fault */ 413#endif /* !__ARM_ARCH < 6 */ 414 415/* 416 * Address of the vector page, low and high versions. 417 */ 418#ifndef __ASSEMBLER__ 419#define ARM_VECTORS_LOW 0x00000000U 420#define ARM_VECTORS_HIGH 0xffff0000U 421#else 422#define ARM_VECTORS_LOW 0 423#define ARM_VECTORS_HIGH 0xffff0000 424#endif 425 426/* 427 * ARM Instructions 428 * 429 * 3 3 2 2 2 430 * 1 0 9 8 7 0 431 * +-------+-------------------------------------------------------+ 432 * | cond | instruction dependant | 433 * |c c c c| | 434 * +-------+-------------------------------------------------------+ 435 */ 436 437#define INSN_SIZE 4 /* Always 4 bytes */ 438#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 439#define INSN_COND_AL 0xe0000000 /* Always condition */ 440 441#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 442 443#endif /* !MACHINE_ARMREG_H */ 444