1226584Sdim/*- 2226584Sdim * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3226584Sdim * All rights reserved. 4226584Sdim * 5226584Sdim * Redistribution and use in source and binary forms, with or without 6226584Sdim * modification, are permitted provided that the following conditions 7226584Sdim * are met: 8226584Sdim * 1. Redistributions of source code must retain the above copyright 9226584Sdim * notice, this list of conditions and the following disclaimer. 10226584Sdim * 2. Redistributions in binary form must reproduce the above copyright 11226584Sdim * notice, this list of conditions and the following disclaimer in the 12226584Sdim * documentation and/or other materials provided with the distribution. 13226584Sdim * 14263508Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15226584Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16226584Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17226584Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18226584Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19226584Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20226584Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21226584Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22226584Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23226584Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24226584Sdim * SUCH DAMAGE. 25243830Sdim */ 26251662Sdim 27249423Sdim/* 28243830Sdim * Vybrid Family Inter-Integrated Circuit (I2C) 29243830Sdim * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013 30243830Sdim */ 31243830Sdim 32243830Sdim/* 33243830Sdim * This driver is based on the I2C driver for i.MX 34243830Sdim */ 35243830Sdim 36243830Sdim#include <sys/cdefs.h> 37243830Sdim__FBSDID("$FreeBSD: releng/10.3/sys/arm/freescale/vybrid/vf_i2c.c 289666 2015-10-20 21:20:34Z ian $"); 38243830Sdim 39251662Sdim#include <sys/param.h> 40251662Sdim#include <sys/systm.h> 41251662Sdim#include <sys/bus.h> 42251662Sdim#include <sys/kernel.h> 43251662Sdim#include <sys/module.h> 44251662Sdim#include <sys/malloc.h> 45251662Sdim#include <sys/rman.h> 46251662Sdim#include <sys/timeet.h> 47251662Sdim#include <sys/timetc.h> 48251662Sdim 49251662Sdim#include <dev/iicbus/iiconf.h> 50251662Sdim#include <dev/iicbus/iicbus.h> 51251662Sdim 52243830Sdim#include "iicbus_if.h" 53243830Sdim 54243830Sdim#include <dev/fdt/fdt_common.h> 55243830Sdim#include <dev/ofw/openfirm.h> 56243830Sdim#include <dev/ofw/ofw_bus.h> 57243830Sdim#include <dev/ofw/ofw_bus_subr.h> 58243830Sdim 59243830Sdim#include <machine/bus.h> 60243830Sdim#include <machine/fdt.h> 61243830Sdim#include <machine/cpu.h> 62243830Sdim#include <machine/intr.h> 63243830Sdim 64243830Sdim#include <arm/freescale/vybrid/vf_common.h> 65243830Sdim 66243830Sdim#define I2C_IBAD 0x0 /* I2C Bus Address Register */ 67243830Sdim#define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */ 68243830Sdim#define I2C_IBCR 0x2 /* I2C Bus Control Register */ 69243830Sdim#define IBCR_MDIS (1 << 7) /* Module disable. */ 70243830Sdim#define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */ 71243830Sdim#define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */ 72243830Sdim#define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */ 73226584Sdim#define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */ 74226584Sdim#define IBCR_RSTA (1 << 2) /* Repeat Start. */ 75226584Sdim#define IBCR_DMAEN (1 << 1) /* DMA Enable. */ 76226584Sdim#define I2C_IBSR 0x3 /* I2C Bus Status Register */ 77226584Sdim#define IBSR_TCF (1 << 7) /* Transfer complete. */ 78226584Sdim#define IBSR_IAAS (1 << 6) /* Addressed as a slave. */ 79226584Sdim#define IBSR_IBB (1 << 5) /* Bus busy. */ 80226584Sdim#define IBSR_IBAL (1 << 4) /* Arbitration Lost. */ 81226584Sdim#define IBSR_SRW (1 << 2) /* Slave Read/Write. */ 82226584Sdim#define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */ 83226584Sdim#define IBSR_RXAK (1 << 0) /* Received Acknowledge. */ 84226584Sdim#define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */ 85243830Sdim#define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */ 86243830Sdim#define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */ 87226584Sdim#define I2C_IBDBG 0x6 /* I2C Bus Debug Register */ 88226584Sdim 89226584Sdim#ifdef DEBUG 90226584Sdim#define vf_i2c_dbg(_sc, fmt, args...) \ 91226584Sdim device_printf((_sc)->dev, fmt, ##args) 92226584Sdim#else 93243830Sdim#define vf_i2c_dbg(_sc, fmt, args...) 94243830Sdim#endif 95243830Sdim 96243830Sdimstatic int i2c_repeated_start(device_t, u_char, int); 97243830Sdimstatic int i2c_start(device_t, u_char, int); 98243830Sdimstatic int i2c_stop(device_t); 99243830Sdimstatic int i2c_reset(device_t, u_char, u_char, u_char *); 100226584Sdimstatic int i2c_read(device_t, char *, int, int *, int, int); 101226584Sdimstatic int i2c_write(device_t, const char *, int, int *, int); 102226584Sdim 103226584Sdimstruct i2c_softc { 104226584Sdim struct resource *res[2]; 105226584Sdim bus_space_tag_t bst; 106243830Sdim bus_space_handle_t bsh; 107243830Sdim device_t dev; 108243830Sdim device_t iicbus; 109243830Sdim struct mtx mutex; 110243830Sdim}; 111243830Sdim 112243830Sdimstatic struct resource_spec i2c_spec[] = { 113226584Sdim { SYS_RES_MEMORY, 0, RF_ACTIVE }, 114226584Sdim { SYS_RES_IRQ, 0, RF_ACTIVE }, 115226584Sdim { -1, 0 } 116226584Sdim}; 117226584Sdim 118226584Sdimstatic int 119226584Sdimi2c_probe(device_t dev) 120226584Sdim{ 121226584Sdim 122226584Sdim if (!ofw_bus_status_okay(dev)) 123226584Sdim return (ENXIO); 124226584Sdim 125226584Sdim if (!ofw_bus_is_compatible(dev, "fsl,mvf600-i2c")) 126226584Sdim return (ENXIO); 127226584Sdim 128226584Sdim device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)"); 129243830Sdim return (BUS_PROBE_DEFAULT); 130243830Sdim} 131226584Sdim 132226584Sdimstatic int 133226584Sdimi2c_attach(device_t dev) 134226584Sdim{ 135226584Sdim struct i2c_softc *sc; 136226584Sdim 137226584Sdim sc = device_get_softc(dev); 138226584Sdim sc->dev = dev; 139226584Sdim 140226584Sdim mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); 141226584Sdim 142226584Sdim if (bus_alloc_resources(dev, i2c_spec, sc->res)) { 143226584Sdim device_printf(dev, "could not allocate resources\n"); 144226584Sdim return (ENXIO); 145243830Sdim } 146243830Sdim 147263508Sdim /* Memory interface */ 148239462Sdim sc->bst = rman_get_bustag(sc->res[0]); 149226584Sdim sc->bsh = rman_get_bushandle(sc->res[0]); 150226584Sdim 151226584Sdim WRITE1(sc, I2C_IBIC, IBIC_BIIE); 152226584Sdim 153226584Sdim sc->iicbus = device_add_child(dev, "iicbus", -1); 154226584Sdim if (sc->iicbus == NULL) { 155226584Sdim device_printf(dev, "could not add iicbus child"); 156243830Sdim mtx_destroy(&sc->mutex); 157226584Sdim return (ENXIO); 158243830Sdim } 159243830Sdim 160226584Sdim bus_generic_attach(dev); 161249423Sdim 162249423Sdim return (0); 163249423Sdim} 164249423Sdim 165249423Sdim/* Wait for transfer interrupt flag */ 166249423Sdimstatic int 167249423Sdimwait_for_iif(struct i2c_softc *sc) 168249423Sdim{ 169249423Sdim int retry; 170226584Sdim 171226584Sdim retry = 1000; 172226584Sdim while (retry --) { 173226584Sdim if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { 174226584Sdim WRITE1(sc, I2C_IBSR, IBSR_IBIF); 175226584Sdim return (IIC_NOERR); 176243830Sdim } 177243830Sdim DELAY(10); 178263508Sdim } 179263508Sdim 180263508Sdim return (IIC_ETIMEOUT); 181263508Sdim} 182263508Sdim 183263508Sdim/* Wait for free bus */ 184263508Sdimstatic int 185263508Sdimwait_for_nibb(struct i2c_softc *sc) 186226584Sdim{ 187226584Sdim int retry; 188226584Sdim 189226584Sdim retry = 1000; 190226584Sdim while (retry --) { 191 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) 192 return (IIC_NOERR); 193 DELAY(10); 194 } 195 196 return (IIC_ETIMEOUT); 197} 198 199/* Wait for transfer complete+interrupt flag */ 200static int 201wait_for_icf(struct i2c_softc *sc) 202{ 203 int retry; 204 205 retry = 1000; 206 while (retry --) { 207 if (READ1(sc, I2C_IBSR) & IBSR_TCF) { 208 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { 209 WRITE1(sc, I2C_IBSR, IBSR_IBIF); 210 return (IIC_NOERR); 211 } 212 } 213 DELAY(10); 214 } 215 216 return (IIC_ETIMEOUT); 217} 218 219static int 220i2c_repeated_start(device_t dev, u_char slave, int timeout) 221{ 222 struct i2c_softc *sc; 223 int error; 224 int reg; 225 226 sc = device_get_softc(dev); 227 228 vf_i2c_dbg(sc, "i2c repeated start\n"); 229 230 mtx_lock(&sc->mutex); 231 232 WRITE1(sc, I2C_IBAD, slave); 233 234 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) { 235 mtx_unlock(&sc->mutex); 236 return (IIC_EBUSERR); 237 } 238 239 /* Set repeated start condition */ 240 DELAY(10); 241 242 reg = READ1(sc, I2C_IBCR); 243 reg |= (IBCR_RSTA | IBCR_IBIE); 244 WRITE1(sc, I2C_IBCR, reg); 245 246 DELAY(10); 247 248 /* Write target address - LSB is R/W bit */ 249 WRITE1(sc, I2C_IBDR, slave); 250 251 error = wait_for_iif(sc); 252 253 mtx_unlock(&sc->mutex); 254 255 if (error) 256 return (error); 257 258 return (IIC_NOERR); 259} 260 261static int 262i2c_start(device_t dev, u_char slave, int timeout) 263{ 264 struct i2c_softc *sc; 265 int error; 266 int reg; 267 268 sc = device_get_softc(dev); 269 270 vf_i2c_dbg(sc, "i2c start\n"); 271 272 mtx_lock(&sc->mutex); 273 274 WRITE1(sc, I2C_IBAD, slave); 275 276 if (READ1(sc, I2C_IBSR) & IBSR_IBB) { 277 mtx_unlock(&sc->mutex); 278 vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n"); 279 return (IIC_EBUSERR); 280 } 281 282 /* Set start condition */ 283 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE); 284 WRITE1(sc, I2C_IBCR, reg); 285 286 DELAY(100); 287 288 reg |= (IBCR_TXRX); 289 WRITE1(sc, I2C_IBCR, reg); 290 291 /* Write target address - LSB is R/W bit */ 292 WRITE1(sc, I2C_IBDR, slave); 293 294 error = wait_for_iif(sc); 295 296 mtx_unlock(&sc->mutex); 297 if (error) { 298 vf_i2c_dbg(sc, "cant i2c start: iif error\n"); 299 return (error); 300 } 301 302 return (IIC_NOERR); 303} 304 305static int 306i2c_stop(device_t dev) 307{ 308 struct i2c_softc *sc; 309 310 sc = device_get_softc(dev); 311 312 vf_i2c_dbg(sc, "i2c stop\n"); 313 314 mtx_lock(&sc->mutex); 315 316 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE); 317 318 DELAY(100); 319 320 /* Reset controller if bus still busy after STOP */ 321 if (wait_for_nibb(sc) == IIC_ETIMEOUT) { 322 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 323 DELAY(1000); 324 WRITE1(sc, I2C_IBCR, IBCR_NOACK); 325 } 326 mtx_unlock(&sc->mutex); 327 328 return (IIC_NOERR); 329} 330 331static int 332i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 333{ 334 struct i2c_softc *sc; 335 336 sc = device_get_softc(dev); 337 338 vf_i2c_dbg(sc, "i2c reset\n"); 339 340 switch (speed) { 341 case IIC_FAST: 342 case IIC_SLOW: 343 case IIC_UNKNOWN: 344 case IIC_FASTEST: 345 default: 346 break; 347 } 348 349 mtx_lock(&sc->mutex); 350 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 351 352 DELAY(1000); 353 354 WRITE1(sc, I2C_IBFD, 20); 355 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */ 356 357 DELAY(1000); 358 359 mtx_unlock(&sc->mutex); 360 361 return (IIC_NOERR); 362} 363 364static int 365i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 366{ 367 struct i2c_softc *sc; 368 int error; 369 370 sc = device_get_softc(dev); 371 372 vf_i2c_dbg(sc, "i2c read\n"); 373 374 *read = 0; 375 376 mtx_lock(&sc->mutex); 377 378 if (len) { 379 if (len == 1) 380 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ 381 IBCR_NOACK); 382 else 383 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL); 384 385 /* dummy read */ 386 READ1(sc, I2C_IBDR); 387 DELAY(1000); 388 } 389 390 while (*read < len) { 391 error = wait_for_icf(sc); 392 if (error) { 393 mtx_unlock(&sc->mutex); 394 return (error); 395 } 396 397 if ((*read == len - 2) && last) { 398 /* NO ACK on last byte */ 399 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ 400 IBCR_NOACK); 401 } 402 403 if ((*read == len - 1) && last) { 404 /* Transfer done, remove master bit */ 405 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK); 406 } 407 408 *buf++ = READ1(sc, I2C_IBDR); 409 (*read)++; 410 } 411 mtx_unlock(&sc->mutex); 412 413 return (IIC_NOERR); 414} 415 416static int 417i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 418{ 419 struct i2c_softc *sc; 420 int error; 421 422 sc = device_get_softc(dev); 423 424 vf_i2c_dbg(sc, "i2c write\n"); 425 426 *sent = 0; 427 428 mtx_lock(&sc->mutex); 429 while (*sent < len) { 430 431 WRITE1(sc, I2C_IBDR, *buf++); 432 433 error = wait_for_iif(sc); 434 if (error) { 435 mtx_unlock(&sc->mutex); 436 return (error); 437 } 438 439 (*sent)++; 440 } 441 mtx_unlock(&sc->mutex); 442 443 return (IIC_NOERR); 444} 445 446static device_method_t i2c_methods[] = { 447 DEVMETHOD(device_probe, i2c_probe), 448 DEVMETHOD(device_attach, i2c_attach), 449 450 DEVMETHOD(iicbus_callback, iicbus_null_callback), 451 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 452 DEVMETHOD(iicbus_start, i2c_start), 453 DEVMETHOD(iicbus_stop, i2c_stop), 454 DEVMETHOD(iicbus_reset, i2c_reset), 455 DEVMETHOD(iicbus_read, i2c_read), 456 DEVMETHOD(iicbus_write, i2c_write), 457 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 458 459 { 0, 0 } 460}; 461 462static driver_t i2c_driver = { 463 "i2c", 464 i2c_methods, 465 sizeof(struct i2c_softc), 466}; 467 468static devclass_t i2c_devclass; 469 470DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 471DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 472