1257454Sian/*- 2257454Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3257454Sian * All rights reserved. 4257454Sian * 5257454Sian * Redistribution and use in source and binary forms, with or without 6257454Sian * modification, are permitted provided that the following conditions 7257454Sian * are met: 8257454Sian * 1. Redistributions of source code must retain the above copyright 9257454Sian * notice, this list of conditions and the following disclaimer. 10257454Sian * 2. Redistributions in binary form must reproduce the above copyright 11257454Sian * notice, this list of conditions and the following disclaimer in the 12257454Sian * documentation and/or other materials provided with the distribution. 13257454Sian * 14257454Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15257454Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16257454Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17257454Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18257454Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19257454Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20257454Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21257454Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22257454Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23257454Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24257454Sian * SUCH DAMAGE. 25257454Sian * 26257454Sian */ 27257454Sian#include <sys/cdefs.h> 28257454Sian__FBSDID("$FreeBSD: releng/10.3/sys/arm/freescale/imx/imx_sdhci.c 294679 2016-01-24 19:36:49Z ian $"); 29257454Sian 30257454Sian/* 31257454Sian * SDHCI driver glue for Freescale i.MX SoC family. 32257454Sian * 33257454Sian * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34257454Sian */ 35257454Sian 36257454Sian#include <sys/param.h> 37257454Sian#include <sys/systm.h> 38266200Sian#include <sys/types.h> 39257454Sian#include <sys/bus.h> 40266200Sian#include <sys/callout.h> 41257454Sian#include <sys/kernel.h> 42266200Sian#include <sys/lock.h> 43257454Sian#include <sys/malloc.h> 44257454Sian#include <sys/module.h> 45266200Sian#include <sys/mutex.h> 46257454Sian#include <sys/resource.h> 47257454Sian#include <sys/rman.h> 48271051Smarius#include <sys/sysctl.h> 49257454Sian#include <sys/taskqueue.h> 50266200Sian#include <sys/time.h> 51257454Sian 52257454Sian#include <machine/bus.h> 53257454Sian#include <machine/resource.h> 54257454Sian#include <machine/intr.h> 55257454Sian 56266371Sian#include <arm/freescale/imx/imx_ccmvar.h> 57257454Sian 58257454Sian#include <dev/ofw/ofw_bus.h> 59257454Sian#include <dev/ofw/ofw_bus_subr.h> 60257454Sian 61257454Sian#include <dev/mmc/bridge.h> 62257454Sian#include <dev/mmc/mmcreg.h> 63257454Sian#include <dev/mmc/mmcbrvar.h> 64257454Sian 65257454Sian#include <dev/sdhci/sdhci.h> 66257454Sian#include "sdhci_if.h" 67257454Sian 68257454Sianstruct imx_sdhci_softc { 69257454Sian device_t dev; 70257454Sian struct resource * mem_res; 71257454Sian struct resource * irq_res; 72257454Sian void * intr_cookie; 73257454Sian struct sdhci_slot slot; 74266200Sian struct callout r1bfix_callout; 75266200Sian sbintime_t r1bfix_timeout_at; 76257454Sian uint32_t baseclk_hz; 77257454Sian uint32_t sdclockreg_freq_bits; 78257454Sian uint32_t cmd_and_mode; 79257454Sian uint32_t r1bfix_intmask; 80257454Sian uint8_t r1bfix_type; 81257454Sian uint8_t hwtype; 82266198Sian boolean_t force_card_present; 83257454Sian}; 84257454Sian 85257454Sian#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 86257454Sian#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 87257454Sian#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 88257454Sian 89257454Sian#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 90257454Sian#define HWTYPE_ESDHC 1 /* imx5x and earlier. */ 91257454Sian#define HWTYPE_USDHC 2 /* imx6. */ 92257454Sian 93257454Sian#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 94257454Sian#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 95257454Sian#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 96257454Sian#define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 97257454Sian#define SDHC_VEND_IPGEN (1 << 11) 98257454Sian#define SDHC_VEND_HCKEN (1 << 12) 99257454Sian#define SDHC_VEND_PEREN (1 << 13) 100257454Sian 101266198Sian#define SDHC_PRES_STATE 0x24 102266198Sian#define SDHC_PRES_CIHB (1 << 0) 103266198Sian#define SDHC_PRES_CDIHB (1 << 1) 104266198Sian#define SDHC_PRES_DLA (1 << 2) 105266198Sian#define SDHC_PRES_SDSTB (1 << 3) 106266198Sian#define SDHC_PRES_IPGOFF (1 << 4) 107266198Sian#define SDHC_PRES_HCKOFF (1 << 5) 108266198Sian#define SDHC_PRES_PEROFF (1 << 6) 109266198Sian#define SDHC_PRES_SDOFF (1 << 7) 110266198Sian#define SDHC_PRES_WTA (1 << 8) 111266198Sian#define SDHC_PRES_RTA (1 << 9) 112266198Sian#define SDHC_PRES_BWEN (1 << 10) 113266198Sian#define SDHC_PRES_BREN (1 << 11) 114266198Sian#define SDHC_PRES_RTR (1 << 12) 115266198Sian#define SDHC_PRES_CINST (1 << 16) 116266198Sian#define SDHC_PRES_CDPL (1 << 18) 117266198Sian#define SDHC_PRES_WPSPL (1 << 19) 118266198Sian#define SDHC_PRES_CLSL (1 << 23) 119266198Sian#define SDHC_PRES_DLSL_SHIFT 24 120266198Sian#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 121266198Sian 122257454Sian#define SDHC_PROT_CTRL 0x28 123257454Sian#define SDHC_PROT_LED (1 << 0) 124257454Sian#define SDHC_PROT_WIDTH_1BIT (0 << 1) 125257454Sian#define SDHC_PROT_WIDTH_4BIT (1 << 1) 126257454Sian#define SDHC_PROT_WIDTH_8BIT (2 << 1) 127257454Sian#define SDHC_PROT_WIDTH_MASK (3 << 1) 128257454Sian#define SDHC_PROT_D3CD (1 << 3) 129257454Sian#define SDHC_PROT_EMODE_BIG (0 << 4) 130257454Sian#define SDHC_PROT_EMODE_HALF (1 << 4) 131257454Sian#define SDHC_PROT_EMODE_LITTLE (2 << 4) 132257454Sian#define SDHC_PROT_EMODE_MASK (3 << 4) 133257454Sian#define SDHC_PROT_SDMA (0 << 8) 134257454Sian#define SDHC_PROT_ADMA1 (1 << 8) 135257454Sian#define SDHC_PROT_ADMA2 (2 << 8) 136257454Sian#define SDHC_PROT_ADMA264 (3 << 8) 137257454Sian#define SDHC_PROT_DMA_MASK (3 << 8) 138257454Sian#define SDHC_PROT_CDTL (1 << 6) 139257454Sian#define SDHC_PROT_CDSS (1 << 7) 140257454Sian 141266200Sian#define SDHC_INT_STATUS 0x30 142266200Sian 143257454Sian#define SDHC_CLK_IPGEN (1 << 0) 144257454Sian#define SDHC_CLK_HCKEN (1 << 1) 145257454Sian#define SDHC_CLK_PEREN (1 << 2) 146257454Sian#define SDHC_CLK_DIVISOR_MASK 0x000000f0 147257454Sian#define SDHC_CLK_DIVISOR_SHIFT 4 148257454Sian#define SDHC_CLK_PRESCALE_MASK 0x0000ff00 149257454Sian#define SDHC_CLK_PRESCALE_SHIFT 8 150257454Sian 151257454Sianstatic struct ofw_compat_data compat_data[] = { 152257454Sian {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 153257454Sian {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 154257454Sian {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 155257454Sian {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 156257454Sian {NULL, HWTYPE_NONE}, 157257454Sian};; 158257454Sian 159257454Sianstatic void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable); 160266200Sianstatic void imx_sdhci_r1bfix_func(void *arg); 161257454Sian 162257454Sianstatic inline uint32_t 163257454SianRD4(struct imx_sdhci_softc *sc, bus_size_t off) 164257454Sian{ 165257454Sian 166257454Sian return (bus_read_4(sc->mem_res, off)); 167257454Sian} 168257454Sian 169257454Sianstatic inline void 170257454SianWR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) 171257454Sian{ 172257454Sian 173257454Sian bus_write_4(sc->mem_res, off, val); 174257454Sian} 175257454Sian 176257454Sianstatic uint8_t 177257454Sianimx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 178257454Sian{ 179257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 180257454Sian uint32_t val32, wrk32; 181257454Sian 182257454Sian /* 183257454Sian * Most of the things in the standard host control register are in the 184257454Sian * hardware's wider protocol control register, but some of the bits are 185257454Sian * moved around. 186257454Sian */ 187257454Sian if (off == SDHCI_HOST_CONTROL) { 188257454Sian wrk32 = RD4(sc, SDHC_PROT_CTRL); 189257454Sian val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 190257454Sian SDHCI_CTRL_FORCE_CARD); 191257454Sian switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 192257454Sian case SDHC_PROT_WIDTH_1BIT: 193257454Sian /* Value is already 0. */ 194257454Sian break; 195257454Sian case SDHC_PROT_WIDTH_4BIT: 196257454Sian val32 |= SDHCI_CTRL_4BITBUS; 197257454Sian break; 198257454Sian case SDHC_PROT_WIDTH_8BIT: 199257454Sian val32 |= SDHCI_CTRL_8BITBUS; 200257454Sian break; 201257454Sian } 202257454Sian switch (wrk32 & SDHC_PROT_DMA_MASK) { 203257454Sian case SDHC_PROT_SDMA: 204257454Sian /* Value is already 0. */ 205257454Sian break; 206257454Sian case SDHC_PROT_ADMA1: 207257454Sian /* This value is deprecated, should never appear. */ 208257454Sian break; 209257454Sian case SDHC_PROT_ADMA2: 210257454Sian val32 |= SDHCI_CTRL_ADMA2; 211257454Sian break; 212257454Sian case SDHC_PROT_ADMA264: 213257454Sian val32 |= SDHCI_CTRL_ADMA264; 214257454Sian break; 215257454Sian } 216257454Sian return val32; 217257454Sian } 218257454Sian 219257454Sian /* 220257454Sian * XXX can't find the bus power on/off knob. For now we have to say the 221257454Sian * power is always on and always set to the same voltage. 222257454Sian */ 223257454Sian if (off == SDHCI_POWER_CONTROL) { 224257454Sian return (SDHCI_POWER_ON | SDHCI_POWER_300); 225257454Sian } 226257454Sian 227257454Sian 228257454Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 229257454Sian} 230257454Sian 231257454Sianstatic uint16_t 232257454Sianimx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 233257454Sian{ 234257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 235257454Sian uint32_t val32, wrk32; 236257454Sian 237257454Sian if (sc->hwtype == HWTYPE_USDHC) { 238257454Sian /* 239257454Sian * The USDHC hardware has nothing in the version register, but 240257454Sian * it's v3 compatible with all our translation code. 241257454Sian */ 242257454Sian if (off == SDHCI_HOST_VERSION) { 243257454Sian return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 244257454Sian } 245257454Sian /* 246257454Sian * The USDHC hardware moved the transfer mode bits to the mixed 247257454Sian * control register, fetch them from there. 248257454Sian */ 249257454Sian if (off == SDHCI_TRANSFER_MODE) 250257454Sian return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 251257454Sian 252257454Sian } else if (sc->hwtype == HWTYPE_ESDHC) { 253257454Sian 254257454Sian /* 255257454Sian * The ESDHC hardware has the typical 32-bit combined "command 256257454Sian * and mode" register that we have to cache so that command 257257454Sian * isn't written until after mode. On a read, just retrieve the 258257454Sian * cached values last written. 259257454Sian */ 260257454Sian if (off == SDHCI_TRANSFER_MODE) { 261257454Sian return (sc->cmd_and_mode >> 16); 262257454Sian } else if (off == SDHCI_COMMAND_FLAGS) { 263257454Sian return (sc->cmd_and_mode & 0x0000ffff); 264257454Sian } 265257454Sian } 266257454Sian 267257454Sian /* 268257454Sian * This hardware only manages one slot. Synthesize a slot interrupt 269257454Sian * status register... if there are any enabled interrupts active they 270257454Sian * must be coming from our one and only slot. 271257454Sian */ 272257454Sian if (off == SDHCI_SLOT_INT_STATUS) { 273257454Sian val32 = RD4(sc, SDHCI_INT_STATUS); 274257454Sian val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 275257454Sian return (val32 ? 1 : 0); 276257454Sian } 277257454Sian 278257454Sian /* 279257454Sian * The clock enable bit is in the vendor register and the clock-stable 280257454Sian * bit is in the present state register. Transcribe them as if they 281257454Sian * were in the clock control register where they should be. 282257454Sian * XXX Is it important that we distinguish between "internal" and "card" 283257454Sian * clocks? Probably not; transcribe the card clock status to both bits. 284257454Sian */ 285257454Sian if (off == SDHCI_CLOCK_CONTROL) { 286257454Sian val32 = 0; 287257454Sian wrk32 = RD4(sc, SDHC_VEND_SPEC); 288257454Sian if (wrk32 & SDHC_VEND_FRC_SDCLK_ON) 289257454Sian val32 |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN; 290266198Sian wrk32 = RD4(sc, SDHC_PRES_STATE); 291266198Sian if (wrk32 & SDHC_PRES_SDSTB) 292257454Sian val32 |= SDHCI_CLOCK_INT_STABLE; 293257454Sian val32 |= sc->sdclockreg_freq_bits; 294257454Sian return (val32); 295257454Sian } 296257454Sian 297257454Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 298257454Sian} 299257454Sian 300257454Sianstatic uint32_t 301257454Sianimx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 302257454Sian{ 303257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 304266198Sian uint32_t val32, wrk32; 305257454Sian 306266198Sian val32 = RD4(sc, off); 307266198Sian 308257454Sian /* 309257454Sian * The hardware leaves the base clock frequency out of the capabilities 310257454Sian * register; fill it in. The timeout clock is the same as the active 311257454Sian * output sdclock; we indicate that with a quirk setting so don't 312257454Sian * populate the timeout frequency bits. 313257454Sian * 314257454Sian * XXX Turn off (for now) features the hardware can do but this driver 315257454Sian * doesn't yet handle (1.8v, suspend/resume, etc). 316257454Sian */ 317257454Sian if (off == SDHCI_CAPABILITIES) { 318257454Sian val32 &= ~SDHCI_CAN_VDD_180; 319257454Sian val32 &= ~SDHCI_CAN_DO_SUSPEND; 320257454Sian val32 |= SDHCI_CAN_DO_8BITBUS; 321257454Sian val32 |= (sc->baseclk_hz / 1000000) << SDHCI_CLOCK_BASE_SHIFT; 322257454Sian return (val32); 323257454Sian } 324257454Sian 325266198Sian /* 326266198Sian * The hardware moves bits around in the present state register to make 327266198Sian * room for all 8 data line state bits. To translate, mask out all the 328266198Sian * bits which are not in the same position in both registers (this also 329266198Sian * masks out some freescale-specific bits in locations defined as 330266198Sian * reserved by sdhci), then shift the data line and retune request bits 331266198Sian * down to their standard locations. 332266198Sian */ 333266198Sian if (off == SDHCI_PRESENT_STATE) { 334266198Sian wrk32 = val32; 335266198Sian val32 &= 0x000F0F07; 336266198Sian val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 337266198Sian val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 338266198Sian if (sc->force_card_present) 339266198Sian val32 |= SDHCI_CARD_PRESENT; 340266198Sian return (val32); 341266198Sian } 342257454Sian 343257454Sian /* 344257454Sian * imx_sdhci_intr() can synthesize a DATA_END interrupt following a 345257454Sian * command with an R1B response, mix it into the hardware status. 346257454Sian */ 347257454Sian if (off == SDHCI_INT_STATUS) { 348266198Sian return (val32 | sc->r1bfix_intmask); 349257454Sian } 350257454Sian 351257454Sian return val32; 352257454Sian} 353257454Sian 354257454Sianstatic void 355257454Sianimx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 356257454Sian uint32_t *data, bus_size_t count) 357257454Sian{ 358257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 359257454Sian 360257454Sian bus_read_multi_4(sc->mem_res, off, data, count); 361257454Sian} 362257454Sian 363257454Sianstatic void 364257454Sianimx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 365257454Sian{ 366257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 367257454Sian uint32_t val32; 368257454Sian 369257454Sian /* 370257454Sian * Most of the things in the standard host control register are in the 371257454Sian * hardware's wider protocol control register, but some of the bits are 372257454Sian * moved around. 373257454Sian */ 374257454Sian if (off == SDHCI_HOST_CONTROL) { 375257454Sian val32 = RD4(sc, SDHC_PROT_CTRL); 376257454Sian val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 377257454Sian SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 378257454Sian val32 |= (val & SDHCI_CTRL_LED); 379257454Sian if (val & SDHCI_CTRL_8BITBUS) 380257454Sian val32 |= SDHC_PROT_WIDTH_8BIT; 381257454Sian else 382257454Sian val32 |= (val & SDHCI_CTRL_4BITBUS); 383257454Sian val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 384257454Sian val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 385257454Sian WR4(sc, SDHC_PROT_CTRL, val32); 386257454Sian return; 387257454Sian } 388257454Sian 389257454Sian /* XXX I can't find the bus power on/off knob; do nothing. */ 390257454Sian if (off == SDHCI_POWER_CONTROL) { 391257454Sian return; 392257454Sian } 393257454Sian 394257454Sian val32 = RD4(sc, off & ~3); 395257454Sian val32 &= ~(0xff << (off & 3) * 8); 396257454Sian val32 |= (val << (off & 3) * 8); 397257454Sian 398257454Sian WR4(sc, off & ~3, val32); 399257454Sian} 400257454Sian 401257454Sianstatic void 402257454Sianimx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 403257454Sian{ 404257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 405257454Sian uint32_t val32; 406257454Sian 407257454Sian /* The USDHC hardware moved the transfer mode bits to mixed control. */ 408257454Sian if (sc->hwtype == HWTYPE_USDHC) { 409257454Sian if (off == SDHCI_TRANSFER_MODE) { 410257454Sian val32 = RD4(sc, USDHC_MIX_CONTROL); 411257454Sian val32 &= ~0x3f; 412257454Sian val32 |= val & 0x37; 413257454Sian // XXX acmd23 not supported here (or by sdhci driver) 414257454Sian WR4(sc, USDHC_MIX_CONTROL, val32); 415257454Sian return; 416257454Sian } 417257454Sian } 418257454Sian 419257454Sian /* 420257454Sian * The clock control stuff is complex enough to have its own routine 421257454Sian * that can both change speeds and en/disable the clock output. Also, 422257454Sian * save the register bits in SDHCI format so that we can play them back 423257454Sian * in the read2 routine without complex decoding. 424257454Sian */ 425257454Sian if (off == SDHCI_CLOCK_CONTROL) { 426257454Sian sc->sdclockreg_freq_bits = val & 0xffc0; 427257454Sian if (val & SDHCI_CLOCK_CARD_EN) { 428257454Sian imx_sdhc_set_clock(sc, true); 429257454Sian } else { 430257454Sian imx_sdhc_set_clock(sc, false); 431257454Sian } 432294679Sian return; 433257454Sian } 434257454Sian 435257454Sian /* 436257454Sian * Figure out whether we need to check the DAT0 line for busy status at 437257454Sian * interrupt time. The controller should be doing this, but for some 438257454Sian * reason it doesn't. There are two cases: 439257454Sian * - R1B response with no data transfer should generate a DATA_END (aka 440257454Sian * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 441257454Sian * there's no data transfer there's no DATA_END interrupt. This is 442257454Sian * documented; they seem to think it's a feature. 443257454Sian * - R1B response after Auto-CMD12 appears to not work, even though 444257454Sian * there's a control bit for it (bit 3) in the vendor register. 445257454Sian * When we're starting a command that needs a manual DAT0 line check at 446257454Sian * interrupt time, we leave ourselves a note in r1bfix_type so that we 447257454Sian * can do the extra work in imx_sdhci_intr(). 448257454Sian */ 449257454Sian if (off == SDHCI_COMMAND_FLAGS) { 450257454Sian if (val & SDHCI_CMD_DATA) { 451257454Sian const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 452257454Sian val32 = RD4(sc, USDHC_MIX_CONTROL); 453257454Sian if ((val32 & MBAUTOCMD) == MBAUTOCMD) 454257454Sian sc->r1bfix_type = R1BFIX_AC12; 455257454Sian } else { 456257454Sian if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 457257454Sian WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 458257454Sian WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 459257454Sian sc->r1bfix_type = R1BFIX_NODATA; 460257454Sian } 461257454Sian } 462257454Sian } 463257454Sian 464257454Sian val32 = RD4(sc, off & ~3); 465257454Sian val32 &= ~(0xffff << (off & 3) * 8); 466257454Sian val32 |= ((val & 0xffff) << (off & 3) * 8); 467257454Sian WR4(sc, off & ~3, val32); 468257454Sian} 469257454Sian 470257454Sianstatic void 471257454Sianimx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 472257454Sian{ 473257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 474257454Sian 475257454Sian /* Clear synthesized interrupts, then pass the value to the hardware. */ 476257454Sian if (off == SDHCI_INT_STATUS) { 477257454Sian sc->r1bfix_intmask &= ~val; 478257454Sian } 479257454Sian 480257454Sian WR4(sc, off, val); 481257454Sian} 482257454Sian 483257454Sianstatic void 484257454Sianimx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 485257454Sian uint32_t *data, bus_size_t count) 486257454Sian{ 487257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 488257454Sian 489257454Sian bus_write_multi_4(sc->mem_res, off, data, count); 490257454Sian} 491257454Sian 492257454Sianstatic void 493257454Sianimx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable) 494257454Sian{ 495257454Sian uint32_t divisor, enable_bits, enable_reg, freq, prescale, val32; 496257454Sian 497257454Sian if (sc->hwtype == HWTYPE_ESDHC) { 498257454Sian divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 499257454Sian SDHCI_DIVIDER_MASK; 500257454Sian enable_reg = SDHCI_CLOCK_CONTROL; 501257454Sian enable_bits = SDHC_CLK_IPGEN | SDHC_CLK_HCKEN | 502257454Sian SDHC_CLK_PEREN; 503257454Sian } else { 504257454Sian divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 505257454Sian SDHCI_DIVIDER_MASK; 506257454Sian divisor |= ((sc->sdclockreg_freq_bits >> 507257454Sian SDHCI_DIVIDER_HI_SHIFT) & 508257454Sian SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 509257454Sian enable_reg = SDHCI_CLOCK_CONTROL; 510257454Sian enable_bits = SDHC_VEND_IPGEN | SDHC_VEND_HCKEN | 511257454Sian SDHC_VEND_PEREN; 512257454Sian } 513257454Sian 514257454Sian WR4(sc, SDHC_VEND_SPEC, 515257454Sian RD4(sc, SDHC_VEND_SPEC) & ~SDHC_VEND_FRC_SDCLK_ON); 516257454Sian WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits); 517257454Sian 518257454Sian if (!enable) 519257454Sian return; 520257454Sian 521257454Sian if (divisor == 0) 522257454Sian freq = sc->baseclk_hz; 523257454Sian else 524257454Sian freq = sc->baseclk_hz / (2 * divisor); 525257454Sian 526294679Sian for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 527257454Sian prescale <<= 1; 528257454Sian 529294679Sian for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 530257454Sian ++divisor; 531257454Sian 532294679Sian#ifdef DEBUG 533294679Sian device_printf(sc->dev, 534294679Sian "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 535294679Sian freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 536294679Sian prescale, divisor); 537294679Sian#endif 538294679Sian 539257454Sian prescale >>= 1; 540257454Sian divisor -= 1; 541257454Sian 542257454Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 543257454Sian val32 &= ~SDHC_CLK_DIVISOR_MASK; 544257454Sian val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 545257454Sian val32 &= ~SDHC_CLK_PRESCALE_MASK; 546257454Sian val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 547257454Sian WR4(sc, SDHCI_CLOCK_CONTROL, val32); 548257454Sian 549257454Sian WR4(sc, enable_reg, RD4(sc, enable_reg) | enable_bits); 550257454Sian WR4(sc, SDHC_VEND_SPEC, 551257454Sian RD4(sc, SDHC_VEND_SPEC) | SDHC_VEND_FRC_SDCLK_ON); 552257454Sian} 553257454Sian 554266200Sianstatic boolean_t 555266200Sianimx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc) 556266200Sian{ 557266200Sian uint32_t inhibit; 558266200Sian 559266200Sian mtx_assert(&sc->slot.mtx, MA_OWNED); 560266200Sian 561266200Sian /* 562266200Sian * Check the DAT0 line status using both the DLA (data line active) and 563266200Sian * CDIHB (data inhibit) bits in the present state register. In theory 564266200Sian * just DLA should do the trick, but in practice it takes both. If the 565266200Sian * DAT0 line is still being held and we're not yet beyond the timeout 566266200Sian * point, just schedule another callout to check again later. 567266200Sian */ 568266200Sian inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 569266200Sian 570266200Sian if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 571266200Sian callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 572266200Sian imx_sdhci_r1bfix_func, sc, 0); 573266200Sian return (false); 574266200Sian } 575266200Sian 576266200Sian /* 577266200Sian * If we reach this point with the inhibit bits still set, we've got a 578266200Sian * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 579266200Sian * line has been released, and we synthesize a DATA_END, and if the type 580266200Sian * of fix needed was on a command-without-data we also now add in the 581266200Sian * original INT_RESPONSE that we suppressed earlier. 582266200Sian */ 583266200Sian if (inhibit) 584266200Sian sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 585266200Sian else { 586266200Sian sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 587266200Sian if (sc->r1bfix_type == R1BFIX_NODATA) 588266200Sian sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 589266200Sian } 590266200Sian 591266200Sian sc->r1bfix_type = R1BFIX_NONE; 592266200Sian return (true); 593266200Sian} 594266200Sian 595257454Sianstatic void 596266200Sianimx_sdhci_r1bfix_func(void * arg) 597266200Sian{ 598266200Sian struct imx_sdhci_softc *sc = arg; 599266200Sian boolean_t r1bwait_done; 600266200Sian 601266200Sian mtx_lock(&sc->slot.mtx); 602266200Sian r1bwait_done = imx_sdhci_r1bfix_is_wait_done(sc); 603266200Sian mtx_unlock(&sc->slot.mtx); 604266200Sian if (r1bwait_done) 605266200Sian sdhci_generic_intr(&sc->slot); 606266200Sian} 607266200Sian 608266200Sianstatic void 609257454Sianimx_sdhci_intr(void *arg) 610257454Sian{ 611257454Sian struct imx_sdhci_softc *sc = arg; 612257454Sian uint32_t intmask; 613257454Sian 614266200Sian mtx_lock(&sc->slot.mtx); 615257454Sian 616257454Sian /* 617257454Sian * Manually check the DAT0 line for R1B response types that the 618266200Sian * controller fails to handle properly. The controller asserts the done 619266200Sian * interrupt while the card is still asserting busy with the DAT0 line. 620257454Sian * 621266200Sian * We check DAT0 immediately because most of the time, especially on a 622266200Sian * read, the card will actually be done by time we get here. If it's 623266200Sian * not, then the wait_done routine will schedule a callout to re-check 624266200Sian * periodically until it is done. In that case we clear the interrupt 625266200Sian * out of the hardware now so that we can present it later when the DAT0 626266200Sian * line is released. 627257454Sian * 628266200Sian * If we need to wait for the the DAT0 line to be released, we set up a 629266200Sian * timeout point 250ms in the future. This number comes from the SD 630266200Sian * spec, which allows a command to take that long. In the real world, 631266200Sian * cards tend to take 10-20ms for a long-running command such as a write 632266200Sian * or erase that spans two pages. 633257454Sian */ 634266200Sian switch (sc->r1bfix_type) { 635266200Sian case R1BFIX_NODATA: 636266200Sian intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_RESPONSE; 637266200Sian break; 638266200Sian case R1BFIX_AC12: 639266200Sian intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_DATA_END; 640266200Sian break; 641266200Sian default: 642266200Sian intmask = 0; 643266200Sian break; 644266200Sian } 645266200Sian if (intmask) { 646266200Sian sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 647266200Sian if (!imx_sdhci_r1bfix_is_wait_done(sc)) { 648266200Sian WR4(sc, SDHC_INT_STATUS, intmask); 649266200Sian bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4, 650266200Sian BUS_SPACE_BARRIER_WRITE); 651257454Sian } 652257454Sian } 653257454Sian 654266200Sian mtx_unlock(&sc->slot.mtx); 655257454Sian sdhci_generic_intr(&sc->slot); 656257454Sian} 657257454Sian 658257454Sianstatic int 659257454Sianimx_sdhci_get_ro(device_t bus, device_t child) 660257454Sian{ 661257454Sian 662257454Sian return (false); 663257454Sian} 664257454Sian 665257454Sianstatic int 666257454Sianimx_sdhci_detach(device_t dev) 667257454Sian{ 668257454Sian 669257454Sian return (EBUSY); 670257454Sian} 671257454Sian 672257454Sianstatic int 673257454Sianimx_sdhci_attach(device_t dev) 674257454Sian{ 675257454Sian struct imx_sdhci_softc *sc = device_get_softc(dev); 676257454Sian int rid, err; 677266198Sian phandle_t node; 678257454Sian 679257454Sian sc->dev = dev; 680257454Sian 681259359Sian sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 682259359Sian if (sc->hwtype == HWTYPE_NONE) 683257454Sian panic("Impossible: not compatible in imx_sdhci_attach()"); 684257454Sian 685257454Sian rid = 0; 686257454Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 687257454Sian RF_ACTIVE); 688257454Sian if (!sc->mem_res) { 689257454Sian device_printf(dev, "cannot allocate memory window\n"); 690257454Sian err = ENXIO; 691257454Sian goto fail; 692257454Sian } 693257454Sian 694257454Sian rid = 0; 695257454Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 696257454Sian RF_ACTIVE); 697257454Sian if (!sc->irq_res) { 698257454Sian device_printf(dev, "cannot allocate interrupt\n"); 699257454Sian err = ENXIO; 700257454Sian goto fail; 701257454Sian } 702257454Sian 703257454Sian if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 704257454Sian NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) { 705257454Sian device_printf(dev, "cannot setup interrupt handler\n"); 706257454Sian err = ENXIO; 707257454Sian goto fail; 708257454Sian } 709257454Sian 710257454Sian sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 711257454Sian 712257454Sian /* 713257454Sian * DMA is not really broken, I just haven't implemented it yet. 714257454Sian */ 715257454Sian sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 716257454Sian 717257454Sian /* 718257454Sian * Set the buffer watermark level to 128 words (512 bytes) for both read 719257454Sian * and write. The hardware has a restriction that when the read or 720257454Sian * write ready status is asserted, that means you can read exactly the 721257454Sian * number of words set in the watermark register before you have to 722257454Sian * re-check the status and potentially wait for more data. The main 723257454Sian * sdhci driver provides no hook for doing status checking on less than 724257454Sian * a full block boundary, so we set the watermark level to be a full 725257454Sian * block. Reads and writes where the block size is less than the 726257454Sian * watermark size will work correctly too, no need to change the 727257454Sian * watermark for different size blocks. However, 128 is the maximum 728257454Sian * allowed for the watermark, so PIO is limitted to 512 byte blocks 729257454Sian * (which works fine for SD cards, may be a problem for SDIO some day). 730257454Sian * 731257454Sian * XXX need named constants for this stuff. 732257454Sian */ 733257454Sian WR4(sc, SDHC_WTMK_LVL, 0x08800880); 734257454Sian 735266371Sian sc->baseclk_hz = imx_ccm_sdhci_hz(); 736257454Sian 737266198Sian /* 738266198Sian * If the slot is flagged with the non-removable property, set our flag 739266198Sian * to always force the SDHCI_CARD_PRESENT bit on. 740266198Sian * 741266198Sian * XXX Workaround for gpio-based card detect... 742266198Sian * 743266198Sian * We don't have gpio support yet. If there's a cd-gpios property just 744266198Sian * force the SDHCI_CARD_PRESENT bit on for now. If there isn't really a 745266198Sian * card there it will fail to probe at the mmc layer and nothing bad 746266200Sian * happens except instantiating an mmcN device for an empty slot. 747266198Sian */ 748266198Sian node = ofw_bus_get_node(dev); 749266198Sian if (OF_hasprop(node, "non-removable")) 750266198Sian sc->force_card_present = true; 751266198Sian else if (OF_hasprop(node, "cd-gpios")) { 752266198Sian /* XXX put real gpio hookup here. */ 753266198Sian sc->force_card_present = true; 754266198Sian } 755266198Sian 756266352Sian callout_init(&sc->r1bfix_callout, true); 757266352Sian sdhci_init_slot(dev, &sc->slot, 0); 758266352Sian 759257454Sian bus_generic_probe(dev); 760257454Sian bus_generic_attach(dev); 761257454Sian 762257454Sian sdhci_start_slot(&sc->slot); 763257454Sian 764257454Sian return (0); 765257454Sian 766257454Sianfail: 767257454Sian if (sc->intr_cookie) 768257454Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 769257454Sian if (sc->irq_res) 770257454Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 771257454Sian if (sc->mem_res) 772257454Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 773257454Sian 774257454Sian return (err); 775257454Sian} 776257454Sian 777257454Sianstatic int 778257454Sianimx_sdhci_probe(device_t dev) 779257454Sian{ 780257454Sian 781266152Sian if (!ofw_bus_status_okay(dev)) 782266152Sian return (ENXIO); 783266152Sian 784257454Sian switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 785257454Sian case HWTYPE_ESDHC: 786257454Sian device_set_desc(dev, "Freescale eSDHC controller"); 787257454Sian return (BUS_PROBE_DEFAULT); 788257454Sian case HWTYPE_USDHC: 789257454Sian device_set_desc(dev, "Freescale uSDHC controller"); 790257454Sian return (BUS_PROBE_DEFAULT); 791257454Sian default: 792257454Sian break; 793257454Sian } 794257454Sian return (ENXIO); 795257454Sian} 796257454Sian 797257454Sianstatic device_method_t imx_sdhci_methods[] = { 798257454Sian /* Device interface */ 799257454Sian DEVMETHOD(device_probe, imx_sdhci_probe), 800257454Sian DEVMETHOD(device_attach, imx_sdhci_attach), 801257454Sian DEVMETHOD(device_detach, imx_sdhci_detach), 802257454Sian 803257454Sian /* Bus interface */ 804257454Sian DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 805257454Sian DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 806257454Sian DEVMETHOD(bus_print_child, bus_generic_print_child), 807257454Sian 808257454Sian /* MMC bridge interface */ 809257454Sian DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 810257454Sian DEVMETHOD(mmcbr_request, sdhci_generic_request), 811257454Sian DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro), 812257454Sian DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 813257454Sian DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 814257454Sian 815257454Sian /* SDHCI registers accessors */ 816257454Sian DEVMETHOD(sdhci_read_1, imx_sdhci_read_1), 817257454Sian DEVMETHOD(sdhci_read_2, imx_sdhci_read_2), 818257454Sian DEVMETHOD(sdhci_read_4, imx_sdhci_read_4), 819257454Sian DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4), 820257454Sian DEVMETHOD(sdhci_write_1, imx_sdhci_write_1), 821257454Sian DEVMETHOD(sdhci_write_2, imx_sdhci_write_2), 822257454Sian DEVMETHOD(sdhci_write_4, imx_sdhci_write_4), 823257454Sian DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4), 824257454Sian 825257454Sian { 0, 0 } 826257454Sian}; 827257454Sian 828257454Sianstatic devclass_t imx_sdhci_devclass; 829257454Sian 830257454Sianstatic driver_t imx_sdhci_driver = { 831257454Sian "sdhci_imx", 832257454Sian imx_sdhci_methods, 833257454Sian sizeof(struct imx_sdhci_softc), 834257454Sian}; 835257454Sian 836257454SianDRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0); 837257454SianMODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1); 838257454Sian 839