1277644Sbr/*- 2277644Sbr * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3277644Sbr * All rights reserved. 4277644Sbr * 5277644Sbr * Redistribution and use in source and binary forms, with or without 6277644Sbr * modification, are permitted provided that the following conditions 7277644Sbr * are met: 8277644Sbr * 1. Redistributions of source code must retain the above copyright 9277644Sbr * notice, this list of conditions and the following disclaimer. 10277644Sbr * 2. Redistributions in binary form must reproduce the above copyright 11277644Sbr * notice, this list of conditions and the following disclaimer in the 12277644Sbr * documentation and/or other materials provided with the distribution. 13277644Sbr * 14277644Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15277644Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16277644Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17277644Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18277644Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19277644Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20277644Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21277644Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22277644Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23277644Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24277644Sbr * SUCH DAMAGE. 25277644Sbr * 26277644Sbr * $FreeBSD: releng/10.3/sys/arm/freescale/imx/imx6_sdma.h 283500 2015-05-24 18:59:45Z ian $ 27277644Sbr */ 28277644Sbr 29277644Sbr#define SDMAARM_MC0PTR 0x00 /* ARM platform Channel 0 Pointer */ 30277644Sbr#define SDMAARM_INTR 0x04 /* Channel Interrupts */ 31277644Sbr#define SDMAARM_STOP_STAT 0x08 /* Channel Stop/Channel Status */ 32277644Sbr#define SDMAARM_HSTART 0x0C /* Channel Start */ 33277644Sbr#define SDMAARM_EVTOVR 0x10 /* Channel Event Override */ 34277644Sbr#define SDMAARM_DSPOVR 0x14 /* Channel BP Override */ 35277644Sbr#define SDMAARM_HOSTOVR 0x18 /* Channel ARM platform Override */ 36277644Sbr#define SDMAARM_EVTPEND 0x1C /* Channel Event Pending */ 37277644Sbr#define SDMAARM_RESET 0x24 /* Reset Register */ 38277644Sbr#define SDMAARM_EVTERR 0x28 /* DMA Request Error Register */ 39277644Sbr#define SDMAARM_INTRMASK 0x2C /* Channel ARM platform Interrupt Mask */ 40277644Sbr#define SDMAARM_PSW 0x30 /* Schedule Status */ 41277644Sbr#define SDMAARM_EVTERRDBG 0x34 /* DMA Request Error Register */ 42277644Sbr#define SDMAARM_CONFIG 0x38 /* Configuration Register */ 43277644Sbr#define CONFIG_CSM 0x3 44277644Sbr#define SDMAARM_SDMA_LOCK 0x3C /* SDMA LOCK */ 45277644Sbr#define SDMAARM_ONCE_ENB 0x40 /* OnCE Enable */ 46277644Sbr#define SDMAARM_ONCE_DATA 0x44 /* OnCE Data Register */ 47277644Sbr#define SDMAARM_ONCE_INSTR 0x48 /* OnCE Instruction Register */ 48277644Sbr#define SDMAARM_ONCE_STAT 0x4C /* OnCE Status Register */ 49277644Sbr#define SDMAARM_ONCE_CMD 0x50 /* OnCE Command Register */ 50277644Sbr#define SDMAARM_ILLINSTADDR 0x58 /* Illegal Instruction Trap Address */ 51277644Sbr#define SDMAARM_CHN0ADDR 0x5C /* Channel 0 Boot Address */ 52277644Sbr#define SDMAARM_EVT_MIRROR 0x60 /* DMA Requests */ 53277644Sbr#define SDMAARM_EVT_MIRROR2 0x64 /* DMA Requests 2 */ 54277644Sbr#define SDMAARM_XTRIG_CONF1 0x70 /* Cross-Trigger Events Configuration Register 1 */ 55277644Sbr#define SDMAARM_XTRIG_CONF2 0x74 /* Cross-Trigger Events Configuration Register 2 */ 56277644Sbr#define SDMAARM_SDMA_CHNPRI(n) (0x100 + 0x4 * n) /* Channel Priority Registers */ 57277644Sbr#define SDMAARM_CHNENBL(n) (0x200 + 0x4 * n) /* Channel Enable RAM */ 58277644Sbr 59277644Sbr/* SDMA Event Mappings */ 60277644Sbr#define SSI1_RX_1 35 61277644Sbr#define SSI1_TX_1 36 62277644Sbr#define SSI1_RX_0 37 63277644Sbr#define SSI1_TX_0 38 64277644Sbr#define SSI2_RX_1 39 65277644Sbr#define SSI2_TX_1 40 66277644Sbr#define SSI2_RX_0 41 67277644Sbr#define SSI2_TX_0 42 68277644Sbr#define SSI3_RX_1 43 69277644Sbr#define SSI3_TX_1 44 70277644Sbr#define SSI3_RX_0 45 71277644Sbr#define SSI3_TX_0 46 72277644Sbr 73277644Sbr#define C0_ADDR 0x01 74277644Sbr#define C0_LOAD 0x02 75277644Sbr#define C0_DUMP 0x03 76277644Sbr#define C0_SETCTX 0x07 77277644Sbr#define C0_GETCTX 0x03 78277644Sbr#define C0_SETDM 0x01 79277644Sbr#define C0_SETPM 0x04 80277644Sbr#define C0_GETDM 0x02 81277644Sbr#define C0_GETPM 0x08 82277644Sbr 83277644Sbr#define BD_DONE 0x01 84277644Sbr#define BD_WRAP 0x02 85277644Sbr#define BD_CONT 0x04 86277644Sbr#define BD_INTR 0x08 87277644Sbr#define BD_RROR 0x10 88277644Sbr#define BD_LAST 0x20 89277644Sbr#define BD_EXTD 0x80 90277644Sbr 91277644Sbr/* sDMA data transfer length */ 92277644Sbr#define CMD_4BYTES 0 93277644Sbr#define CMD_3BYTES 3 94277644Sbr#define CMD_2BYTES 2 95277644Sbr#define CMD_1BYTES 1 96277644Sbr 97277644Sbrstruct sdma_firmware_header { 98277644Sbr uint32_t magic; 99277644Sbr uint32_t version_major; 100277644Sbr uint32_t version_minor; 101277644Sbr uint32_t script_addrs_start; 102277644Sbr uint32_t num_script_addrs; 103277644Sbr uint32_t ram_code_start; 104277644Sbr uint32_t ram_code_size; 105277644Sbr}; 106277644Sbr 107277644Sbrstruct sdma_mode_count { 108277644Sbr uint16_t count; 109277644Sbr uint8_t status; 110277644Sbr uint8_t command; 111277644Sbr}; 112277644Sbr 113277644Sbrstruct sdma_buffer_descriptor { 114277644Sbr struct sdma_mode_count mode; 115277644Sbr uint32_t buffer_addr; 116277644Sbr uint32_t ext_buffer_addr; 117277644Sbr} __packed; 118277644Sbr 119277644Sbrstruct sdma_channel_control { 120277644Sbr uint32_t current_bd_ptr; 121277644Sbr uint32_t base_bd_ptr; 122277644Sbr uint32_t unused[2]; 123277644Sbr} __packed; 124277644Sbr 125277644Sbrstruct sdma_state_registers { 126277644Sbr uint32_t pc :14; 127277644Sbr uint32_t unused1: 1; 128277644Sbr uint32_t t : 1; 129277644Sbr uint32_t rpc :14; 130277644Sbr uint32_t unused0: 1; 131277644Sbr uint32_t sf : 1; 132277644Sbr uint32_t spc :14; 133277644Sbr uint32_t unused2: 1; 134277644Sbr uint32_t df : 1; 135277644Sbr uint32_t epc :14; 136277644Sbr uint32_t lm : 2; 137277644Sbr} __packed; 138277644Sbr 139277644Sbrstruct sdma_context_data { 140277644Sbr struct sdma_state_registers channel_state; 141277644Sbr uint32_t gReg[8]; 142277644Sbr uint32_t mda; 143277644Sbr uint32_t msa; 144277644Sbr uint32_t ms; 145277644Sbr uint32_t md; 146277644Sbr uint32_t pda; 147277644Sbr uint32_t psa; 148277644Sbr uint32_t ps; 149277644Sbr uint32_t pd; 150277644Sbr uint32_t ca; 151277644Sbr uint32_t cs; 152277644Sbr uint32_t dda; 153277644Sbr uint32_t dsa; 154277644Sbr uint32_t ds; 155277644Sbr uint32_t dd; 156277644Sbr uint32_t unused[8]; 157277644Sbr} __packed; 158277644Sbr 159277644Sbr/* SDMA firmware script pointers */ 160277644Sbrstruct sdma_script_start_addrs { 161277644Sbr int32_t ap_2_ap_addr; 162277644Sbr int32_t ap_2_bp_addr; 163277644Sbr int32_t ap_2_ap_fixed_addr; 164277644Sbr int32_t bp_2_ap_addr; 165277644Sbr int32_t loopback_on_dsp_side_addr; 166277644Sbr int32_t mcu_interrupt_only_addr; 167277644Sbr int32_t firi_2_per_addr; 168277644Sbr int32_t firi_2_mcu_addr; 169277644Sbr int32_t per_2_firi_addr; 170277644Sbr int32_t mcu_2_firi_addr; 171277644Sbr int32_t uart_2_per_addr; 172277644Sbr int32_t uart_2_mcu_addr; 173277644Sbr int32_t per_2_app_addr; 174277644Sbr int32_t mcu_2_app_addr; 175277644Sbr int32_t per_2_per_addr; 176277644Sbr int32_t uartsh_2_per_addr; 177277644Sbr int32_t uartsh_2_mcu_addr; 178277644Sbr int32_t per_2_shp_addr; 179277644Sbr int32_t mcu_2_shp_addr; 180277644Sbr int32_t ata_2_mcu_addr; 181277644Sbr int32_t mcu_2_ata_addr; 182277644Sbr int32_t app_2_per_addr; 183277644Sbr int32_t app_2_mcu_addr; 184277644Sbr int32_t shp_2_per_addr; 185277644Sbr int32_t shp_2_mcu_addr; 186277644Sbr int32_t mshc_2_mcu_addr; 187277644Sbr int32_t mcu_2_mshc_addr; 188277644Sbr int32_t spdif_2_mcu_addr; 189277644Sbr int32_t mcu_2_spdif_addr; 190277644Sbr int32_t asrc_2_mcu_addr; 191277644Sbr int32_t ext_mem_2_ipu_addr; 192277644Sbr int32_t descrambler_addr; 193277644Sbr int32_t dptc_dvfs_addr; 194277644Sbr int32_t utra_addr; 195277644Sbr int32_t ram_code_start_addr; 196277644Sbr int32_t mcu_2_ssish_addr; 197277644Sbr int32_t ssish_2_mcu_addr; 198277644Sbr int32_t hdmi_dma_addr; 199277644Sbr}; 200277644Sbr 201277644Sbr#define SDMA_N_CHANNELS 32 202277644Sbr#define SDMA_N_EVENTS 48 203277644Sbr#define FW_HEADER_MAGIC 0x414d4453 204277644Sbr 205277644Sbrstruct sdma_channel { 206277644Sbr struct sdma_conf *conf; 207277644Sbr struct sdma_buffer_descriptor *bd; 208277644Sbr uint8_t in_use; 209277644Sbr}; 210277644Sbr 211277644Sbrstruct sdma_softc { 212277644Sbr struct resource *res[2]; 213277644Sbr bus_space_tag_t bst; 214277644Sbr bus_space_handle_t bsh; 215277644Sbr device_t dev; 216277644Sbr void *ih; 217277644Sbr struct sdma_channel_control *ccb; 218277644Sbr struct sdma_buffer_descriptor *bd0; 219277644Sbr struct sdma_context_data *context; 220277644Sbr struct sdma_channel channel[SDMA_N_CHANNELS]; 221277644Sbr uint32_t num_bd; 222277644Sbr uint32_t ccb_phys; 223277644Sbr uint32_t context_phys; 224277644Sbr struct sdma_firmware_header *fw_header; 225277644Sbr struct sdma_script_start_addrs *fw_scripts; 226277644Sbr}; 227277644Sbr 228277644Sbrstruct sdma_conf { 229277644Sbr bus_addr_t saddr; 230277644Sbr bus_addr_t daddr; 231277644Sbr uint32_t word_length; 232277644Sbr uint32_t nbits; 233277644Sbr uint32_t command; 234277644Sbr uint32_t num_bd; 235277644Sbr uint32_t event; 236277644Sbr uint32_t period; 237277644Sbr uint32_t (*ih)(void *, int); 238277644Sbr void *ih_user; 239277644Sbr}; 240277644Sbr 241277644Sbrint sdma_configure(int, struct sdma_conf *); 242277644Sbrint sdma_start(int); 243277644Sbrint sdma_stop(int); 244277644Sbrint sdma_alloc(void); 245277644Sbrint sdma_free(int); 246