1/*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/10.3/sys/arm/freescale/imx/imx51_sdmareg.h 250357 2013-05-08 09:42:50Z ray $ 30 */ 31 32/* Internal Registers definition for Freescale i.MX515 SDMA Core */ 33 34/* SDMA Core Instruction Memory Space */ 35#define SDMA_IBUS_ROM_ADDR_BASE 0x0000 36#define SDMA_IBUS_ROM_ADDR_SIZE 0x07ff 37#define SDMA_IBUS_RAM_ADDR_BASE 0x1000 38#define SDMA_IBUS_RAM_ADDR_SIZE 0x1fff 39 40/* SDMA Core Internal Registers */ 41#define SDMA_MC0PTR 0x7000 /* AP (MCU) Channel 0 Pointer R */ 42 43#define SDMA_CCPTR 0x7002 /* Current Channel Pointer R */ 44#define SDMA_ECTL_CCPTR_MASK 0x0000ffff 45#define SDMA_ECTL_CCPTR_SHIFT 0 46 47#define SDMA_CCR 0x7003 /* Current Channel Register R */ 48#define SDMA_ECTL_CCR_MASK 0x0000001f 49#define SDMA_ECTL_CCR_SHIFT 0 50 51#define SDMA_NCR 0x7004 /* Highest Pending Channel Register R */ 52#define SDMA_ECTL_NCR_MASK 0x0000001f 53#define SDMA_ECTL_NCR_SHIFT 0 54 55#define SDMA_EVENTS 0x7005 /* External DMA Requests Mirror R */ 56 57#define SDMA_CCPRI 0x7006 /* Current Channel Priority R */ 58#define SDMA_ECTL_CCPRI_MASK 0x00000007 59#define SDMA_ECTL_CCPRI_SHIFT 0 60 61#define SDMA_NCPRI 0x7007 /* Next Channel Priority R */ 62#define SDMA_ECTL_NCPRI_MASK 0x00000007 63#define SDMA_ECTL_NCPRI_SHIFT 0 64 65#define SDMA_ECOUNT 0x7009 /* OnCE Event Cell Counter R/W */ 66#define SDMA_ECTL_ECOUNT_MASK 0x0000ffff 67#define SDMA_ECTL_ECOUNT_SHIFT 0 68 69#define SDMA_ECTL 0x700A /* OnCE Event Cell Control Register R/W */ 70#define SDMA_ECTL_EN (1 << 13) 71#define SDMA_ECTL_CNT (1 << 12) 72#define SDMA_ECTL_ECTC_MASK 0x00000c00 73#define SDMA_ECTL_ECTC_SHIFT 10 74#define SDMA_ECTL_DTC_MASK 0x00000300 75#define SDMA_ECTL_DTC_SHIFT 8 76#define SDMA_ECTL_ATC_MASK 0x000000c0 77#define SDMA_ECTL_ATC_SHIFT 6 78#define SDMA_ECTL_ABTC_MASK 0x00000030 79#define SDMA_ECTL_ABTC_SHIFT 4 80#define SDMA_ECTL_AATC_MASK 0x0000000c 81#define SDMA_ECTL_AATC_SHIFT 2 82#define SDMA_ECTL_ATS_MASK 0x00000003 83#define SDMA_ECTL_ATS_SHIFT 0 84 85#define SDMA_EAA 0x700B /* OnCE Event Address Register A R/W */ 86#define SDMA_ECTL_EAA_MASK 0x0000ffff 87#define SDMA_ECTL_EAA_SHIFT 0 88 89#define SDMA_EAB 0x700C /* OnCE Event Cell Address Register B R/W */ 90#define SDMA_ECTL_EAB_MASK 0x0000ffff 91#define SDMA_ECTL_EAB_SHIFT 0 92 93#define SDMA_EAM 0x700D /* OnCE Event Cell Address Mask R/W */ 94#define SDMA_ECTL_EAM_MASK 0x0000ffff 95#define SDMA_ECTL_EAM_SHIFT 0 96 97#define SDMA_ED 0x700E /* OnCE Event Cell Data Register R/W */ 98#define SDMA_EDM 0x700F /* OnCE Event Cell Data Mask R/W */ 99#define SDMA_RTB 0x7018 /* OnCE Real-Time Buffer R/W */ 100 101#define SDMA_TB 0x7019 /* OnCE Trace Buffer R */ 102#define SDMA_TB_TBF (1 << 28) 103#define SDMA_TB_TADDR_MASK 0x0fffc000 104#define SDMA_TB_TADDR_SHIFT 14 105#define SDMA_TB_CHFADDR_MASK 0x00003fff 106#define SDMA_TB_CHFADDR_SHIFT 0 107 108#define SDMA_OSTAT 0x701A /* OnCE Status R */ 109#define SDMA_OSTAT_PST_MASK 0x0000f000 110#define SDMA_OSTAT_PST_SHIFT 12 111#define SDMA_OSTAT_RCV (1 << 11) 112#define SDMA_OSTAT_EDR (1 << 10) 113#define SDMA_OSTAT_ODR (1 << 9) 114#define SDMA_OSTAT_SWB (1 << 8) 115#define SDMA_OSTAT_MST (1 << 7) 116#define SDMA_OSTAT_ECDR_MASK 0x00000007 117#define SDMA_OSTAT_ECDR_SHIFT 0 118 119#define SDMA_MCHN0ADDR 0x701C /* Channel 0 Boot Address R */ 120#define SDMA_MCHN0ADDR_SMS_Z (1 << 14) 121#define SDMA_MCHN0ADDR_CHN0ADDR_MASK 0x00003fff 122#define SDMA_MCHN0ADDR_CHN0ADDR_SHIFT 0 123 124#define SDMA_MODE 0x701D /* Mode Status Register R */ 125#define SDMA_MODE_DSPCtrl (1 << 3) 126#define SDMA_MODE_AP_END (1 << 0) 127 128#define SDMA_LOCK 0x701E /* Lock Status Register R */ 129#define SDMA_LOCK_LOCK (1 << 0) 130 131#define SDMA_EVENTS2 0x701F /* External DMA Requests Mirror #2 R */ 132 133#define SDMA_HE 0x7020 /* AP Enable Register R */ 134#define SDMA_PRIV 0x7022 /* Current Channel BP Privilege Register R */ 135#define SDMA_PRIV_BPPRIV (1 << 0) 136#define SDMA_PRF_CNT 0x7023 /* Profile Free Running Register R/W */ 137#define SDMA_PRF_CNT_SEL_MASK 0xc0000000 138#define SDMA_PRF_CNT_SEL_SHIFT 30 139#define SDMA_PRF_CNT_EN (1 << 29) 140#define SDMA_PRF_CNT_OFL (1 << 22) 141#define SDMA_PRF_CNT_COUNTER_MASK 0x003fffff 142#define SDMA_PRF_CNT_COUNTER_SHIFT 0 143