1248557Sray/* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ 2248557Sray/* 3248557Sray * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4248557Sray * Written by Hashimoto Kenichi for Genetec Corporation. 5248557Sray * 6248557Sray * Redistribution and use in source and binary forms, with or without 7248557Sray * modification, are permitted provided that the following conditions 8248557Sray * are met: 9248557Sray * 1. Redistributions of source code must retain the above copyright 10248557Sray * notice, this list of conditions and the following disclaimer. 11248557Sray * 2. Redistributions in binary form must reproduce the above copyright 12248557Sray * notice, this list of conditions and the following disclaimer in the 13248557Sray * documentation and/or other materials provided with the distribution. 14248557Sray * 15248557Sray * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16248557Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17248557Sray * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18248557Sray * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19248557Sray * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20248557Sray * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21248557Sray * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22248557Sray * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23248557Sray * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24248557Sray * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25248557Sray * POSSIBILITY OF SUCH DAMAGE. 26248557Sray */ 27248557Sray 28248557Sray/*- 29250357Sray * Copyright (c) 2012, 2013 The FreeBSD Foundation 30248557Sray * All rights reserved. 31248557Sray * 32248557Sray * Portions of this software were developed by Oleksandr Rybalko 33248557Sray * under sponsorship from the FreeBSD Foundation. 34248557Sray * 35248557Sray * Redistribution and use in source and binary forms, with or without 36248557Sray * modification, are permitted provided that the following conditions 37248557Sray * are met: 38248557Sray * 1. Redistributions of source code must retain the above copyright 39248557Sray * notice, this list of conditions and the following disclaimer. 40248557Sray * 2. Redistributions in binary form must reproduce the above copyright 41248557Sray * notice, this list of conditions and the following disclaimer in the 42248557Sray * documentation and/or other materials provided with the distribution. 43248557Sray * 44248557Sray * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45248557Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46248557Sray * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47248557Sray * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48248557Sray * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49248557Sray * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50248557Sray * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51248557Sray * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52248557Sray * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53248557Sray * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54248557Sray * SUCH DAMAGE. 55248557Sray * 56248557Sray * $FreeBSD: releng/10.3/sys/arm/freescale/imx/imx51_ipuv3reg.h 266365 2014-05-17 22:00:10Z ian $ 57248557Sray */ 58248557Sray 59248557Sray#ifndef _ARM_IMX_IMX51_IPUV3REG_H 60248557Sray#define _ARM_IMX_IMX51_IPUV3REG_H 61248557Sray 62248557Sray/* register offset address */ 63248557Sray 64248557Sray/* 65248557Sray * CM 66248557Sray * Control Module 67248557Sray */ 68248557Sray#define IPU_CM_CONF 0x00000000 69248557Sray#define CM_CONF_CSI_SEL 0x80000000 70248557Sray#define CM_CONF_IC_INPUT 0x40000000 71248557Sray#define CM_CONF_CSI1_DATA_SOURCE 0x20000000 72248557Sray#define CM_CONF_CSI0_DATA_SOURCE 0x10000000 73248557Sray#define CM_CONF_VDI_DMFC_SYNC 0x08000000 74248557Sray#define CM_CONF_IC_DMFC_SYNC 0x04000000 75248557Sray#define CM_CONF_IC_DMFC_SEL 0x02000000 76248557Sray#define CM_CONF_ISP_DOUBLE_FLOW 0x01000000 77248557Sray#define CM_CONF_IDMAC_DISABLE 0x00400000 78248557Sray#define CM_CONF_IPU_DIAGBUS_ON 0x00200000 79248557Sray#define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000 80248557Sray#define CM_CONF_VDI_EN 0x00001000 81248557Sray#define CM_CONF_SISG_EN 0x00000800 82248557Sray#define CM_CONF_DMFC_EN 0x00000400 83248557Sray#define CM_CONF_DC_EN 0x00000200 84248557Sray#define CM_CONF_SMFC_EN 0x00000100 85248557Sray#define CM_CONF_DI1_EN 0x00000080 86248557Sray#define CM_CONF_DI0_EN 0x00000040 87248557Sray#define CM_CONF_DP_EN 0x00000020 88248557Sray#define CM_CONF_ISP_EN 0x00000010 89248557Sray#define CM_CONF_IRT_EN 0x00000008 90248557Sray#define CM_CONF_IC_EN 0x00000004 91248557Sray#define CM_CONF_CSI1_EN 0x00000002 92248557Sray#define CM_CONF_CSI0_EN 0x00000001 93248557Sray#define IPU_SISG_CTRL0 0x00000004 94248557Sray#define IPU_SISG_CTRL1 0x00000008 95248557Sray#define IPU_CM_INT_CTRL_1 0x0000003c 96248557Sray#define IPU_CM_INT_CTRL_2 0x00000040 97248557Sray#define IPU_CM_INT_CTRL_3 0x00000044 98248557Sray#define IPU_CM_INT_CTRL_4 0x00000048 99248557Sray#define IPU_CM_INT_CTRL_5 0x0000004c 100248557Sray#define IPU_CM_INT_CTRL_6 0x00000050 101248557Sray#define IPU_CM_INT_CTRL_7 0x00000054 102248557Sray#define IPU_CM_INT_CTRL_8 0x00000058 103248557Sray#define IPU_CM_INT_CTRL_9 0x0000005c 104248557Sray#define IPU_CM_INT_CTRL_10 0x00000060 105248557Sray#define IPU_CM_INT_CTRL_11 0x00000064 106248557Sray#define IPU_CM_INT_CTRL_12 0x00000068 107248557Sray#define IPU_CM_INT_CTRL_13 0x0000006c 108248557Sray#define IPU_CM_INT_CTRL_14 0x00000070 109248557Sray#define IPU_CM_INT_CTRL_15 0x00000074 110248557Sray#define IPU_CM_SDMA_EVENT_1 0x00000078 111248557Sray#define IPU_CM_SDMA_EVENT_2 0x0000007c 112248557Sray#define IPU_CM_SDMA_EVENT_3 0x00000080 113248557Sray#define IPU_CM_SDMA_EVENT_4 0x00000084 114248557Sray#define IPU_CM_SDMA_EVENT_7 0x00000088 115248557Sray#define IPU_CM_SDMA_EVENT_8 0x0000008c 116248557Sray#define IPU_CM_SDMA_EVENT_11 0x00000090 117248557Sray#define IPU_CM_SDMA_EVENT_12 0x00000094 118248557Sray#define IPU_CM_SDMA_EVENT_13 0x00000098 119248557Sray#define IPU_CM_SDMA_EVENT_14 0x0000009c 120248557Sray#define IPU_CM_SRM_PRI1 0x000000a0 121248557Sray#define IPU_CM_SRM_PRI2 0x000000a4 122248557Sray#define IPU_CM_FS_PROC_FLOW1 0x000000a8 123248557Sray#define IPU_CM_FS_PROC_FLOW2 0x000000ac 124248557Sray#define IPU_CM_FS_PROC_FLOW3 0x000000b0 125248557Sray#define IPU_CM_FS_DISP_FLOW1 0x000000b4 126248557Sray#define IPU_CM_FS_DISP_FLOW2 0x000000b8 127248557Sray#define IPU_CM_SKIP 0x000000bc 128248557Sray#define IPU_CM_DISP_ALT_CONF 0x000000c0 129248557Sray#define IPU_CM_DISP_GEN 0x000000c4 130248557Sray#define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000 131248557Sray#define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000 132248557Sray#define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000 133248557Sray#define CM_DISP_GEN_MCU_T_SHIFT 18 134248557Sray#define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) 135248557Sray#define IPU_CM_DISP_ALT1 0x000000c8 136248557Sray#define IPU_CM_DISP_ALT2 0x000000cc 137248557Sray#define IPU_CM_DISP_ALT3 0x000000d0 138248557Sray#define IPU_CM_DISP_ALT4 0x000000d4 139248557Sray#define IPU_CM_SNOOP 0x000000d8 140248557Sray#define IPU_CM_MEM_RST 0x000000dc 141248557Sray#define CM_MEM_START 0x80000000 142248557Sray#define CM_MEM_EN 0x007fffff 143248557Sray#define IPU_CM_PM 0x000000e0 144248557Sray#define IPU_CM_GPR 0x000000e4 145248557Sray#define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000 146248557Sray#define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000 147248557Sray#define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000 148248557Sray#define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000 149248557Sray#define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000 150248557Sray#define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000 151248557Sray#define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000 152248557Sray#define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000 153248557Sray#define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000 154248557Sray#define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000 155248557Sray#define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000 156248557Sray#define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000 157248557Sray#define CM_GPR_IPU_GP(n) __BIT((n)) 158248557Sray#define IPU_CM_CH_DB_MODE_SEL_0 0x00000150 159248557Sray#define IPU_CM_CH_DB_MODE_SEL_1 0x00000154 160248557Sray#define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168 161248557Sray#define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c 162248557Sray#define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178 163248557Sray#define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c 164248557Sray#define IPU_CM_INT_STAT_1 0x00000200 165248557Sray#define IPU_CM_INT_STAT_2 0x00000204 166248557Sray#define IPU_CM_INT_STAT_3 0x00000208 167248557Sray#define IPU_CM_INT_STAT_4 0x0000020c 168248557Sray#define IPU_CM_INT_STAT_5 0x00000210 169248557Sray#define IPU_CM_INT_STAT_6 0x00000214 170248557Sray#define IPU_CM_INT_STAT_7 0x00000218 171248557Sray#define IPU_CM_INT_STAT_8 0x0000021c 172248557Sray#define IPU_CM_INT_STAT_9 0x00000220 173248557Sray#define IPU_CM_INT_STAT_10 0x00000224 174248557Sray#define IPU_CM_INT_STAT_11 0x00000228 175248557Sray#define IPU_CM_INT_STAT_12 0x0000022c 176248557Sray#define IPU_CM_INT_STAT_13 0x00000230 177248557Sray#define IPU_CM_INT_STAT_14 0x00000234 178248557Sray#define IPU_CM_INT_STAT_15 0x00000238 179248557Sray#define IPU_CM_CUR_BUF_0 0x0000023c 180248557Sray#define IPU_CM_CUR_BUF_1 0x00000240 181248557Sray#define IPU_CM_ALT_CUR_BUF_0 0x00000244 182248557Sray#define IPU_CM_ALT_CUR_BUF_1 0x00000248 183248557Sray#define IPU_CM_SRM_STAT 0x0000024c 184248557Sray#define IPU_CM_PROC_TASKS_STAT 0x00000250 185248557Sray#define IPU_CM_DISP_TASKS_STAT 0x00000254 186248557Sray#define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258 187248557Sray#define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c 188248557Sray#define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260 189248557Sray#define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264 190248557Sray#define IPU_CM_CH_BUF0_RDY0 0x00000268 191248557Sray#define IPU_CM_CH_BUF0_RDY1 0x0000026c 192248557Sray#define IPU_CM_CH_BUF1_RDY0 0x00000270 193248557Sray#define IPU_CM_CH_BUF1_RDY1 0x00000274 194248557Sray#define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278 195248557Sray#define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c 196248557Sray#define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280 197248557Sray#define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284 198248557Sray#define IPU_CM_CH_BUF2_RDY0 0x00000288 199248557Sray#define IPU_CM_CH_BUF2_RDY1 0x0000028c 200248557Sray 201248557Sray/* 202248557Sray * IDMAC 203248557Sray * Image DMA Controller 204248557Sray */ 205248557Sray#define IPU_IDMAC_CONF 0x00000000 206248557Sray#define IPU_IDMAC_CH_EN_1 0x00000004 207248557Sray#define IPU_IDMAC_CH_EN_2 0x00000008 208248557Sray#define IPU_IDMAC_SEP_ALPHA 0x0000000c 209248557Sray#define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010 210248557Sray#define IPU_IDMAC_CH_PRI_1 0x00000014 211248557Sray#define IPU_IDMAC_CH_PRI_2 0x00000018 212248557Sray#define IPU_IDMAC_WM_EN_1 0x0000001c 213248557Sray#define IPU_IDMAC_WM_EN_2 0x00000020 214248557Sray#define IPU_IDMAC_LOCK_EN_1 0x00000024 215248557Sray#define IPU_IDMAC_LOCK_EN_2 0x00000028 216248557Sray#define IPU_IDMAC_SUB_ADDR_0 0x0000002c 217248557Sray#define IPU_IDMAC_SUB_ADDR_1 0x00000030 218248557Sray#define IPU_IDMAC_SUB_ADDR_2 0x00000034 219248557Sray#define IPU_IDMAC_SUB_ADDR_3 0x00000038 220248557Sray#define IPU_IDMAC_SUB_ADDR_4 0x0000003c 221248557Sray#define IPU_IDMAC_BNDM_EN_1 0x00000040 222248557Sray#define IPU_IDMAC_BNDM_EN_2 0x00000044 223248557Sray#define IPU_IDMAC_SC_CORD 0x00000048 224248557Sray#define IPU_IDMAC_SC_CORD1 0x0000004c 225248557Sray#define IPU_IDMAC_CH_BUSY_1 0x00000100 226248557Sray#define IPU_IDMAC_CH_BUSY_2 0x00000104 227248557Sray 228248557Sray#define CH_PANNEL_BG 23 229248557Sray#define CH_PANNEL_FG 27 230248557Sray 231248557Sray/* 232248557Sray * DP 233248557Sray * Display Port 234248557Sray */ 235248557Sray#define IPU_DP_DEBUG_CNT 0x000000bc 236248557Sray#define IPU_DP_DEBUG_STAT 0x000000c0 237248557Sray 238248557Sray/* 239248557Sray * IC 240248557Sray * Image Converter 241248557Sray */ 242248557Sray#define IPU_IC_CONF 0x00000000 243248557Sray#define IPU_IC_PRP_ENC_RSC 0x00000004 244248557Sray#define IPU_IC_PRP_VF_RSC 0x00000008 245248557Sray#define IPU_IC_PP_RSC 0x0000000c 246248557Sray#define IPU_IC_CMBP_1 0x00000010 247248557Sray#define IPU_IC_CMBP_2 0x00000014 248248557Sray#define IPU_IC_IDMAC_1 0x00000018 249248557Sray#define IPU_IC_IDMAC_2 0x0000001c 250248557Sray#define IPU_IC_IDMAC_3 0x00000020 251248557Sray#define IPU_IC_IDMAC_4 0x00000024 252248557Sray 253248557Sray/* 254248557Sray * CSI 255248557Sray * Camera Sensor Interface 256248557Sray */ 257248557Sray#define IPU_CSI0_SENS_CONF 0x00000000 258248557Sray#define IPU_CSI0_SENS_FRM_SIZE 0x00000004 259248557Sray#define IPU_CSI0_ACT_FRM_SIZE 0x00000008 260248557Sray#define IPU_CSI0_OUT_FRM_CTRL 0x0000000c 261248557Sray#define IPU_CSI0_TST_CTRL 0x00000010 262248557Sray#define IPU_CSI0_CCIR_CODE_1 0x00000014 263248557Sray#define IPU_CSI0_CCIR_CODE_2 0x00000018 264248557Sray#define IPU_CSI0_CCIR_CODE_3 0x0000001c 265248557Sray#define IPU_CSI0_DI 0x00000020 266248557Sray#define IPU_CSI0_SKIP 0x00000024 267248557Sray#define IPU_CSI0_CPD_CTRL 0x00000028 268248557Sray#define IPU_CSI0_CPD_OFFSET1 0x000000ec 269248557Sray#define IPU_CSI0_CPD_OFFSET2 0x000000f0 270248557Sray 271248557Sray#define IPU_CSI1_SENS_CONF 0x00000000 272248557Sray#define IPU_CSI1_SENS_FRM_SIZE 0x00000004 273248557Sray#define IPU_CSI1_ACT_FRM_SIZE 0x00000008 274248557Sray#define IPU_CSI1_OUT_FRM_CTRL 0x0000000c 275248557Sray#define IPU_CSI1_TST_CTRL 0x00000010 276248557Sray#define IPU_CSI1_CCIR_CODE_1 0x00000014 277248557Sray#define IPU_CSI1_CCIR_CODE_2 0x00000018 278248557Sray#define IPU_CSI1_CCIR_CODE_3 0x0000001c 279248557Sray#define IPU_CSI1_DI 0x00000020 280248557Sray#define IPU_CSI1_SKIP 0x00000024 281248557Sray#define IPU_CSI1_CPD_CTRL 0x00000028 282248557Sray#define IPU_CSI1_CPD_OFFSET1 0x000000ec 283248557Sray#define IPU_CSI1_CPD_OFFSET2 0x000000f0 284248557Sray 285248557Sray/* 286248557Sray * DI 287248557Sray * Display Interface 288248557Sray */ 289248557Sray#define IPU_DI_GENERAL 0x00000000 290248557Sray#define DI_GENERAL_DISP_Y_SEL 0x70000000 291248557Sray#define DI_GENERAL_CLOCK_STOP_MODE 0x0f000000 292248557Sray#define DI_GENERAL_DISP_CLOCK_INIT 0x00800000 293248557Sray#define DI_GENERAL_MASK_SEL 0x00400000 294248557Sray#define DI_GENERAL_VSYNC_EXT 0x00200000 295248557Sray#define DI_GENERAL_CLK_EXT 0x00100000 296248557Sray#define DI_GENERAL_WATCHDOG_MODE 0x000c0000 297248557Sray#define DI_GENERAL_POLARITY_DISP_CLK 0x00020000 298248557Sray#define DI_GENERAL_SYNC_COUNT_SEL 0x0000f000 299248557Sray#define DI_GENERAL_ERR_TREATMENT 0x00000800 300248557Sray#define DI_GENERAL_ERM_VSYNC_SEL 0x00000400 301248557Sray#define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) 302248557Sray#define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) 303248557Sray 304248557Sray#define IPU_DI_BS_CLKGEN0 0x00000004 305248557Sray#define DI_BS_CLKGEN0_OFFSET_SHIFT 16 306248557Sray#define IPU_DI_BS_CLKGEN1 0x00000008 307248557Sray#define DI_BS_CLKGEN1_DOWN_SHIFT 16 308248557Sray#define DI_BS_CLKGEN1_UP_SHIFT 0 309248557Sray#define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) 310248557Sray#define DI_SW_GEN0_RUN_VAL 0x7ff80000 311248557Sray#define DI_SW_GEN0_RUN_RESOL 0x00070000 312248557Sray#define DI_SW_GEN0_OFFSET_VAL 0x00007ff8 313248557Sray#define DI_SW_GEN0_OFFSET_RESOL 0x00000007 314248557Sray#define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \ 315248557Sray (((run_val) << 19) | ((run_resol) << 16) | \ 316248557Sray ((offset_val) << 3) | (offset_resol)) 317248557Sray#define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4) 318248557Sray#define DI_SW_GEN1_CNT_POL_GEN_EN 0x60000000 319248557Sray#define DI_SW_GEN1_CNT_AUTO_RELOAD 0x10000000 320248557Sray#define DI_SW_GEN1_CNT_CLR_SEL 0x0e000000 321248557Sray#define DI_SW_GEN1_CNT_DOWN 0x01ff0000 322248557Sray#define DI_SW_GEN1_CNT_POL_TRIG_SEL 0x00007000 323248557Sray#define DI_SW_GEN1_CNT_POL_CLR_SEL 0x00000e00 324248557Sray#define DI_SW_GEN1_CNT_UP 0x000001ff 325248557Sray#define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \ 326248557Sray (((pol_gen_en) << 29) | ((auto_reload) << 28) | \ 327248557Sray ((clr_sel) << 25) | \ 328248557Sray ((down) << 16) | ((pol_trig_sel) << 12) | \ 329248557Sray ((pol_clr_sel) << 9) | (up)) 330248557Sray#define IPU_DI_SYNC_AS_GEN 0x00000054 331248557Sray#define DI_SYNC_AS_GEN_SYNC_START_EN 0x10000000 332248557Sray#define DI_SYNC_AS_GEN_VSYNC_SEL 0x0000e000 333248557Sray#define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 334248557Sray#define DI_SYNC_AS_GEN_SYNC_STAR 0x00000fff 335248557Sray#define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) 336248557Sray#define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 337248557Sray#define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 338248557Sray#define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) 339248557Sray#define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ 340248557Sray DI_DW_GEN_PIN_SHIFT(n)) 341248557Sray#define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) 342248557Sray#define DI_DW_SET_DOWN_SHIFT 16 343248557Sray#define DI_DW_SET_UP_SHIFT 0 344248557Sray#define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) 345248557Sray#define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) 346248557Sray#define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n))) 347248557Sray#define IPU_DI_SER_CONF 0x0000015c 348248557Sray#define IPU_DI_SSC 0x00000160 349248557Sray#define IPU_DI_POL 0x00000164 350248557Sray#define DI_POL_DRDY_POLARITY_17 0x00000040 351248557Sray#define DI_POL_DRDY_POLARITY_16 0x00000020 352248557Sray#define DI_POL_DRDY_POLARITY_15 0x00000010 353248557Sray#define DI_POL_DRDY_POLARITY_14 0x00000008 354248557Sray#define DI_POL_DRDY_POLARITY_13 0x00000004 355248557Sray#define DI_POL_DRDY_POLARITY_12 0x00000002 356248557Sray#define DI_POL_DRDY_POLARITY_11 0x00000001 357248557Sray#define IPU_DI_AW0 0x00000168 358248557Sray#define IPU_DI_AW1 0x0000016c 359248557Sray#define IPU_DI_SCR_CONF 0x00000170 360248557Sray#define IPU_DI_STAT 0x00000174 361248557Sray 362248557Sray/* 363248557Sray * SMFC 364248557Sray * Sensor Multi FIFO Controller 365248557Sray */ 366248557Sray#define IPU_SMFC_MAP 0x00000000 367248557Sray#define IPU_SMFC_WMC 0x00000004 368248557Sray#define IPU_SMFC_BS 0x00000008 369248557Sray 370248557Sray/* 371248557Sray * DC 372248557Sray * Display Controller 373248557Sray */ 374248557Sray#define IPU_DC_READ_CH_CONF 0x00000000 375248557Sray#define IPU_DC_READ_CH_ADDR 0x00000004 376248557Sray 377248557Sray#define IPU_DC_RL0_CH_0 0x00000008 378248557Sray#define IPU_DC_RL1_CH_0 0x0000000c 379248557Sray#define IPU_DC_RL2_CH_0 0x00000010 380248557Sray#define IPU_DC_RL3_CH_0 0x00000014 381248557Sray#define IPU_DC_RL4_CH_0 0x00000018 382248557Sray#define IPU_DC_WR_CH_CONF_1 0x0000001c 383248557Sray#define IPU_DC_WR_CH_ADDR_1 0x00000020 384248557Sray#define IPU_DC_RL0_CH_1 0x00000024 385248557Sray#define IPU_DC_RL1_CH_1 0x00000028 386248557Sray#define IPU_DC_RL2_CH_1 0x0000002c 387248557Sray#define IPU_DC_RL3_CH_1 0x00000030 388248557Sray#define IPU_DC_RL4_CH_1 0x00000034 389248557Sray#define IPU_DC_WR_CH_CONF_2 0x00000038 390248557Sray#define IPU_DC_WR_CH_ADDR_2 0x0000003c 391248557Sray#define IPU_DC_RL0_CH_2 0x00000040 392248557Sray#define IPU_DC_RL1_CH_2 0x00000044 393248557Sray#define IPU_DC_RL2_CH_2 0x00000048 394248557Sray#define IPU_DC_RL3_CH_2 0x0000004c 395248557Sray#define IPU_DC_RL4_CH_2 0x00000050 396248557Sray#define IPU_DC_CMD_CH_CONF_3 0x00000054 397248557Sray#define IPU_DC_CMD_CH_CONF_4 0x00000058 398248557Sray#define IPU_DC_WR_CH_CONF_5 0x0000005c 399248557Sray#define IPU_DC_WR_CH_ADDR_5 0x00000060 400248557Sray#define IPU_DC_RL0_CH_5 0x00000064 401248557Sray#define IPU_DC_RL1_CH_5 0x00000068 402248557Sray#define IPU_DC_RL2_CH_5 0x0000006c 403248557Sray#define IPU_DC_RL3_CH_5 0x00000070 404248557Sray#define IPU_DC_RL4_CH_5 0x00000074 405248557Sray#define IPU_DC_WR_CH_CONF_6 0x00000078 406248557Sray#define IPU_DC_WR_CH_ADDR_6 0x0000007c 407248557Sray#define IPU_DC_RL0_CH_6 0x00000080 408248557Sray#define IPU_DC_RL1_CH_6 0x00000084 409248557Sray#define IPU_DC_RL2_CH_6 0x00000088 410248557Sray#define IPU_DC_RL3_CH_6 0x0000008c 411248557Sray#define IPU_DC_RL4_CH_6 0x00000090 412248557Sray#define IPU_DC_WR_CH_CONF1_8 0x00000094 413248557Sray#define IPU_DC_WR_CH_CONF2_8 0x00000098 414248557Sray#define IPU_DC_RL1_CH_8 0x0000009c 415248557Sray#define IPU_DC_RL2_CH_8 0x000000a0 416248557Sray#define IPU_DC_RL3_CH_8 0x000000a4 417248557Sray#define IPU_DC_RL4_CH_8 0x000000a8 418248557Sray#define IPU_DC_RL5_CH_8 0x000000ac 419248557Sray#define IPU_DC_RL6_CH_8 0x000000b0 420248557Sray#define IPU_DC_WR_CH_CONF1_9 0x000000b4 421248557Sray#define IPU_DC_WR_CH_CONF2_9 0x000000b8 422248557Sray#define IPU_DC_RL1_CH_9 0x000000bc 423248557Sray#define IPU_DC_RL2_CH_9 0x000000c0 424248557Sray#define IPU_DC_RL3_CH_9 0x000000c4 425248557Sray#define IPU_DC_RL4_CH_9 0x000000c8 426248557Sray#define IPU_DC_RL5_CH_9 0x000000cc 427248557Sray#define IPU_DC_RL6_CH_9 0x000000d0 428248557Sray 429248557Sray#define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) 430248557Sray#define DC_RL_CH_0 IPU_DC_RL0_CH_0 431248557Sray#define DC_RL_CH_1 IPU_DC_RL0_CH_1 432248557Sray#define DC_RL_CH_2 IPU_DC_RL0_CH_2 433248557Sray#define DC_RL_CH_5 IPU_DC_RL0_CH_5 434248557Sray#define DC_RL_CH_6 IPU_DC_RL0_CH_6 435248557Sray#define DC_RL_CH_8 IPU_DC_RL0_CH_8 436248557Sray 437248557Sray#define DC_RL_EVT_NF 0 438248557Sray#define DC_RL_EVT_NL 1 439248557Sray#define DC_RL_EVT_EOF 2 440248557Sray#define DC_RL_EVT_NFIELD 3 441248557Sray#define DC_RL_EVT_EOL 4 442248557Sray#define DC_RL_EVT_EOFIELD 5 443248557Sray#define DC_RL_EVT_NEW_ADDR 6 444248557Sray#define DC_RL_EVT_NEW_CHAN 7 445248557Sray#define DC_RL_EVT_NEW_DATA 8 446248557Sray 447248557Sray#define IPU_DC_GEN 0x000000d4 448248557Sray#define IPU_DC_DISP_CONF1_0 0x000000d8 449248557Sray#define IPU_DC_DISP_CONF1_1 0x000000dc 450248557Sray#define IPU_DC_DISP_CONF1_2 0x000000e0 451248557Sray#define IPU_DC_DISP_CONF1_3 0x000000e4 452248557Sray#define IPU_DC_DISP_CONF2_0 0x000000e8 453248557Sray#define IPU_DC_DISP_CONF2_1 0x000000ec 454248557Sray#define IPU_DC_DISP_CONF2_2 0x000000f0 455248557Sray#define IPU_DC_DISP_CONF2_3 0x000000f4 456248557Sray#define IPU_DC_DI0_CONF_1 0x000000f8 457248557Sray#define IPU_DC_DI0_CONF_2 0x000000fc 458248557Sray#define IPU_DC_DI1_CONF_1 0x00000100 459248557Sray#define IPU_DC_DI1_CONF_2 0x00000104 460248557Sray 461248557Sray#define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) 462248557Sray#define IPU_DC_MAP_CONF_0 0x00000108 463248557Sray#define IPU_DC_MAP_CONF_1 0x0000010c 464248557Sray#define IPU_DC_MAP_CONF_2 0x00000110 465248557Sray#define IPU_DC_MAP_CONF_3 0x00000114 466248557Sray#define IPU_DC_MAP_CONF_4 0x00000118 467248557Sray#define IPU_DC_MAP_CONF_5 0x0000011c 468248557Sray#define IPU_DC_MAP_CONF_6 0x00000120 469248557Sray#define IPU_DC_MAP_CONF_7 0x00000124 470248557Sray#define IPU_DC_MAP_CONF_8 0x00000128 471248557Sray#define IPU_DC_MAP_CONF_9 0x0000012c 472248557Sray#define IPU_DC_MAP_CONF_10 0x00000130 473248557Sray#define IPU_DC_MAP_CONF_11 0x00000134 474248557Sray#define IPU_DC_MAP_CONF_12 0x00000138 475248557Sray#define IPU_DC_MAP_CONF_13 0x0000013c 476248557Sray#define IPU_DC_MAP_CONF_14 0x00000140 477248557Sray 478248557Sray#define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) 479248557Sray#define IPU_DC_MAP_CONF_15 0x00000144 480248557Sray#define IPU_DC_MAP_CONF_16 0x00000148 481248557Sray#define IPU_DC_MAP_CONF_17 0x0000014c 482248557Sray#define IPU_DC_MAP_CONF_18 0x00000150 483248557Sray#define IPU_DC_MAP_CONF_19 0x00000154 484248557Sray#define IPU_DC_MAP_CONF_20 0x00000158 485248557Sray#define IPU_DC_MAP_CONF_21 0x0000015c 486248557Sray#define IPU_DC_MAP_CONF_22 0x00000160 487248557Sray#define IPU_DC_MAP_CONF_23 0x00000164 488248557Sray#define IPU_DC_MAP_CONF_24 0x00000168 489248557Sray#define IPU_DC_MAP_CONF_25 0x0000016c 490248557Sray#define IPU_DC_MAP_CONF_26 0x00000170 491248557Sray 492248557Sray#define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) 493248557Sray#define IPU_DC_UGDE0_0 0x00000174 494248557Sray#define IPU_DC_UGDE0_1 0x00000178 495248557Sray#define IPU_DC_UGDE0_2 0x0000017c 496248557Sray#define IPU_DC_UGDE0_3 0x00000180 497248557Sray#define IPU_DC_UGDE1_0 0x00000184 498248557Sray#define IPU_DC_UGDE1_1 0x00000188 499248557Sray#define IPU_DC_UGDE1_2 0x0000018c 500248557Sray#define IPU_DC_UGDE1_3 0x00000190 501248557Sray#define IPU_DC_UGDE2_0 0x00000194 502248557Sray#define IPU_DC_UGDE2_1 0x00000198 503248557Sray#define IPU_DC_UGDE2_2 0x0000019c 504248557Sray#define IPU_DC_UGDE2_3 0x000001a0 505248557Sray#define IPU_DC_UGDE3_0 0x000001a4 506248557Sray#define IPU_DC_UGDE3_1 0x000001a8 507248557Sray#define IPU_DC_UGDE3_2 0x000001ac 508248557Sray#define IPU_DC_UGDE3_3 0x000001b0 509248557Sray#define IPU_DC_LLA0 0x000001b4 510248557Sray#define IPU_DC_LLA1 0x000001b8 511248557Sray#define IPU_DC_R_LLA0 0x000001bc 512248557Sray#define IPU_DC_R_LLA1 0x000001c0 513248557Sray#define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4 514248557Sray#define IPU_DC_STAT 0x000001c8 515248557Sray 516248557Sray/* 517248557Sray * DMFC 518248557Sray * Display Multi FIFO Controller 519248557Sray */ 520248557Sray#define IPU_DMFC_RD_CHAN 0x00000000 521248557Sray#define DMFC_RD_CHAN_PPW_C 0x03000000 522248557Sray#define DMFC_RD_CHAN_WM_DR_0 0x00e00000 523248557Sray#define DMFC_RD_CHAN_WM_SET_0 0x001c0000 524248557Sray#define DMFC_RD_CHAN_WM_EN_0 0x00020000 525248557Sray#define DMFC_RD_CHAN_BURST_SIZE_0 0x000000c0 526248557Sray#define IPU_DMFC_WR_CHAN 0x00000004 527248557Sray#define DMFC_WR_CHAN_BUSRT_SIZE_2C 0xc0000000 528248557Sray#define DMFC_WR_CHAN_FIFO_SIZE_2C 0x38000000 529248557Sray#define DMFC_WR_CHAN_ST_ADDR_2C 0x07000000 530248557Sray#define DMFC_WR_CHAN_BURST_SIZE_1C 0x00c00000 531248557Sray#define DMFC_WR_CHAN_FIFO_SIZE_1C 0x00380000 532248557Sray#define DMFC_WR_CHAN_ST_ADDR_1C 0x00070000 533248557Sray#define DMFC_WR_CHAN_BURST_SIZE_2 0x0000c000 534248557Sray#define DMFC_WR_CHAN_FIFO_SIZE_2 0x00003800 535248557Sray#define DMFC_WR_CHAN_ST_ADDR_2 0x00000700 536248557Sray#define DMFC_WR_CHAN_BURST_SIZE_1 0x000000c0 537248557Sray#define DMFC_WR_CHAN_FIFO_SIZE_1 0x00000038 538248557Sray#define DMFC_WR_CHAN_ST_ADDR_1 0x00000007 539248557Sray#define IPU_DMFC_WR_CHAN_DEF 0x00000008 540248557Sray#define DMFC_WR_CHAN_DEF_WM_CLR_2C 0xe0000000 541248557Sray#define DMFC_WR_CHAN_DEF_WM_SET_2C 0x1c000000 542248557Sray#define DMFC_WR_CHAN_DEF_WM_EN_2C 0x02000000 543248557Sray#define DMFC_WR_CHAN_DEF_WM_CLR_1C 0x00e00000 544248557Sray#define DMFC_WR_CHAN_DEF_WM_SET_1C 0x001c0000 545248557Sray#define DMFC_WR_CHAN_DEF_WM_EN_1C 0x00020000 546248557Sray#define DMFC_WR_CHAN_DEF_WM_CLR_2 0x0000e000 547248557Sray#define DMFC_WR_CHAN_DEF_WM_SET_2 0x00001c00 548248557Sray#define DMFC_WR_CHAN_DEF_WM_EN_2 0x00000200 549248557Sray#define DMFC_WR_CHAN_DEF_WM_CLR_1 0x000000e0 550248557Sray#define DMFC_WR_CHAN_DEF_WM_SET_1 0x0000000c 551248557Sray#define DMFC_WR_CHAN_DEF_WM_EN_1 0x00000002 552248557Sray#define IPU_DMFC_DP_CHAN 0x0000000c 553248557Sray#define DMFC_DP_CHAN_BUSRT_SIZE_6F 0xc0000000 554248557Sray#define DMFC_DP_CHAN_FIFO_SIZE_6F 0x38000000 555248557Sray#define DMFC_DP_CHAN_ST_ADDR_6F 0x07000000 556248557Sray#define DMFC_DP_CHAN_BURST_SIZE_6B 0x00c00000 557248557Sray#define DMFC_DP_CHAN_FIFO_SIZE_6B 0x00380000 558248557Sray#define DMFC_DP_CHAN_ST_ADDR_6B 0x00070000 559248557Sray#define DMFC_DP_CHAN_BURST_SIZE_5F 0x0000c000 560248557Sray#define DMFC_DP_CHAN_FIFO_SIZE_5F 0x00003800 561248557Sray#define DMFC_DP_CHAN_ST_ADDR_5F 0x00000700 562248557Sray#define DMFC_DP_CHAN_BURST_SIZE_5B 0x000000c0 563248557Sray#define DMFC_DP_CHAN_FIFO_SIZE_5B 0x00000038 564248557Sray#define DMFC_DP_CHAN_ST_ADDR_5B 0x00000007 565248557Sray#define IPU_DMFC_DP_CHAN_DEF 0x00000010 566248557Sray#define DMFC_DP_CHAN_DEF_WM_CLR_6F 0xe0000000 567248557Sray#define DMFC_DP_CHAN_DEF_WM_SET_6F 0x1c000000 568248557Sray#define DMFC_DP_CHAN_DEF_WM_EN_6F 0x02000000 569248557Sray#define DMFC_DP_CHAN_DEF_WM_CLR_6B 0x00e00000 570248557Sray#define DMFC_DP_CHAN_DEF_WM_SET_6B 0x001c0000 571248557Sray#define DMFC_DP_CHAN_DEF_WM_EN_6B 0x00020000 572248557Sray#define DMFC_DP_CHAN_DEF_WM_CLR_5F 0x0000e000 573248557Sray#define DMFC_DP_CHAN_DEF_WM_SET_5F 0x00001c00 574248557Sray#define DMFC_DP_CHAN_DEF_WM_EN_5F 0x00000200 575248557Sray#define DMFC_DP_CHAN_DEF_WM_CLR_5B 0x000000e0 576248557Sray#define DMFC_DP_CHAN_DEF_WM_SET_5B 0x0000001c 577248557Sray#define DMFC_DP_CHAN_DEF_WM_EN_5B 0x00000002 578248557Sray#define IPU_DMFC_GENERAL1 0x00000014 579248557Sray#define DMFC_GENERAL1_WAIT4EOT_9 0x01000000 580248557Sray#define DMFC_GENERAL1_WAIT4EOT_6F 0x00800000 581248557Sray#define DMFC_GENERAL1_WAIT4EOT_6B 0x00400000 582248557Sray#define DMFC_GENERAL1_WAIT4EOT_5F 0x00200000 583248557Sray#define DMFC_GENERAL1_WAIT4EOT_5B 0x00100000 584248557Sray#define DMFC_GENERAL1_WAIT4EOT_4 0x00080000 585248557Sray#define DMFC_GENERAL1_WAIT4EOT_3 0x00040000 586248557Sray#define DMFC_GENERAL1_WAIT4EOT_2 0x00020000 587248557Sray#define DMFC_GENERAL1_WAIT4EOT_1 0x00010000 588248557Sray#define DMFC_GENERAL1_WM_CLR_9 0x0000e000 589248557Sray#define DMFC_GENERAL1_WM_SET_9 0x00001c00 590248557Sray#define DMFC_GENERAL1_BURST_SIZE_9 0x00000060 591248557Sray#define DMFC_GENERAL1_DCDP_SYNC_PR 0x00000003 592248557Sray#define DCDP_SYNC_PR_FORBIDDEN 0 593248557Sray#define DCDP_SYNC_PR_DC_DP 1 594248557Sray#define DCDP_SYNC_PR_DP_DC 2 595248557Sray#define DCDP_SYNC_PR_ROUNDROBIN 3 596248557Sray#define IPU_DMFC_GENERAL2 0x00000018 597248557Sray#define DMFC_GENERAL2_FRAME_HEIGHT_RD 0x1fff0000 598248557Sray#define DMFC_GENERAL2_FRAME_WIDTH_RD 0x00001fff 599248557Sray#define IPU_DMFC_IC_CTRL 0x0000001c 600248557Sray#define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD 0xfff80000 601248557Sray#define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD 0x0007ffc0 602248557Sray#define DMFC_IC_CTRL_IC_PPW_C 0x00000030 603248557Sray#define DMFC_IC_CTRL_IC_IN_PORT 0x00000007 604248557Sray#define IC_IN_PORT_CH28 0 605248557Sray#define IC_IN_PORT_CH41 1 606248557Sray#define IC_IN_PORT_DISABLE 2 607248557Sray#define IC_IN_PORT_CH23 4 608248557Sray#define IC_IN_PORT_CH27 5 609248557Sray#define IC_IN_PORT_CH24 6 610248557Sray#define IC_IN_PORT_CH29 7 611248557Sray#define IPU_DMFC_WR_CHAN_ALT 0x00000020 612248557Sray#define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024 613248557Sray#define IPU_DMFC_DP_CHAN_ALT 0x00000028 614248557Sray#define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c 615248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT 0xe0000000 616248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT 0x1c000000 617248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT 0x02000000 618248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT 0x00e00000 619248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT 0x001c0000 620248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT 0x00020000 621248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT 0x000000e0 622248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT 0x0000001c 623248557Sray#define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT 0x00000002 624248557Sray#define IPU_DMFC_GENERAL1_ALT 0x00000030 625248557Sray#define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT 0x00800000 626248557Sray#define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT 0x00400000 627248557Sray#define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT 0x00100000 628248557Sray#define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT 0x00020000 629248557Sray#define IPU_DMFC_STAT 0x00000034 630248557Sray#define DMFC_STAT_IC_BUFFER_EMPTY 0x02000000 631248557Sray#define DMFC_STAT_IC_BUFFER_FULL 0x01000000 632248557Sray#define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) 633248557Sray#define DMFC_STAT_FIFO_FULL(n) __BIT((n)) 634248557Sray 635248557Sray/* 636248557Sray * VCI 637248557Sray * Video De Interkacing Module 638248557Sray */ 639248557Sray#define IPU_VDI_FSIZE 0x00000000 640248557Sray#define IPU_VDI_C 0x00000004 641248557Sray 642248557Sray/* 643248557Sray * DP 644248557Sray * Display Processor 645248557Sray */ 646248557Sray#define IPU_DP_COM_CONF_SYNC 0x00000000 647248557Sray#define DP_FG_EN_SYNC 0x00000001 648248557Sray#define DP_DP_GWAM_SYNC 0x00000004 649248557Sray#define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004 650248557Sray#define IPU_DP_FG_POS_SYNC 0x00000008 651248557Sray#define IPU_DP_CUR_POS_SYNC 0x0000000c 652248557Sray#define IPU_DP_CUR_MAP_SYNC 0x00000010 653248557Sray#define IPU_DP_CSC_SYNC_0 0x00000054 654248557Sray#define IPU_DP_CSC_SYNC_1 0x00000058 655248557Sray#define IPU_DP_CUR_POS_ALT 0x0000005c 656248557Sray#define IPU_DP_COM_CONF_ASYNC0 0x00000060 657248557Sray#define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064 658248557Sray#define IPU_DP_FG_POS_ASYNC0 0x00000068 659248557Sray#define IPU_DP_CUR_POS_ASYNC0 0x0000006c 660248557Sray#define IPU_DP_CUR_MAP_ASYNC0 0x00000070 661248557Sray#define IPU_DP_CSC_ASYNC0_0 0x000000b4 662248557Sray#define IPU_DP_CSC_ASYNC0_1 0x000000b8 663248557Sray#define IPU_DP_COM_CONF_ASYNC1 0x000000bc 664248557Sray#define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0 665248557Sray#define IPU_DP_FG_POS_ASYNC1 0x000000c4 666248557Sray#define IPU_DP_CUR_POS_ASYNC1 0x000000c8 667248557Sray#define IPU_DP_CUR_MAP_ASYNC1 0x000000cc 668248557Sray#define IPU_DP_CSC_ASYNC1_0 0x00000110 669248557Sray#define IPU_DP_CSC_ASYNC1_1 0x00000114 670248557Sray 671248557Sray/* IDMA parameter */ 672248557Sray /* 673248557Sray * non-Interleaved parameter 674248557Sray * 675248557Sray * param 0: XV W0[ 9: 0] 676248557Sray * YV W0[18:10] 677248557Sray * XB W0[31:19] 678248557Sray * param 1: YB W0[43:32] 679248557Sray * NSB W0[44] 680248557Sray * CF W0[45] 681248557Sray * UBO W0[61:46] 682248557Sray * param 2: UBO W0[67:62] 683248557Sray * VBO W0[89:68] 684248557Sray * IOX W0[93:90] 685248557Sray * RDRW W0[94] 686248557Sray * Reserved W0[95] 687248557Sray * param 3: Reserved W0[112:96] 688248557Sray * S0 W0[113] 689248557Sray * BNDM W0[116:114] 690248557Sray * BM W0[118:117] 691248557Sray * ROT W0[119] 692248557Sray * HF W0[120] 693248557Sray * VF W0[121] 694248557Sray * THF W0[122] 695248557Sray * CAP W0[123] 696248557Sray * CAE W0[124] 697248557Sray * FW W0[127:125] 698248557Sray * param 4: FW W0[137:128] 699248557Sray * FH W0[149:138] 700248557Sray * param 5: EBA0 W1[28:0] 701248557Sray * EBA1 W1[31:29] 702248557Sray * param 6: EBA1 W1[57:32] 703248557Sray * ILO W1[63:58] 704248557Sray * param 7: ILO W1[77:64] 705248557Sray * NPB W1[84:78] 706248557Sray * PFS W1[88:85] 707248557Sray * ALU W1[89] 708248557Sray * ALBM W1[92:90] 709248557Sray * ID W1[94:93] 710248557Sray * TH W1[95] 711248557Sray * param 8: TH W1[101:96] 712248557Sray * SLY W1[115:102] 713248557Sray * WID3 W1[127:125] 714248557Sray * param 9: SLUV W1[141:128] 715248557Sray * CRE W1[149] 716248557Sray * 717248557Sray * Interleaved parameter 718248557Sray * 719248557Sray * param 0: XV W0[ 9: 0] 720248557Sray * YV W0[18:10] 721248557Sray * XB W0[31:19] 722248557Sray * param 1: YB W0[43:32] 723248557Sray * NSB W0[44] 724248557Sray * CF W0[45] 725248557Sray * SX W0[57:46] 726248557Sray * SY W0[61:58] 727248557Sray * param 2: SY W0[68:62] 728248557Sray * NS W0[78:69] 729248557Sray * SDX W0[85:79] 730248557Sray * SM W0[95:86] 731248557Sray * param 3: SCC W0[96] 732248557Sray * SCE W0[97] 733248557Sray * SDY W0[104:98] 734248557Sray * SDRX W0[105] 735248557Sray * SDRY W0[106] 736248557Sray * BPP W0[109:107] 737248557Sray * DEC_SEL W0[111:110] 738248557Sray * DIM W0[112] 739248557Sray * SO W0[113] 740248557Sray * BNDM W0[116:114] 741248557Sray * BM W0[118:117] 742248557Sray * ROT W0[119] 743248557Sray * HF W0[120] 744248557Sray * VF W0[121] 745248557Sray * THF W0[122] 746248557Sray * CAP W0[123] 747248557Sray * CAE W0[124] 748248557Sray * FW W0[127:125] 749248557Sray * param 4: FW W0[137:128] 750248557Sray * FH W0[149:138] 751248557Sray * param 5: EBA0 W1[28:0] 752248557Sray * EBA1 W1[31:29] 753248557Sray * param 6: EBA1 W1[57:32] 754248557Sray * ILO W1[63:58] 755248557Sray * param 7: ILO W1[77:64] 756248557Sray * NPB W1[84:78] 757248557Sray * PFS W1[88:85] 758248557Sray * ALU W1[89] 759248557Sray * ALBM W1[92:90] 760248557Sray * ID W1[94:93] 761248557Sray * TH W1[95] 762248557Sray * param 8: TH W1[101:96] 763248557Sray * SL W1[115:102] 764248557Sray * WID0 W1[118:116] 765248557Sray * WID1 W1[121:119] 766248557Sray * WID2 W1[124:122] 767248557Sray * WID3 W1[127:125] 768248557Sray * param 9: OFS0 W1[132:128] 769248557Sray * OFS1 W1[137:133] 770248557Sray * OFS2 W1[142:138] 771248557Sray * OFS3 W1[147:143] 772248557Sray * SXYS W1[148] 773248557Sray * CRE W1[149] 774248557Sray * DEC_SEL2 W1[150] 775248557Sray */ 776248557Sray 777248557Sray#define __IDMA_PARAM(word, shift, size) \ 778248557Sray ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff)) 779248557Sray 780248557Sray/* non-Interleaved parameter */ 781248557Sray/* W0 */ 782248557Sray#define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 783248557Sray#define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 784248557Sray#define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 785248557Sray#define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 786248557Sray#define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 787248557Sray#define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 788248557Sray#define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22) 789248557Sray#define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22) 790248557Sray#define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4) 791248557Sray#define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1) 792248557Sray#define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1) 793248557Sray#define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 794248557Sray#define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 795248557Sray#define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 796248557Sray#define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 797248557Sray#define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 798248557Sray#define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 799248557Sray#define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 800248557Sray#define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 801248557Sray#define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 802248557Sray#define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 803248557Sray/* W1 */ 804248557Sray#define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 805248557Sray#define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 806248557Sray#define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 807248557Sray#define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 808248557Sray#define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 809248557Sray#define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 810248557Sray#define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 811248557Sray#define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 812248557Sray#define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 813248557Sray#define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 814248557Sray#define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 815248557Sray#define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14) 816248557Sray#define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 817248557Sray 818248557Sray/* Interleaved parameter */ 819248557Sray/* W0 */ 820248557Sray#define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 821248557Sray#define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 822248557Sray#define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 823248557Sray#define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 824248557Sray#define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 825248557Sray#define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 826248557Sray#define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12) 827248557Sray#define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11) 828248557Sray#define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10) 829248557Sray#define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7) 830248557Sray#define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10) 831248557Sray#define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1) 832248557Sray#define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1) 833248557Sray#define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7) 834248557Sray#define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1) 835248557Sray#define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1) 836248557Sray#define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3) 837248557Sray#define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2) 838248557Sray#define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1) 839248557Sray#define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1) 840248557Sray#define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 841248557Sray#define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 842248557Sray#define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 843248557Sray#define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 844248557Sray#define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 845248557Sray#define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 846248557Sray#define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 847248557Sray#define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 848248557Sray#define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 849248557Sray#define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 850248557Sray/* W1 */ 851248557Sray#define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 852248557Sray#define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 853248557Sray#define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 854248557Sray#define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 855248557Sray#define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 856248557Sray#define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 857248557Sray#define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 858248557Sray#define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 859248557Sray#define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 860248557Sray#define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 861248557Sray#define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3) 862248557Sray#define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3) 863248557Sray#define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3) 864248557Sray#define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 865248557Sray#define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5) 866248557Sray#define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5) 867248557Sray#define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5) 868248557Sray#define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5) 869248557Sray#define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1) 870248557Sray#define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 871248557Sray#define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1) 872248557Sray 873248557Sray/* XXX Temp */ 874248557Sray#define GPUMEM_BASE 0x20000000 875248557Sray#define GPUMEM_SIZE 0x20000 876248557Sray 877248557Sray#define GPU_BASE 0x30000000 878248557Sray#define GPU_SIZE 0x10000000 879248557Sray 880266365Sian/* 881266365Sian * Image Processing Unit 882266365Sian * 883266365Sian * All addresses are relative to the base SoC address. 884266365Sian */ 885266365Sian#define IPU_CM_BASE(_base) ((_base) + 0x1e000000) 886266365Sian#define IPU_CM_SIZE 0x8000 887266365Sian#define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000) 888266365Sian#define IPU_IDMAC_SIZE 0x8000 889266365Sian#define IPU_DP_BASE(_base) ((_base) + 0x1e018000) 890266365Sian#define IPU_DP_SIZE 0x8000 891266365Sian#define IPU_IC_BASE(_base) ((_base) + 0x1e020000) 892266365Sian#define IPU_IC_SIZE 0x8000 893266365Sian#define IPU_IRT_BASE(_base) ((_base) + 0x1e028000) 894266365Sian#define IPU_IRT_SIZE 0x8000 895266365Sian#define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000) 896266365Sian#define IPU_CSI0_SIZE 0x8000 897266365Sian#define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000) 898266365Sian#define IPU_CSI1_SIZE 0x8000 899266365Sian#define IPU_DI0_BASE(_base) ((_base) + 0x1e040000) 900266365Sian#define IPU_DI0_SIZE 0x8000 901266365Sian#define IPU_DI1_BASE(_base) ((_base) + 0x1e048000) 902266365Sian#define IPU_DI1_SIZE 0x8000 903266365Sian#define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000) 904266365Sian#define IPU_SMFC_SIZE 0x8000 905266365Sian#define IPU_DC_BASE(_base) ((_base) + 0x1e058000) 906266365Sian#define IPU_DC_SIZE 0x8000 907266365Sian#define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000) 908266365Sian#define IPU_DMFC_SIZE 0x8000 909266365Sian#define IPU_VDI_BASE(_base) ((_base) + 0x1e068000) 910266365Sian#define IPU_VDI_SIZE 0x8000 911266365Sian#define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000) 912266365Sian#define IPU_CPMEM_SIZE 0x20000 913266365Sian#define IPU_LUT_BASE(_base) ((_base) + 0x1f020000) 914266365Sian#define IPU_LUT_SIZE 0x20000 915266365Sian#define IPU_SRM_BASE(_base) ((_base) + 0x1f040000) 916266365Sian#define IPU_SRM_SIZE 0x20000 917266365Sian#define IPU_TPM_BASE(_base) ((_base) + 0x1f060000) 918266365Sian#define IPU_TPM_SIZE 0x20000 919266365Sian#define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000) 920266365Sian#define IPU_DCTMPL_SIZE 0x20000 921248557Sray 922248557Sray#endif /* _ARM_IMX_IMX51_IPUV3REG_H */ 923