at91_pmcreg.h revision 213496
1157088Simp/*- 2157088Simp * Copyright (c) 2005 M. Warner Losh. All rights reserved. 3157088Simp * 4157088Simp * Redistribution and use in source and binary forms, with or without 5157088Simp * modification, are permitted provided that the following conditions 6157088Simp * are met: 7157088Simp * 1. Redistributions of source code must retain the above copyright 8157088Simp * notice, this list of conditions and the following disclaimer. 9157088Simp * 2. Redistributions in binary form must reproduce the above copyright 10157088Simp * notice, this list of conditions and the following disclaimer in the 11157088Simp * documentation and/or other materials provided with the distribution. 12157088Simp * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24157088Simp */ 25157088Simp 26157088Simp/* $FreeBSD: head/sys/arm/at91/at91_pmcreg.h 213496 2010-10-06 22:25:21Z cognet $ */ 27157088Simp 28157088Simp#ifndef ARM_AT91_AT91_PMCREG_H 29157088Simp#define ARM_AT91_AT91_PMCREG_H 30157088Simp 31157088Simp/* Registers */ 32157088Simp#define PMC_SCER 0x00 /* System Clock Enable Register */ 33157088Simp#define PMC_SCDR 0x04 /* System Clock Disable Register */ 34157088Simp#define PMC_SCSR 0x08 /* System Clock Status Register */ 35157088Simp /* 0x0c reserved */ 36157088Simp#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 37157088Simp#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 38157088Simp#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 39157088Simp /* 0x1c reserved */ 40157088Simp#define CKGR_MOR 0x20 /* Main Oscillator Register */ 41157088Simp#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 42157088Simp#define CKGR_PLLAR 0x28 /* PLL A Register */ 43157088Simp#define CKGR_PLLBR 0x2c /* PLL B Register */ 44157088Simp#define PMC_MCKR 0x30 /* Master Clock Register */ 45157088Simp /* 0x34 reserved */ 46157088Simp /* 0x38 reserved */ 47157088Simp /* 0x3c reserved */ 48157088Simp#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ 49157088Simp#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ 50157088Simp#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */ 51157088Simp#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */ 52157088Simp /* 0x50 reserved */ 53157088Simp /* 0x54 reserved */ 54157088Simp /* 0x58 reserved */ 55157088Simp /* 0x5c reserved */ 56157088Simp#define PMC_IER 0x60 /* Interrupt Enable Register */ 57157088Simp#define PMC_IDR 0x64 /* Interrupt Disable Register */ 58157088Simp#define PMC_SR 0x68 /* Status Register */ 59157088Simp#define PMC_IMR 0x6c /* Interrupt Mask Register */ 60157088Simp 61157088Simp/* PMC System Clock Enable Register */ 62157088Simp/* PMC System Clock Disable Register */ 63157088Simp/* PMC System Clock StatusRegister */ 64157088Simp#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */ 65157088Simp#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */ 66157088Simp#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */ 67157088Simp#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */ 68157088Simp#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */ 69213496Scognet#define PMC_SCER_PCK1 (1UL << 9) /* PCK1: Programmable Clock out en */ 70213496Scognet#define PMC_SCER_PCK2 (1UL << 10) /* PCK2: Programmable Clock out en */ 71213496Scognet#define PMC_SCER_PCK3 (1UL << 11) /* PCK3: Programmable Clock out en */ 72213496Scognet#define PMC_SCER_UHP_SAM9 (1UL << 6) /* UHP: USB Host Port Clock Enable */ 73213496Scognet#define PMC_SCER_UDP_SAM9 (1UL << 7) /* UDP: USB Device Port Clock Enable */ 74157088Simp 75157088Simp/* PMC Peripheral Clock Enable Register */ 76157088Simp/* PMC Peripheral Clock Disable Register */ 77157088Simp/* PMC Peripheral Clock Status Register */ 78157088Simp/* Each bit here is 1 << peripheral number to enable/disable/status */ 79157088Simp 80157088Simp/* PMC Clock Generator Main Oscillator Register */ 81157088Simp#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ 82157088Simp#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ 83157088Simp#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */ 84157088Simp 85157088Simp/* PMC Clock Generator Main Clock Frequency Register */ 86157088Simp#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */ 87157088Simp#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */ 88157088Simp 89213496Scognet/* PMC Clock Generator Master Clock Register */ 90213496Scognet#define PMC_MCKR_PDIV (1 << 12) /* SAM9G20 Only */ 91213496Scognet#define PMC_MCKR_PLLADIV2 (1 << 12) /* SAM9G45 Only */ 92213496Scognet#define PMC_MCKR_CSS_MASK (3 << 8) 93213496Scognet#define PMC_MCKR_MDIV_MASK (3 << 8) 94213496Scognet#define PMC_MCKR_PRES_MASK (7 << 2) 95213496Scognet 96157088Simp/* PMC Interrupt Enable Register */ 97157088Simp/* PMC Interrupt Disable Register */ 98157088Simp/* PMC Status Register */ 99157088Simp/* PMC Interrupt Mask Register */ 100157088Simp#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */ 101157088Simp#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ 102157088Simp#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ 103157088Simp#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ 104157088Simp#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ 105157088Simp#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ 106157088Simp#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ 107157088Simp#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */ 108157088Simp 109157088Simp/* 110157088Simp * PLL input frequency spec sheet says it must be between 1MHz and 32MHz, 111157088Simp * but it works down as low as 100kHz, a frequency necessary for some 112157088Simp * output frequencies to work. 113157088Simp */ 114157088Simp#define PMC_PLL_MIN_IN_FREQ 100000 115157088Simp#define PMC_PLL_MAX_IN_FREQ 32000000 116157088Simp 117157088Simp/* 118157088Simp * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 119157088Simp * for some revisions of this part. Be more permissive and optimistic. 120157088Simp */ 121157088Simp#define PMC_PLL_MAX_OUT_FREQ 240000000 122157088Simp 123157088Simp#define PMC_PLL_MULT_MIN 2 124157088Simp#define PMC_PLL_MULT_MAX 2048 125157088Simp 126157088Simp#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */ 127157088Simp 128157088Simp#define PMC_PLL_FAST_THRESH 155000000 129157088Simp 130157088Simp#endif /* ARM_AT91_AT91_PMCREG_H */ 131