at91_pmcreg.h revision 157088
1157088Simp/*- 2157088Simp * Copyright (c) 2005 M. Warner Losh. All rights reserved. 3157088Simp * 4157088Simp * Redistribution and use in source and binary forms, with or without 5157088Simp * modification, are permitted provided that the following conditions 6157088Simp * are met: 7157088Simp * 1. Redistributions of source code must retain the above copyright 8157088Simp * notice, this list of conditions and the following disclaimer. 9157088Simp * 2. Redistributions in binary form must reproduce the above copyright 10157088Simp * notice, this list of conditions and the following disclaimer in the 11157088Simp * documentation and/or other materials provided with the distribution. 12157088Simp * 13157088Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14157088Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15157088Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16157088Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17157088Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18157088Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19157088Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20157088Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21157088Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22157088Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23157088Simp */ 24157088Simp 25157088Simp/* $FreeBSD: head/sys/arm/at91/at91_pmcreg.h 157088 2006-03-24 07:37:56Z imp $ */ 26157088Simp 27157088Simp#ifndef ARM_AT91_AT91_PMCREG_H 28157088Simp#define ARM_AT91_AT91_PMCREG_H 29157088Simp 30157088Simp/* Registers */ 31157088Simp#define PMC_SCER 0x00 /* System Clock Enable Register */ 32157088Simp#define PMC_SCDR 0x04 /* System Clock Disable Register */ 33157088Simp#define PMC_SCSR 0x08 /* System Clock Status Register */ 34157088Simp /* 0x0c reserved */ 35157088Simp#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 36157088Simp#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 37157088Simp#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 38157088Simp /* 0x1c reserved */ 39157088Simp#define CKGR_MOR 0x20 /* Main Oscillator Register */ 40157088Simp#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 41157088Simp#define CKGR_PLLAR 0x28 /* PLL A Register */ 42157088Simp#define CKGR_PLLBR 0x2c /* PLL B Register */ 43157088Simp#define PMC_MCKR 0x30 /* Master Clock Register */ 44157088Simp /* 0x34 reserved */ 45157088Simp /* 0x38 reserved */ 46157088Simp /* 0x3c reserved */ 47157088Simp#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ 48157088Simp#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ 49157088Simp#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */ 50157088Simp#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */ 51157088Simp /* 0x50 reserved */ 52157088Simp /* 0x54 reserved */ 53157088Simp /* 0x58 reserved */ 54157088Simp /* 0x5c reserved */ 55157088Simp#define PMC_IER 0x60 /* Interrupt Enable Register */ 56157088Simp#define PMC_IDR 0x64 /* Interrupt Disable Register */ 57157088Simp#define PMC_SR 0x68 /* Status Register */ 58157088Simp#define PMC_IMR 0x6c /* Interrupt Mask Register */ 59157088Simp 60157088Simp/* PMC System Clock Enable Register */ 61157088Simp/* PMC System Clock Disable Register */ 62157088Simp/* PMC System Clock StatusRegister */ 63157088Simp#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */ 64157088Simp#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */ 65157088Simp#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */ 66157088Simp#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */ 67157088Simp#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */ 68157088Simp#define PMC_SCER_PCK1 (1UL << 10) /* PCK1: Programmable Clock out en */ 69157088Simp#define PMC_SCER_PCK2 (1UL << 11) /* PCK2: Programmable Clock out en */ 70157088Simp#define PMC_SCER_PCK3 (1UL << 12) /* PCK3: Programmable Clock out en */ 71157088Simp 72157088Simp/* PMC Peripheral Clock Enable Register */ 73157088Simp/* PMC Peripheral Clock Disable Register */ 74157088Simp/* PMC Peripheral Clock Status Register */ 75157088Simp/* Each bit here is 1 << peripheral number to enable/disable/status */ 76157088Simp 77157088Simp/* PMC Clock Generator Main Oscillator Register */ 78157088Simp#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ 79157088Simp#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ 80157088Simp#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */ 81157088Simp 82157088Simp/* PMC Clock Generator Main Clock Frequency Register */ 83157088Simp#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */ 84157088Simp#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */ 85157088Simp 86157088Simp/* PMC Interrupt Enable Register */ 87157088Simp/* PMC Interrupt Disable Register */ 88157088Simp/* PMC Status Register */ 89157088Simp/* PMC Interrupt Mask Register */ 90157088Simp#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */ 91157088Simp#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ 92157088Simp#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ 93157088Simp#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ 94157088Simp#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ 95157088Simp#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ 96157088Simp#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ 97157088Simp#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */ 98157088Simp 99157088Simp/* 100157088Simp * PLL input frequency spec sheet says it must be between 1MHz and 32MHz, 101157088Simp * but it works down as low as 100kHz, a frequency necessary for some 102157088Simp * output frequencies to work. 103157088Simp */ 104157088Simp#define PMC_PLL_MIN_IN_FREQ 100000 105157088Simp#define PMC_PLL_MAX_IN_FREQ 32000000 106157088Simp 107157088Simp/* 108157088Simp * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 109157088Simp * for some revisions of this part. Be more permissive and optimistic. 110157088Simp */ 111157088Simp#define PMC_PLL_MAX_OUT_FREQ 240000000 112157088Simp 113157088Simp#define PMC_PLL_MULT_MIN 2 114157088Simp#define PMC_PLL_MULT_MAX 2048 115157088Simp 116157088Simp#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */ 117157088Simp 118157088Simp#define PMC_PLL_FAST_THRESH 155000000 119157088Simp 120157088Simp#endif /* ARM_AT91_AT91_PMCREG_H */ 121