at91_pioreg.h revision 213496
1157089Simp/*- 2157089Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3157089Simp * 4157089Simp * Redistribution and use in source and binary forms, with or without 5157089Simp * modification, are permitted provided that the following conditions 6157089Simp * are met: 7157089Simp * 1. Redistributions of source code must retain the above copyright 8157089Simp * notice, this list of conditions and the following disclaimer. 9157089Simp * 2. Redistributions in binary form must reproduce the above copyright 10157089Simp * notice, this list of conditions and the following disclaimer in the 11157089Simp * documentation and/or other materials provided with the distribution. 12157089Simp * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24157089Simp */ 25157089Simp 26157089Simp/* $FreeBSD: head/sys/arm/at91/at91_pioreg.h 213496 2010-10-06 22:25:21Z cognet $ */ 27157089Simp 28157089Simp#ifndef ARM_AT91_AT91_PIOREG_H 29157089Simp#define ARM_AT91_AT91_PIOREG_H 30157089Simp 31157089Simp/* Registers */ 32157089Simp#define PIO_PER 0x00 /* PIO Enable Register */ 33157089Simp#define PIO_PDR 0x04 /* PIO Disable Register */ 34157089Simp#define PIO_PSR 0x08 /* PIO Status Register */ 35157089Simp /* 0x0c reserved */ 36157089Simp#define PIO_OER 0x10 /* PIO Output Enable Register */ 37157089Simp#define PIO_ODR 0x14 /* PIO Output Disable Register */ 38157089Simp#define PIO_OSR 0x18 /* PIO Output Status Register */ 39157089Simp /* 0x1c reserved */ 40157089Simp#define PIO_IFER 0x20 /* PIO Glitch Input Enable Register */ 41157089Simp#define PIO_IFDR 0x24 /* PIO Glitch Input Disable Register */ 42157089Simp#define PIO_IFSR 0x28 /* PIO Glitch Input Status Register */ 43157089Simp /* 0x2c reserved */ 44157089Simp#define PIO_SODR 0x30 /* PIO Set Output Data Register */ 45157089Simp#define PIO_CODR 0x34 /* PIO Clear Output Data Register */ 46157089Simp#define PIO_ODSR 0x38 /* PIO Output Data Status Register */ 47157089Simp#define PIO_PDSR 0x3c /* PIO Pin Data Status Register */ 48157089Simp#define PIO_IER 0x40 /* PIO Interrupt Enable Register */ 49157089Simp#define PIO_IDR 0x44 /* PIO Interrupt Disable Register */ 50157089Simp#define PIO_IMR 0x48 /* PIO Interrupt Mask Register */ 51157089Simp#define PIO_ISR 0x4c /* PIO Interrupt Status Register */ 52157089Simp#define PIO_MDER 0x50 /* PIO Multi-Driver Enable Register */ 53157089Simp#define PIO_MDDR 0x54 /* PIO Multi-Driver Disable Register */ 54157089Simp#define PIO_MDSR 0x58 /* PIO Multi-Driver Status Register */ 55157089Simp /* 0x5c reserved */ 56165711Simp#define PIO_PUDR 0x60 /* PIO Pull-up Disable Register */ 57165711Simp#define PIO_PUER 0x64 /* PIO Pull-up Enable Register */ 58157089Simp#define PIO_PUSR 0x68 /* PIO Pull-up Status Register */ 59157089Simp /* 0x6c reserved */ 60157089Simp#define PIO_ASR 0x70 /* PIO Peripheral A Select Register */ 61157089Simp#define PIO_BSR 0x74 /* PIO Peripheral B Select Register */ 62157089Simp#define PIO_ABSR 0x78 /* PIO AB Status Register */ 63157089Simp /* 0x7c-0x9c reserved */ 64157089Simp#define PIO_OWER 0xa0 /* PIO Output Write Enable Register */ 65157089Simp#define PIO_OWDR 0xa4 /* PIO Output Write Disable Register */ 66157089Simp#define PIO_OWSR 0xa8 /* PIO Output Write Status Register */ 67157089Simp /* 0xac reserved */ 68157089Simp 69213496Scognet#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 70213496Scognet#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 71213496Scognet#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 72213496Scognet#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 73213496Scognet#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 74213496Scognet#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 75213496Scognet#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 76213496Scognet#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 77213496Scognet#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 78213496Scognet#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 79213496Scognet#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 80213496Scognet#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 81213496Scognet#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 82213496Scognet#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 83213496Scognet#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 84213496Scognet#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 85213496Scognet#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 86213496Scognet#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 87213496Scognet#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 88213496Scognet#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 89213496Scognet#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 90213496Scognet#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 91213496Scognet#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 92213496Scognet#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 93213496Scognet#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 94213496Scognet#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 95213496Scognet#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 96213496Scognet#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 97213496Scognet#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 98213496Scognet#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 99213496Scognet#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 100213496Scognet#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 101213496Scognet#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 102213496Scognet#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 103213496Scognet#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 104213496Scognet#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 105213496Scognet#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 106213496Scognet#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 107213496Scognet#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 108213496Scognet#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 109213496Scognet#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 110213496Scognet#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 111213496Scognet#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 112213496Scognet#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 113213496Scognet#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 114213496Scognet#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 115213496Scognet#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 116213496Scognet#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 117213496Scognet#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 118213496Scognet#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 119213496Scognet#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 120213496Scognet#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 121213496Scognet#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 122213496Scognet#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 123213496Scognet#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 124213496Scognet#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 125213496Scognet#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 126213496Scognet#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 127213496Scognet#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 128213496Scognet#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 129213496Scognet#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 130213496Scognet#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 131213496Scognet#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 132213496Scognet#define AT91C_PIO_PB31 ((unsigned int) 1 << 31) // Pin Controlled by PB31 133213496Scognet#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 134213496Scognet#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 135213496Scognet#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 136213496Scognet#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3 137213496Scognet#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4 138213496Scognet#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5 139213496Scognet#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6 140213496Scognet#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7 141213496Scognet#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8 142213496Scognet#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9 143213496Scognet#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10 144213496Scognet#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11 145213496Scognet#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12 146213496Scognet#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13 147213496Scognet#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14 148213496Scognet#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15 149213496Scognet#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16 150213496Scognet#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17 151213496Scognet#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18 152213496Scognet#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19 153213496Scognet#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20 154213496Scognet#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21 155213496Scognet#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22 156213496Scognet#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23 157213496Scognet#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24 158213496Scognet#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25 159213496Scognet#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26 160213496Scognet#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27 161213496Scognet#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 162213496Scognet#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 163213496Scognet#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 164213496Scognet#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 165213496Scognet 166157089Simp#endif /* ARM_AT91_AT91_PIOREG_H */ 167