if_emacreg.h revision 296373
1/* 2 * Copyright (C) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.3/sys/arm/allwinner/if_emacreg.h 266337 2014-05-17 18:53:36Z ian $ 27 */ 28 29#ifndef __IF_EMACREG_H__ 30#define __IF_EMACREG_H__ 31 32/* 33 * EMAC register definitions 34 */ 35#define EMAC_CTL 0x00 36#define EMAC_CTL_RST (1 << 0) 37#define EMAC_CTL_TX_EN (1 << 1) 38#define EMAC_CTL_RX_EN (1 << 2) 39 40#define EMAC_TX_MODE 0x04 41#define EMAC_TX_FLOW 0x08 42#define EMAC_TX_CTL0 0x0C 43#define EMAC_TX_CTL1 0x10 44#define EMAC_TX_INS 0x14 45#define EMAC_TX_PL0 0x18 46#define EMAC_TX_PL1 0x1C 47#define EMAC_TX_STA 0x20 48#define EMAC_TX_IO_DATA 0x24 49#define EMAC_TX_IO_DATA1 0x28 50#define EMAC_TX_TSVL0 0x2C 51#define EMAC_TX_TSVH0 0x30 52#define EMAC_TX_TSVL1 0x34 53#define EMAC_TX_TSVH1 0x38 54 55#define EMAC_RX_CTL 0x3C 56#define EMAC_RX_HASH0 0x40 57#define EMAC_RX_HASH1 0x44 58#define EMAC_RX_STA 0x48 59#define EMAC_RX_IO_DATA 0x4C 60#define EMAC_RX_FBC 0x50 61 62#define EMAC_INT_CTL 0x54 63#define EMAC_INT_STA 0x58 64#define EMAC_INT_STA_TX (0x01 | 0x02) 65#define EMAC_INT_STA_RX 0x100 66#define EMAC_INT_EN (0xf << 0) | (1 << 8) 67 68#define EMAC_MAC_CTL0 0x5C 69#define EMAC_MAC_CTL1 0x60 70#define EMAC_MAC_IPGT 0x64 71#define EMAC_MAC_IPGR 0x68 72#define EMAC_MAC_CLRT 0x6C 73#define EMAC_MAC_MAXF 0x70 74#define EMAC_MAC_SUPP 0x74 75#define EMAC_MAC_TEST 0x78 76#define EMAC_MAC_MCFG 0x7C 77#define EMAC_MAC_MCMD 0x80 78#define EMAC_MAC_MADR 0x84 79#define EMAC_MAC_MWTD 0x88 80#define EMAC_MAC_MRDD 0x8C 81#define EMAC_MAC_MIND 0x90 82#define EMAC_MAC_SSRR 0x94 83#define EMAC_MAC_A0 0x98 84#define EMAC_MAC_A1 0x9C 85#define EMAC_MAC_A2 0xA0 86 87#define EMAC_SAFX_L0 0xA4 88#define EMAC_SAFX_H0 0xA8 89#define EMAC_SAFX_L1 0xAC 90#define EMAC_SAFX_H1 0xB0 91#define EMAC_SAFX_L2 0xB4 92#define EMAC_SAFX_H2 0xB8 93#define EMAC_SAFX_L3 0xBC 94#define EMAC_SAFX_H3 0xC0 95 96#define EMAC_PHY_DUPLEX (1 << 8) 97 98/* 99 * Each received packet has 8 bytes header: 100 * Byte 0: Packet valid flag: 0x01 valid, 0x00 not valid 101 * Byte 1: 0x43 -> Ascii code 'C' 102 * Byte 2: 0x41 -> Ascii code 'A' 103 * Byte 3: 0x4d -> Ascii code 'M' 104 * Byte 4: High byte of received packet's status 105 * Byte 5: Low byte of received packet's status 106 * Byte 6: High byte of packet size 107 * Byte 7: Low byte of packet size 108 */ 109#define EMAC_PACKET_HEADER (0x0143414d) 110 111/* Aborted frame enable */ 112#define EMAC_TX_AB_M (1 << 0) 113 114/* 0: Enable CPU mode for TX, 1: DMA */ 115#define EMAC_TX_TM ~(1 << 1) 116 117/* 0: DRQ asserted, 1: DRQ automatically */ 118#define EMAC_RX_DRQ_MODE (1 << 1) 119 120/* 0: Enable CPU mode for RX, 1: DMA */ 121#define EMAC_RX_TM ~(1 << 2) 122 123/* Pass all Frames */ 124#define EMAC_RX_PA (1 << 4) 125 126/* Pass Control Frames */ 127#define EMAC_RX_PCF (1 << 5) 128 129/* Pass Frames with CRC Error */ 130#define EMAC_RX_PCRCE (1 << 6) 131 132/* Pass Frames with Length Error */ 133#define EMAC_RX_PLE (1 << 7) 134 135/* Pass Frames length out of range */ 136#define EMAC_RX_POR (1 << 8) 137 138/* Accept unicast Packets */ 139#define EMAC_RX_UCAD (1 << 16) 140 141/* Enable DA Filtering */ 142#define EMAC_RX_DAF (1 << 17) 143 144/* Accept multicast Packets */ 145#define EMAC_RX_MCO (1 << 20) 146 147/* Enable Hash filter */ 148#define EMAC_RX_MHF (1 << 21) 149 150/* Accept Broadcast Packets */ 151#define EMAC_RX_BCO (1 << 22) 152 153/* Enable SA Filtering */ 154#define EMAC_RX_SAF (1 << 24) 155 156/* Inverse Filtering */ 157#define EMAC_RX_SAIF (1 << 25) 158 159#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | \ 160 EMAC_RX_DAF | EMAC_RX_MCO | EMAC_RX_BCO) 161 162/* Enable Receive Flow Control */ 163#define EMAC_MAC_CTL0_RFC (1 << 2) 164 165/* Enable Transmit Flow Control */ 166#define EMAC_MAC_CTL0_TFC (1 << 3) 167 168/* Enable soft reset */ 169#define EMAC_MAC_CTL0_SOFT_RST (1 << 15) 170 171#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) 172 173/* Enable duplex */ 174#define EMAC_MAC_CTL1_DUP (1 << 0) 175 176/* Enable MAC Frame Length Checking */ 177#define EMAC_MAC_CTL1_FLC (1 << 1) 178 179/* Enable Huge Frame */ 180#define EMAC_MAC_CTL1_HF (1 << 2) 181 182/* Enable MAC Delayed CRC */ 183#define EMAC_MAC_CTL1_DCRC (1 << 3) 184 185/* Enable MAC CRC */ 186#define EMAC_MAC_CTL1_CRC (1 << 4) 187 188/* Enable MAC PAD Short frames */ 189#define EMAC_MAC_CTL1_PC (1 << 5) 190 191/* Enable MAC PAD Short frames and append CRC */ 192#define EMAC_MAC_CTL1_VC (1 << 6) 193 194/* Enable MAC auto detect Short frames */ 195#define EMAC_MAC_CTL1_ADP (1 << 7) 196 197#define EMAC_MAC_CTL1_PRE (1 << 8) 198#define EMAC_MAC_CTL1_LPE (1 << 9) 199 200/* Enable no back off */ 201#define EMAC_MAC_CTL1_NB (1 << 12) 202 203#define EMAC_MAC_CTL1_BNB (1 << 13) 204#define EMAC_MAC_CTL1_ED (1 << 14) 205 206#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ 207 EMAC_MAC_CTL1_PC) 208 209/* half duplex */ 210#define EMAC_MAC_IPGT_HD 0x12 211 212/* full duplex */ 213#define EMAC_MAC_IPGT_FD 0x15 214 215#define EMAC_MAC_NBTB_IPG1 0xC 216#define EMAC_MAC_NBTB_IPG2 0x12 217 218#define EMAC_MAC_CW 0x37 219#define EMAC_MAC_RM 0xF 220 221#define EMAC_MAC_MFL 0x0600 222 223/* Receive status */ 224#define EMAC_CRCERR (1 << 4) 225#define EMAC_LENERR (3 << 5) 226 227#define EMAC_RX_FLUSH_FIFO (1 << 3) 228#define EMAC_PHY_RESET (1 << 15) 229#define EMAC_PHY_PWRDOWN (1 << 11) 230 231#define EMAC_PROC_MIN 16 232#define EMAC_PROC_MAX 255 233#define EMAC_PROC_DEFAULT 64 234 235#define EMAC_LOCK(cs) mtx_lock(&(sc)->emac_mtx) 236#define EMAC_UNLOCK(cs) mtx_unlock(&(sc)->emac_mtx) 237#define EMAC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->emac_mtx, MA_OWNED); 238 239#endif /* __IF_EMACREG_H__ */ 240