if_emacreg.h revision 262710
1262710Sganbold/* 2262710Sganbold * Copyright (C) 2013 Ganbold Tsagaankhuu <ganbold@gmail.com> 3262710Sganbold * All rights reserved. 4262710Sganbold * 5262710Sganbold * Redistribution and use in source and binary forms, with or without 6262710Sganbold * modification, are permitted provided that the following conditions 7262710Sganbold * are met: 8262710Sganbold * 1. Redistributions of source code must retain the above copyright 9262710Sganbold * notice, this list of conditions and the following disclaimer. 10262710Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11262710Sganbold * notice, this list of conditions and the following disclaimer in the 12262710Sganbold * documentation and/or other materials provided with the distribution. 13262710Sganbold * 14262710Sganbold * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15262710Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16262710Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17262710Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18262710Sganbold * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19262710Sganbold * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20262710Sganbold * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21262710Sganbold * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22262710Sganbold * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23262710Sganbold * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24262710Sganbold * SUCH DAMAGE. 25262710Sganbold * 26262710Sganbold * $FreeBSD: head/sys/arm/allwinner/if_emacreg.h 262710 2014-03-03 11:32:55Z ganbold $ 27262710Sganbold */ 28262710Sganbold 29262710Sganbold#ifndef __IF_EMACREG_H__ 30262710Sganbold#define __IF_EMACREG_H__ 31262710Sganbold 32262710Sganbold/* 33262710Sganbold * EMAC register definitions 34262710Sganbold */ 35262710Sganbold#define EMAC_CTL 0x00 36262710Sganbold#define EMAC_CTL_RST (1 << 0) 37262710Sganbold#define EMAC_CTL_TX_EN (1 << 1) 38262710Sganbold#define EMAC_CTL_RX_EN (1 << 2) 39262710Sganbold 40262710Sganbold#define EMAC_TX_MODE 0x04 41262710Sganbold#define EMAC_TX_FLOW 0x08 42262710Sganbold#define EMAC_TX_CTL0 0x0C 43262710Sganbold#define EMAC_TX_CTL1 0x10 44262710Sganbold#define EMAC_TX_INS 0x14 45262710Sganbold#define EMAC_TX_PL0 0x18 46262710Sganbold#define EMAC_TX_PL1 0x1C 47262710Sganbold#define EMAC_TX_STA 0x20 48262710Sganbold#define EMAC_TX_IO_DATA 0x24 49262710Sganbold#define EMAC_TX_IO_DATA1 0x28 50262710Sganbold#define EMAC_TX_TSVL0 0x2C 51262710Sganbold#define EMAC_TX_TSVH0 0x30 52262710Sganbold#define EMAC_TX_TSVL1 0x34 53262710Sganbold#define EMAC_TX_TSVH1 0x38 54262710Sganbold 55262710Sganbold#define EMAC_RX_CTL 0x3C 56262710Sganbold#define EMAC_RX_HASH0 0x40 57262710Sganbold#define EMAC_RX_HASH1 0x44 58262710Sganbold#define EMAC_RX_STA 0x48 59262710Sganbold#define EMAC_RX_IO_DATA 0x4C 60262710Sganbold#define EMAC_RX_FBC 0x50 61262710Sganbold 62262710Sganbold#define EMAC_INT_CTL 0x54 63262710Sganbold#define EMAC_INT_STA 0x58 64262710Sganbold#define EMAC_INT_STA_TX (0x01 | 0x02) 65262710Sganbold#define EMAC_INT_STA_RX 0x100 66262710Sganbold#define EMAC_INT_EN (0xf << 0) | (1 << 8) 67262710Sganbold 68262710Sganbold#define EMAC_MAC_CTL0 0x5C 69262710Sganbold#define EMAC_MAC_CTL1 0x60 70262710Sganbold#define EMAC_MAC_IPGT 0x64 71262710Sganbold#define EMAC_MAC_IPGR 0x68 72262710Sganbold#define EMAC_MAC_CLRT 0x6C 73262710Sganbold#define EMAC_MAC_MAXF 0x70 74262710Sganbold#define EMAC_MAC_SUPP 0x74 75262710Sganbold#define EMAC_MAC_TEST 0x78 76262710Sganbold#define EMAC_MAC_MCFG 0x7C 77262710Sganbold#define EMAC_MAC_MCMD 0x80 78262710Sganbold#define EMAC_MAC_MADR 0x84 79262710Sganbold#define EMAC_MAC_MWTD 0x88 80262710Sganbold#define EMAC_MAC_MRDD 0x8C 81262710Sganbold#define EMAC_MAC_MIND 0x90 82262710Sganbold#define EMAC_MAC_SSRR 0x94 83262710Sganbold#define EMAC_MAC_A0 0x98 84262710Sganbold#define EMAC_MAC_A1 0x9C 85262710Sganbold#define EMAC_MAC_A2 0xA0 86262710Sganbold 87262710Sganbold#define EMAC_SAFX_L0 0xA4 88262710Sganbold#define EMAC_SAFX_H0 0xA8 89262710Sganbold#define EMAC_SAFX_L1 0xAC 90262710Sganbold#define EMAC_SAFX_H1 0xB0 91262710Sganbold#define EMAC_SAFX_L2 0xB4 92262710Sganbold#define EMAC_SAFX_H2 0xB8 93262710Sganbold#define EMAC_SAFX_L3 0xBC 94262710Sganbold#define EMAC_SAFX_H3 0xC0 95262710Sganbold 96262710Sganbold#define EMAC_PHY_DUPLEX (1 << 8) 97262710Sganbold 98262710Sganbold/* 99262710Sganbold * Each received packet has 8 bytes header: 100262710Sganbold * Byte 0: Packet valid flag: 0x01 valid, 0x00 not valid 101262710Sganbold * Byte 1: 0x43 -> Ascii code 'C' 102262710Sganbold * Byte 2: 0x41 -> Ascii code 'A' 103262710Sganbold * Byte 3: 0x4d -> Ascii code 'M' 104262710Sganbold * Byte 4: High byte of received packet's status 105262710Sganbold * Byte 5: Low byte of received packet's status 106262710Sganbold * Byte 6: High byte of packet size 107262710Sganbold * Byte 7: Low byte of packet size 108262710Sganbold */ 109262710Sganbold#define EMAC_PACKET_HEADER (0x0143414d) 110262710Sganbold 111262710Sganbold/* Aborted frame enable */ 112262710Sganbold#define EMAC_TX_AB_M (1 << 0) 113262710Sganbold 114262710Sganbold/* 0: Enable CPU mode for TX, 1: DMA */ 115262710Sganbold#define EMAC_TX_TM ~(1 << 1) 116262710Sganbold 117262710Sganbold/* 0: DRQ asserted, 1: DRQ automatically */ 118262710Sganbold#define EMAC_RX_DRQ_MODE (1 << 1) 119262710Sganbold 120262710Sganbold/* 0: Enable CPU mode for RX, 1: DMA */ 121262710Sganbold#define EMAC_RX_TM ~(1 << 2) 122262710Sganbold 123262710Sganbold/* Pass all Frames */ 124262710Sganbold#define EMAC_RX_PA (1 << 4) 125262710Sganbold 126262710Sganbold/* Pass Control Frames */ 127262710Sganbold#define EMAC_RX_PCF (1 << 5) 128262710Sganbold 129262710Sganbold/* Pass Frames with CRC Error */ 130262710Sganbold#define EMAC_RX_PCRCE (1 << 6) 131262710Sganbold 132262710Sganbold/* Pass Frames with Length Error */ 133262710Sganbold#define EMAC_RX_PLE (1 << 7) 134262710Sganbold 135262710Sganbold/* Pass Frames length out of range */ 136262710Sganbold#define EMAC_RX_POR (1 << 8) 137262710Sganbold 138262710Sganbold/* Accept unicast Packets */ 139262710Sganbold#define EMAC_RX_UCAD (1 << 16) 140262710Sganbold 141262710Sganbold/* Enable DA Filtering */ 142262710Sganbold#define EMAC_RX_DAF (1 << 17) 143262710Sganbold 144262710Sganbold/* Accept multicast Packets */ 145262710Sganbold#define EMAC_RX_MCO (1 << 20) 146262710Sganbold 147262710Sganbold/* Enable Hash filter */ 148262710Sganbold#define EMAC_RX_MHF (1 << 21) 149262710Sganbold 150262710Sganbold/* Accept Broadcast Packets */ 151262710Sganbold#define EMAC_RX_BCO (1 << 22) 152262710Sganbold 153262710Sganbold/* Enable SA Filtering */ 154262710Sganbold#define EMAC_RX_SAF (1 << 24) 155262710Sganbold 156262710Sganbold/* Inverse Filtering */ 157262710Sganbold#define EMAC_RX_SAIF (1 << 25) 158262710Sganbold 159262710Sganbold#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | \ 160262710Sganbold EMAC_RX_DAF | EMAC_RX_MCO | EMAC_RX_BCO) 161262710Sganbold 162262710Sganbold/* Enable Receive Flow Control */ 163262710Sganbold#define EMAC_MAC_CTL0_RFC (1 << 2) 164262710Sganbold 165262710Sganbold/* Enable Transmit Flow Control */ 166262710Sganbold#define EMAC_MAC_CTL0_TFC (1 << 3) 167262710Sganbold 168262710Sganbold/* Enable soft reset */ 169262710Sganbold#define EMAC_MAC_CTL0_SOFT_RST (1 << 15) 170262710Sganbold 171262710Sganbold#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) 172262710Sganbold 173262710Sganbold/* Enable duplex */ 174262710Sganbold#define EMAC_MAC_CTL1_DUP (1 << 0) 175262710Sganbold 176262710Sganbold/* Enable MAC Frame Length Checking */ 177262710Sganbold#define EMAC_MAC_CTL1_FLC (1 << 1) 178262710Sganbold 179262710Sganbold/* Enable Huge Frame */ 180262710Sganbold#define EMAC_MAC_CTL1_HF (1 << 2) 181262710Sganbold 182262710Sganbold/* Enable MAC Delayed CRC */ 183262710Sganbold#define EMAC_MAC_CTL1_DCRC (1 << 3) 184262710Sganbold 185262710Sganbold/* Enable MAC CRC */ 186262710Sganbold#define EMAC_MAC_CTL1_CRC (1 << 4) 187262710Sganbold 188262710Sganbold/* Enable MAC PAD Short frames */ 189262710Sganbold#define EMAC_MAC_CTL1_PC (1 << 5) 190262710Sganbold 191262710Sganbold/* Enable MAC PAD Short frames and append CRC */ 192262710Sganbold#define EMAC_MAC_CTL1_VC (1 << 6) 193262710Sganbold 194262710Sganbold/* Enable MAC auto detect Short frames */ 195262710Sganbold#define EMAC_MAC_CTL1_ADP (1 << 7) 196262710Sganbold 197262710Sganbold#define EMAC_MAC_CTL1_PRE (1 << 8) 198262710Sganbold#define EMAC_MAC_CTL1_LPE (1 << 9) 199262710Sganbold 200262710Sganbold/* Enable no back off */ 201262710Sganbold#define EMAC_MAC_CTL1_NB (1 << 12) 202262710Sganbold 203262710Sganbold#define EMAC_MAC_CTL1_BNB (1 << 13) 204262710Sganbold#define EMAC_MAC_CTL1_ED (1 << 14) 205262710Sganbold 206262710Sganbold#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ 207262710Sganbold EMAC_MAC_CTL1_PC) 208262710Sganbold 209262710Sganbold/* half duplex */ 210262710Sganbold#define EMAC_MAC_IPGT_HD 0x12 211262710Sganbold 212262710Sganbold/* full duplex */ 213262710Sganbold#define EMAC_MAC_IPGT_FD 0x15 214262710Sganbold 215262710Sganbold#define EMAC_MAC_NBTB_IPG1 0xC 216262710Sganbold#define EMAC_MAC_NBTB_IPG2 0x12 217262710Sganbold 218262710Sganbold#define EMAC_MAC_CW 0x37 219262710Sganbold#define EMAC_MAC_RM 0xF 220262710Sganbold 221262710Sganbold#define EMAC_MAC_MFL 0x0600 222262710Sganbold 223262710Sganbold/* Receive status */ 224262710Sganbold#define EMAC_CRCERR (1 << 4) 225262710Sganbold#define EMAC_LENERR (3 << 5) 226262710Sganbold 227262710Sganbold#define EMAC_RX_FLUSH_FIFO (1 << 3) 228262710Sganbold#define EMAC_PHY_RESET (1 << 15) 229262710Sganbold#define EMAC_PHY_PWRDOWN (1 << 11) 230262710Sganbold 231262710Sganbold#define EMAC_PROC_MIN 16 232262710Sganbold#define EMAC_PROC_MAX 255 233262710Sganbold#define EMAC_PROC_DEFAULT 64 234262710Sganbold 235262710Sganbold#define EMAC_LOCK(cs) mtx_lock(&(sc)->emac_mtx) 236262710Sganbold#define EMAC_UNLOCK(cs) mtx_unlock(&(sc)->emac_mtx) 237262710Sganbold#define EMAC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->emac_mtx, MA_OWNED); 238262710Sganbold 239262710Sganbold#endif /* __IF_EMACREG_H__ */ 240