vlapic_priv.h revision 259863
1/*- 2 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/amd64/vmm/io/vlapic_priv.h 259863 2013-12-25 06:46:31Z neel $ 27 */ 28 29#ifndef _VLAPIC_PRIV_H_ 30#define _VLAPIC_PRIV_H_ 31 32/* 33 * APIC Register: Offset Description 34 */ 35#define APIC_OFFSET_ID 0x20 /* Local APIC ID */ 36#define APIC_OFFSET_VER 0x30 /* Local APIC Version */ 37#define APIC_OFFSET_TPR 0x80 /* Task Priority Register */ 38#define APIC_OFFSET_APR 0x90 /* Arbitration Priority */ 39#define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */ 40#define APIC_OFFSET_EOI 0xB0 /* EOI Register */ 41#define APIC_OFFSET_RRR 0xC0 /* Remote read */ 42#define APIC_OFFSET_LDR 0xD0 /* Logical Destination */ 43#define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */ 44#define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */ 45#define APIC_OFFSET_ISR0 0x100 /* In Service Register */ 46#define APIC_OFFSET_ISR1 0x110 47#define APIC_OFFSET_ISR2 0x120 48#define APIC_OFFSET_ISR3 0x130 49#define APIC_OFFSET_ISR4 0x140 50#define APIC_OFFSET_ISR5 0x150 51#define APIC_OFFSET_ISR6 0x160 52#define APIC_OFFSET_ISR7 0x170 53#define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */ 54#define APIC_OFFSET_TMR1 0x190 55#define APIC_OFFSET_TMR2 0x1A0 56#define APIC_OFFSET_TMR3 0x1B0 57#define APIC_OFFSET_TMR4 0x1C0 58#define APIC_OFFSET_TMR5 0x1D0 59#define APIC_OFFSET_TMR6 0x1E0 60#define APIC_OFFSET_TMR7 0x1F0 61#define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */ 62#define APIC_OFFSET_IRR1 0x210 63#define APIC_OFFSET_IRR2 0x220 64#define APIC_OFFSET_IRR3 0x230 65#define APIC_OFFSET_IRR4 0x240 66#define APIC_OFFSET_IRR5 0x250 67#define APIC_OFFSET_IRR6 0x260 68#define APIC_OFFSET_IRR7 0x270 69#define APIC_OFFSET_ESR 0x280 /* Error Status Register */ 70#define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */ 71#define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */ 72#define APIC_OFFSET_ICR_HI 0x310 73#define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */ 74#define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */ 75#define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */ 76#define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */ 77#define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */ 78#define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */ 79#define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */ 80#define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */ 81#define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */ 82 83enum boot_state { 84 BS_INIT, 85 BS_SIPI, 86 BS_RUNNING 87}; 88 89/* 90 * 16 priority levels with at most one vector injected per level. 91 */ 92#define ISRVEC_STK_SIZE (16 + 1) 93 94struct vlapic { 95 struct vm *vm; 96 int vcpuid; 97 struct LAPIC *apic_page; 98 99 uint32_t esr_pending; 100 int esr_firing; 101 102 struct callout callout; /* vlapic timer */ 103 struct bintime timer_fire_bt; /* callout expiry time */ 104 struct bintime timer_freq_bt; /* timer frequency */ 105 struct bintime timer_period_bt; /* timer period */ 106 struct mtx timer_mtx; 107 108 /* 109 * The 'isrvec_stk' is a stack of vectors injected by the local apic. 110 * A vector is popped from the stack when the processor does an EOI. 111 * The vector on the top of the stack is used to compute the 112 * Processor Priority in conjunction with the TPR. 113 */ 114 uint8_t isrvec_stk[ISRVEC_STK_SIZE]; 115 int isrvec_stk_top; 116 117 uint64_t msr_apicbase; 118 enum boot_state boot_state; 119}; 120 121void vlapic_init(struct vlapic *vlapic); 122void vlapic_cleanup(struct vlapic *vlapic); 123 124#endif /* _VLAPIC_PRIV_H_ */ 125