1249130Sneel/*- 2249130Sneel * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 3249130Sneel * All rights reserved. 4249130Sneel * 5249130Sneel * Redistribution and use in source and binary forms, with or without 6249130Sneel * modification, are permitted provided that the following conditions 7249130Sneel * are met: 8249130Sneel * 1. Redistributions of source code must retain the above copyright 9249967Sneel * notice unmodified, this list of conditions, and the following 10249967Sneel * disclaimer. 11249130Sneel * 2. Redistributions in binary form must reproduce the above copyright 12249130Sneel * notice, this list of conditions and the following disclaimer in the 13249130Sneel * documentation and/or other materials provided with the distribution. 14249130Sneel * 15249967Sneel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16249967Sneel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17249967Sneel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18249967Sneel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19249967Sneel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20249967Sneel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21249967Sneel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22249967Sneel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23249967Sneel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24249967Sneel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25249130Sneel * 26249130Sneel * $FreeBSD: releng/10.3/sys/amd64/vmm/amd/vmcb.h 276403 2014-12-30 08:24:14Z neel $ 27249130Sneel */ 28249130Sneel 29249130Sneel#ifndef _VMCB_H_ 30249130Sneel#define _VMCB_H_ 31249130Sneel 32271939Sneelstruct svm_softc; 33271939Sneel 34272929Sneel#define BIT(n) (1ULL << n) 35272929Sneel 36249130Sneel/* 37249130Sneel * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 38249130Sneel * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 39249130Sneel */ 40249130Sneel 41271348Sneel/* vmcb_ctrl->intercept[] array indices */ 42271348Sneel#define VMCB_CR_INTCPT 0 43271348Sneel#define VMCB_DR_INTCPT 1 44271348Sneel#define VMCB_EXC_INTCPT 2 45271348Sneel#define VMCB_CTRL1_INTCPT 3 46271348Sneel#define VMCB_CTRL2_INTCPT 4 47271348Sneel 48271348Sneel/* intercept[VMCB_CTRL1_INTCPT] fields */ 49249130Sneel#define VMCB_INTCPT_INTR BIT(0) 50249130Sneel#define VMCB_INTCPT_NMI BIT(1) 51249130Sneel#define VMCB_INTCPT_SMI BIT(2) 52249130Sneel#define VMCB_INTCPT_INIT BIT(3) 53249130Sneel#define VMCB_INTCPT_VINTR BIT(4) 54249130Sneel#define VMCB_INTCPT_CR0_WRITE BIT(5) 55249130Sneel#define VMCB_INTCPT_IDTR_READ BIT(6) 56249130Sneel#define VMCB_INTCPT_GDTR_READ BIT(7) 57249130Sneel#define VMCB_INTCPT_LDTR_READ BIT(8) 58249130Sneel#define VMCB_INTCPT_TR_READ BIT(9) 59249130Sneel#define VMCB_INTCPT_IDTR_WRITE BIT(10) 60249130Sneel#define VMCB_INTCPT_GDTR_WRITE BIT(11) 61249130Sneel#define VMCB_INTCPT_LDTR_WRITE BIT(12) 62249130Sneel#define VMCB_INTCPT_TR_WRITE BIT(13) 63249130Sneel#define VMCB_INTCPT_RDTSC BIT(14) 64249130Sneel#define VMCB_INTCPT_RDPMC BIT(15) 65249130Sneel#define VMCB_INTCPT_PUSHF BIT(16) 66249130Sneel#define VMCB_INTCPT_POPF BIT(17) 67249130Sneel#define VMCB_INTCPT_CPUID BIT(18) 68249130Sneel#define VMCB_INTCPT_RSM BIT(19) 69249130Sneel#define VMCB_INTCPT_IRET BIT(20) 70249130Sneel#define VMCB_INTCPT_INTn BIT(21) 71249130Sneel#define VMCB_INTCPT_INVD BIT(22) 72249130Sneel#define VMCB_INTCPT_PAUSE BIT(23) 73249130Sneel#define VMCB_INTCPT_HLT BIT(24) 74249130Sneel#define VMCB_INTCPT_INVPG BIT(25) 75249130Sneel#define VMCB_INTCPT_INVPGA BIT(26) 76249130Sneel#define VMCB_INTCPT_IO BIT(27) 77249130Sneel#define VMCB_INTCPT_MSR BIT(28) 78249130Sneel#define VMCB_INTCPT_TASK_SWITCH BIT(29) 79249130Sneel#define VMCB_INTCPT_FERR_FREEZE BIT(30) 80249130Sneel#define VMCB_INTCPT_SHUTDOWN BIT(31) 81249130Sneel 82271348Sneel/* intercept[VMCB_CTRL2_INTCPT] fields */ 83249130Sneel#define VMCB_INTCPT_VMRUN BIT(0) 84249130Sneel#define VMCB_INTCPT_VMMCALL BIT(1) 85249130Sneel#define VMCB_INTCPT_VMLOAD BIT(2) 86249130Sneel#define VMCB_INTCPT_VMSAVE BIT(3) 87249130Sneel#define VMCB_INTCPT_STGI BIT(4) 88249130Sneel#define VMCB_INTCPT_CLGI BIT(5) 89249130Sneel#define VMCB_INTCPT_SKINIT BIT(6) 90249130Sneel#define VMCB_INTCPT_RDTSCP BIT(7) 91249130Sneel#define VMCB_INTCPT_ICEBP BIT(8) 92249130Sneel#define VMCB_INTCPT_WBINVD BIT(9) 93249130Sneel#define VMCB_INTCPT_MONITOR BIT(10) 94249130Sneel#define VMCB_INTCPT_MWAIT BIT(11) 95249130Sneel#define VMCB_INTCPT_MWAIT_ARMED BIT(12) 96249130Sneel#define VMCB_INTCPT_XSETBV BIT(13) 97249130Sneel 98249130Sneel/* VMCB TLB control */ 99249130Sneel#define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 100259579Sgrehan#define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 101249130Sneel#define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 102249130Sneel#define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 103249130Sneel 104249130Sneel/* VMCB state caching */ 105271348Sneel#define VMCB_CACHE_NONE 0 /* No caching */ 106271348Sneel#define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */ 107271348Sneel#define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 108271348Sneel#define VMCB_CACHE_ASID BIT(2) /* ASID */ 109271348Sneel#define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 110271348Sneel#define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 111271348Sneel#define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 112271348Sneel#define VMCB_CACHE_DR BIT(6) /* Debug registers */ 113271348Sneel#define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 114271348Sneel#define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 115271348Sneel#define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 116271348Sneel#define VMCB_CACHE_LBR BIT(10) /* Last branch */ 117249130Sneel 118249130Sneel/* VMCB control event injection */ 119249130Sneel#define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 120249130Sneel#define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 121249130Sneel 122249130Sneel/* Event types that can be injected */ 123249130Sneel#define VMCB_EVENTINJ_TYPE_INTR 0 124249130Sneel#define VMCB_EVENTINJ_TYPE_NMI 2 125249130Sneel#define VMCB_EVENTINJ_TYPE_EXCEPTION 3 126249130Sneel#define VMCB_EVENTINJ_TYPE_INTn 4 127249130Sneel 128249130Sneel/* VMCB exit code, APM vol2 Appendix C */ 129249130Sneel#define VMCB_EXIT_MC 0x52 130249130Sneel#define VMCB_EXIT_INTR 0x60 131271559Sneel#define VMCB_EXIT_NMI 0x61 132271343Sneel#define VMCB_EXIT_VINTR 0x64 133249130Sneel#define VMCB_EXIT_PUSHF 0x70 134249130Sneel#define VMCB_EXIT_POPF 0x71 135249130Sneel#define VMCB_EXIT_CPUID 0x72 136249130Sneel#define VMCB_EXIT_IRET 0x74 137249130Sneel#define VMCB_EXIT_PAUSE 0x77 138249130Sneel#define VMCB_EXIT_HLT 0x78 139249130Sneel#define VMCB_EXIT_IO 0x7B 140249130Sneel#define VMCB_EXIT_MSR 0x7C 141249130Sneel#define VMCB_EXIT_SHUTDOWN 0x7F 142249130Sneel#define VMCB_EXIT_VMSAVE 0x83 143276403Sneel#define VMCB_EXIT_MONITOR 0x8A 144276403Sneel#define VMCB_EXIT_MWAIT 0x8B 145249130Sneel#define VMCB_EXIT_NPF 0x400 146249130Sneel#define VMCB_EXIT_INVALID -1 147249130Sneel 148249130Sneel/* 149249130Sneel * Nested page fault. 150249130Sneel * Bit definitions to decode EXITINFO1. 151249130Sneel */ 152249130Sneel#define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */ 153249130Sneel#define VMCB_NPF_INFO1_W BIT(1) /* Access was write. */ 154249130Sneel#define VMCB_NPF_INFO1_U BIT(2) /* Access was user access. */ 155249130Sneel#define VMCB_NPF_INFO1_RSV BIT(3) /* Reserved bits present. */ 156249130Sneel#define VMCB_NPF_INFO1_ID BIT(4) /* Code read. */ 157249130Sneel 158249130Sneel#define VMCB_NPF_INFO1_GPA BIT(32) /* Guest physical address. */ 159249130Sneel#define VMCB_NPF_INFO1_GPT BIT(33) /* Guest page table. */ 160249130Sneel 161259579Sgrehan/* 162259579Sgrehan * EXITINTINFO, Interrupt exit info for all intrecepts. 163259579Sgrehan * Section 15.7.2, Intercepts during IDT Interrupt Delivery. 164259579Sgrehan */ 165270511Sneel#define VMCB_EXITINTINFO_VECTOR(x) ((x) & 0xFF) 166270511Sneel#define VMCB_EXITINTINFO_TYPE(x) (((x) >> 8) & 0x7) 167270511Sneel#define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) ? 1 : 0) 168270511Sneel#define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) ? 1 : 0) 169270511Sneel#define VMCB_EXITINTINFO_EC(x) (((x) >> 32) & 0xFFFFFFFF) 170259579Sgrehan 171272916Sneel/* Offset of various VMCB fields. */ 172272916Sneel#define VMCB_OFF_CTRL(x) (x) 173272916Sneel#define VMCB_OFF_STATE(x) ((x) + 0x400) 174272916Sneel 175272916Sneel#define VMCB_OFF_CR_INTERCEPT VMCB_OFF_CTRL(0x0) 176272916Sneel#define VMCB_OFF_DR_INTERCEPT VMCB_OFF_CTRL(0x4) 177272916Sneel#define VMCB_OFF_EXC_INTERCEPT VMCB_OFF_CTRL(0x8) 178272916Sneel#define VMCB_OFF_INST1_INTERCEPT VMCB_OFF_CTRL(0xC) 179272916Sneel#define VMCB_OFF_INST2_INTERCEPT VMCB_OFF_CTRL(0x10) 180272916Sneel#define VMCB_OFF_IO_PERM VMCB_OFF_CTRL(0x40) 181272916Sneel#define VMCB_OFF_MSR_PERM VMCB_OFF_CTRL(0x48) 182272916Sneel#define VMCB_OFF_TSC_OFFSET VMCB_OFF_CTRL(0x50) 183272916Sneel#define VMCB_OFF_ASID VMCB_OFF_CTRL(0x58) 184272916Sneel#define VMCB_OFF_TLB_CTRL VMCB_OFF_CTRL(0x5C) 185272916Sneel#define VMCB_OFF_VIRQ VMCB_OFF_CTRL(0x60) 186272916Sneel#define VMCB_OFF_EXIT_REASON VMCB_OFF_CTRL(0x70) 187272916Sneel#define VMCB_OFF_EXITINFO1 VMCB_OFF_CTRL(0x78) 188272916Sneel#define VMCB_OFF_EXITINFO2 VMCB_OFF_CTRL(0x80) 189272916Sneel#define VMCB_OFF_EXITINTINFO VMCB_OFF_CTRL(0x88) 190272916Sneel#define VMCB_OFF_AVIC_BAR VMCB_OFF_CTRL(0x98) 191272916Sneel#define VMCB_OFF_NPT_BASE VMCB_OFF_CTRL(0xB0) 192272916Sneel#define VMCB_OFF_AVIC_PAGE VMCB_OFF_CTRL(0xE0) 193272916Sneel#define VMCB_OFF_AVIC_LT VMCB_OFF_CTRL(0xF0) 194272916Sneel#define VMCB_OFF_AVIC_PT VMCB_OFF_CTRL(0xF8) 195272916Sneel#define VMCB_OFF_SYSENTER_CS VMCB_OFF_STATE(0x228) 196272916Sneel#define VMCB_OFF_SYSENTER_ESP VMCB_OFF_STATE(0x230) 197272916Sneel#define VMCB_OFF_SYSENTER_EIP VMCB_OFF_STATE(0x238) 198272916Sneel#define VMCB_OFF_GUEST_PAT VMCB_OFF_STATE(0x268) 199272916Sneel 200272916Sneel/* 201272916Sneel * Encode the VMCB offset and bytes that we want to read from VMCB. 202272916Sneel */ 203272916Sneel#define VMCB_ACCESS(o, w) (0x80000000 | (((w) & 0xF) << 16) | \ 204272916Sneel ((o) & 0xFFF)) 205272916Sneel#define VMCB_ACCESS_OK(v) ((v) & 0x80000000 ) 206272916Sneel#define VMCB_ACCESS_BYTES(v) (((v) >> 16) & 0xF) 207272916Sneel#define VMCB_ACCESS_OFFSET(v) ((v) & 0xFFF) 208272916Sneel 209272916Sneel#ifdef _KERNEL 210249130Sneel/* VMCB save state area segment format */ 211249130Sneelstruct vmcb_segment { 212249130Sneel uint16_t selector; 213249130Sneel uint16_t attrib; 214249130Sneel uint32_t limit; 215249130Sneel uint64_t base; 216249130Sneel} __attribute__ ((__packed__)); 217249130SneelCTASSERT(sizeof(struct vmcb_segment) == 16); 218249130Sneel 219270962Sneel/* Code segment descriptor attribute in 12 bit format as saved by VMCB. */ 220270962Sneel#define VMCB_CS_ATTRIB_L BIT(9) /* Long mode. */ 221270962Sneel#define VMCB_CS_ATTRIB_D BIT(10) /* OPerand size bit. */ 222270962Sneel 223249130Sneel/* 224249130Sneel * The VMCB is divided into two areas - the first one contains various 225249130Sneel * control bits including the intercept vector and the second one contains 226249130Sneel * the guest state. 227249130Sneel */ 228249130Sneel 229249130Sneel/* VMCB control area - padded up to 1024 bytes */ 230249130Sneelstruct vmcb_ctrl { 231271348Sneel uint32_t intercept[5]; /* all intercepts */ 232249130Sneel uint8_t pad1[0x28]; /* Offsets 0x14-0x3B are reserved. */ 233249130Sneel uint16_t pause_filthresh; /* Offset 0x3C, PAUSE filter threshold */ 234249130Sneel uint16_t pause_filcnt; /* Offset 0x3E, PAUSE filter count */ 235249130Sneel uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 236249130Sneel uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 237249130Sneel uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 238249130Sneel uint32_t asid; /* 0x58: Guest ASID */ 239249130Sneel uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ 240249130Sneel uint8_t pad2[3]; /* 0x5D-0x5F: Reserved. */ 241249130Sneel uint8_t v_tpr; /* 0x60: V_TPR, guest CR8 */ 242249130Sneel uint8_t v_irq:1; /* Is virtual interrupt pending? */ 243249130Sneel uint8_t :7; /* Padding */ 244249130Sneel uint8_t v_intr_prio:4; /* 0x62: Priority for virtual interrupt. */ 245249130Sneel uint8_t v_ign_tpr:1; 246249130Sneel uint8_t :3; 247249130Sneel uint8_t v_intr_masking:1; /* Guest and host sharing of RFLAGS. */ 248249130Sneel uint8_t :7; 249249130Sneel uint8_t v_intr_vector; /* 0x65: Vector for virtual interrupt. */ 250249130Sneel uint8_t pad3[3]; /* Bit64-40 Reserved. */ 251249130Sneel uint64_t intr_shadow:1; /* 0x68: Interrupt shadow, section15.2.1 APM2 */ 252249130Sneel uint64_t :63; 253249130Sneel uint64_t exitcode; /* 0x70, Exitcode */ 254249130Sneel uint64_t exitinfo1; /* 0x78, EXITINFO1 */ 255249130Sneel uint64_t exitinfo2; /* 0x80, EXITINFO2 */ 256249130Sneel uint64_t exitintinfo; /* 0x88, Interrupt exit value. */ 257249130Sneel uint64_t np_enable:1; /* 0x90, Nested paging enable. */ 258249130Sneel uint64_t :63; 259249130Sneel uint8_t pad4[0x10]; /* 0x98-0xA7 reserved. */ 260249130Sneel uint64_t eventinj; /* 0xA8, Event injection. */ 261249130Sneel uint64_t n_cr3; /* B0, Nested page table. */ 262249130Sneel uint64_t lbr_virt_en:1; /* Enable LBR virtualization. */ 263249130Sneel uint64_t :63; 264249130Sneel uint32_t vmcb_clean; /* 0xC0: VMCB clean bits for caching */ 265249130Sneel uint32_t :32; /* 0xC4: Reserved */ 266249130Sneel uint64_t nrip; /* 0xC8: Guest next nRIP. */ 267271554Sneel uint8_t inst_len; /* 0xD0: #NPF decode assist */ 268271554Sneel uint8_t inst_bytes[15]; 269249130Sneel uint8_t padd6[0x320]; 270249130Sneel} __attribute__ ((__packed__)); 271249130SneelCTASSERT(sizeof(struct vmcb_ctrl) == 1024); 272249130Sneel 273249130Sneelstruct vmcb_state { 274249130Sneel struct vmcb_segment es; 275249130Sneel struct vmcb_segment cs; 276249130Sneel struct vmcb_segment ss; 277249130Sneel struct vmcb_segment ds; 278249130Sneel struct vmcb_segment fs; 279249130Sneel struct vmcb_segment gs; 280249130Sneel struct vmcb_segment gdt; 281249130Sneel struct vmcb_segment ldt; 282249130Sneel struct vmcb_segment idt; 283249130Sneel struct vmcb_segment tr; 284249130Sneel uint8_t pad1[0x2b]; /* Reserved: 0xA0-0xCA */ 285249130Sneel uint8_t cpl; 286249130Sneel uint8_t pad2[4]; 287249130Sneel uint64_t efer; 288249130Sneel uint8_t pad3[0x70]; /* Reserved: 0xd8-0x147 */ 289249130Sneel uint64_t cr4; 290249130Sneel uint64_t cr3; /* Guest CR3 */ 291249130Sneel uint64_t cr0; 292249130Sneel uint64_t dr7; 293249130Sneel uint64_t dr6; 294249130Sneel uint64_t rflags; 295249130Sneel uint64_t rip; 296249130Sneel uint8_t pad4[0x58]; /* Reserved: 0x180-0x1D7 */ 297249130Sneel uint64_t rsp; 298249130Sneel uint8_t pad5[0x18]; /* Reserved 0x1E0-0x1F7 */ 299249130Sneel uint64_t rax; 300249130Sneel uint64_t star; 301249130Sneel uint64_t lstar; 302249130Sneel uint64_t cstar; 303249130Sneel uint64_t sfmask; 304249130Sneel uint64_t kernelgsbase; 305249130Sneel uint64_t sysenter_cs; 306249130Sneel uint64_t sysenter_esp; 307249130Sneel uint64_t sysenter_eip; 308249130Sneel uint64_t cr2; 309249130Sneel uint8_t pad6[0x20]; 310249130Sneel uint64_t g_pat; 311249130Sneel uint64_t dbgctl; 312249130Sneel uint64_t br_from; 313249130Sneel uint64_t br_to; 314259579Sgrehan uint64_t int_from; 315259579Sgrehan uint64_t int_to; 316249130Sneel uint8_t pad7[0x968]; /* Reserved upto end of VMCB */ 317249130Sneel} __attribute__ ((__packed__)); 318249130SneelCTASSERT(sizeof(struct vmcb_state) == 0xC00); 319249130Sneel 320249130Sneelstruct vmcb { 321249130Sneel struct vmcb_ctrl ctrl; 322249130Sneel struct vmcb_state state; 323249130Sneel} __attribute__ ((__packed__)); 324249130SneelCTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 325249130SneelCTASSERT(offsetof(struct vmcb, state) == 0x400); 326249130Sneel 327271939Sneelint vmcb_read(struct svm_softc *sc, int vcpu, int ident, uint64_t *retval); 328271939Sneelint vmcb_write(struct svm_softc *sc, int vcpu, int ident, uint64_t val); 329271939Sneelint vmcb_setdesc(void *arg, int vcpu, int ident, struct seg_desc *desc); 330271939Sneelint vmcb_getdesc(void *arg, int vcpu, int ident, struct seg_desc *desc); 331271939Sneelint vmcb_seg(struct vmcb *vmcb, int ident, struct vmcb_segment *seg); 332249353Sneel 333272916Sneel#endif /* _KERNEL */ 334249130Sneel#endif /* _VMCB_H_ */ 335