1121982Sjhb/*- 2121982Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121982Sjhb * All rights reserved. 4121982Sjhb * 5121982Sjhb * Redistribution and use in source and binary forms, with or without 6121982Sjhb * modification, are permitted provided that the following conditions 7121982Sjhb * are met: 8121982Sjhb * 1. Redistributions of source code must retain the above copyright 9121982Sjhb * notice, this list of conditions and the following disclaimer. 10121982Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11121982Sjhb * notice, this list of conditions and the following disclaimer in the 12121982Sjhb * documentation and/or other materials provided with the distribution. 13121982Sjhb * 14121982Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15121982Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16121982Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17121982Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18121982Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19121982Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20121982Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21121982Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22121982Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23121982Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24121982Sjhb * SUCH DAMAGE. 25121982Sjhb * 26121982Sjhb * $FreeBSD: releng/10.3/sys/amd64/include/intr_machdep.h 255726 2013-09-20 05:06:03Z gibbs $ 27121982Sjhb */ 28121982Sjhb 29121982Sjhb#ifndef __MACHINE_INTR_MACHDEP_H__ 30121982Sjhb#define __MACHINE_INTR_MACHDEP_H__ 31121982Sjhb 32121982Sjhb#ifdef _KERNEL 33121982Sjhb 34151979Sjhb/* 35151979Sjhb * The maximum number of I/O interrupts we allow. This number is rather 36151979Sjhb * arbitrary as it is just the maximum IRQ resource value. The interrupt 37151979Sjhb * source for a given IRQ maps that I/O interrupt to device interrupt 38151979Sjhb * source whether it be a pin on an interrupt controller or an MSI interrupt. 39151979Sjhb * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40151979Sjhb * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41151979Sjhb * vectors available for device interrupts. On many systems with I/O APICs, 42151979Sjhb * a lot of the IRQs are not used, so this number can be much larger than 43151979Sjhb * 191 and still be safe since only interrupt sources in actual use will 44151979Sjhb * allocate IDT vectors. 45151979Sjhb * 46164265Sjhb * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47255040Sgibbs * IRQ values from 256 to 767 are used by MSI. When running under the Xen 48255040Sgibbs * Hypervisor, IRQ values from 768 to 4863 are available for binding to 49255040Sgibbs * event channel events. We leave 255 unused to avoid confusion since 255 is 50255040Sgibbs * used in PCI to indicate an invalid IRQ. 51151979Sjhb */ 52187880Sjeff#define NUM_MSI_INTS 512 53164265Sjhb#define FIRST_MSI_INT 256 54255040Sgibbs#ifdef XENHVM 55255040Sgibbs#include <xen/xen-os.h> 56255040Sgibbs#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 57255040Sgibbs#define FIRST_EVTCHN_INT \ 58255040Sgibbs (FIRST_MSI_INT + NUM_MSI_INTS) 59255040Sgibbs#define LAST_EVTCHN_INT \ 60255040Sgibbs (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 61255040Sgibbs#else 62255040Sgibbs#define NUM_EVTCHN_INTS 0 63255040Sgibbs#endif 64255040Sgibbs#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 65121982Sjhb 66151979Sjhb/* 67164265Sjhb * Default base address for MSI messages on x86 platforms. 68164265Sjhb */ 69164265Sjhb#define MSI_INTEL_ADDR_BASE 0xfee00000 70164265Sjhb 71164265Sjhb/* 72151979Sjhb * - 1 ??? dummy counter. 73151979Sjhb * - 2 counters for each I/O interrupt. 74151979Sjhb * - 1 counter for each CPU for lapic timer. 75234207Savg * - 8 counters for each CPU for IPI counters for SMP. 76151979Sjhb */ 77151979Sjhb#ifdef SMP 78234207Savg#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) 79163212Sjhb#else 80151979Sjhb#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 81151979Sjhb#endif 82151979Sjhb 83121982Sjhb#ifndef LOCORE 84121982Sjhb 85121982Sjhbtypedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 86121982Sjhb 87121982Sjhb#define IDTVEC(name) __CONCAT(X,name) 88121982Sjhb 89121982Sjhbstruct intsrc; 90121982Sjhb 91121982Sjhb/* 92121982Sjhb * Methods that a PIC provides to mask/unmask a given interrupt source, 93121982Sjhb * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 94121982Sjhb * return the vector associated with this source. 95121982Sjhb */ 96121982Sjhbstruct pic { 97121982Sjhb void (*pic_enable_source)(struct intsrc *); 98133907Speter void (*pic_disable_source)(struct intsrc *, int); 99121982Sjhb void (*pic_eoi_source)(struct intsrc *); 100121982Sjhb void (*pic_enable_intr)(struct intsrc *); 101169391Sjhb void (*pic_disable_intr)(struct intsrc *); 102121982Sjhb int (*pic_vector)(struct intsrc *); 103121982Sjhb int (*pic_source_pending)(struct intsrc *); 104163219Sjhb void (*pic_suspend)(struct pic *); 105255726Sgibbs void (*pic_resume)(struct pic *, bool suspend_cancelled); 106129284Speter int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 107129284Speter enum intr_polarity); 108195249Sjhb int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 109246247Savg TAILQ_ENTRY(pic) pics; 110121982Sjhb}; 111121982Sjhb 112133907Speter/* Flags for pic_disable_source() */ 113133907Speterenum { 114133907Speter PIC_EOI, 115133907Speter PIC_NO_EOI, 116133907Speter}; 117133907Speter 118121982Sjhb/* 119121982Sjhb * An interrupt source. The upper-layer code uses the PIC methods to 120121982Sjhb * control a given source. The lower-layer PIC drivers can store additional 121121982Sjhb * private data in a given interrupt source such as an interrupt pin number 122121982Sjhb * or an I/O APIC pointer. 123121982Sjhb */ 124121982Sjhbstruct intsrc { 125121982Sjhb struct pic *is_pic; 126151658Sjhb struct intr_event *is_event; 127121982Sjhb u_long *is_count; 128121982Sjhb u_long *is_straycount; 129121982Sjhb u_int is_index; 130169391Sjhb u_int is_handlers; 131121982Sjhb}; 132121982Sjhb 133153241Sjhbstruct trapframe; 134121982Sjhb 135188065Sjkoshy/* 136188065Sjkoshy * The following data structure holds per-cpu data, and is placed just 137188065Sjkoshy * above the top of the space used for the NMI stack. 138188065Sjkoshy */ 139188065Sjkoshystruct nmi_pcpu { 140188065Sjkoshy register_t np_pcpu; 141188065Sjkoshy register_t __padding; /* pad to 16 bytes */ 142188065Sjkoshy}; 143188065Sjkoshy 144121982Sjhbextern struct mtx icu_lock; 145140555Speterextern int elcr_found; 146121982Sjhb 147163219Sjhb#ifndef DEV_ATPIC 148163219Sjhbvoid atpic_reset(void); 149163219Sjhb#endif 150129284Speter/* XXX: The elcr_* prototypes probably belong somewhere else. */ 151129284Speterint elcr_probe(void); 152129284Speterenum intr_trigger elcr_read_trigger(u_int irq); 153129284Spetervoid elcr_resume(void); 154129284Spetervoid elcr_write_trigger(u_int irq, enum intr_trigger trigger); 155241371Sattilio#ifdef SMP 156167273Sjhbvoid intr_add_cpu(u_int cpu); 157241371Sattilio#endif 158166901Spisoint intr_add_handler(const char *name, int vector, driver_filter_t filter, 159166901Spiso driver_intr_t handler, void *arg, enum intr_type flags, 160166901Spiso void **cookiep); 161234989Sattilio#ifdef SMP 162177181Sjhbint intr_bind(u_int vector, u_char cpu); 163234989Sattilio#endif 164129284Speterint intr_config_intr(int vector, enum intr_trigger trig, 165129284Speter enum intr_polarity pol); 166198134Sjhbint intr_describe(u_int vector, void *ih, const char *descr); 167153241Sjhbvoid intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 168194985Sjhbu_int intr_next_cpu(void); 169121982Sjhbstruct intsrc *intr_lookup_source(int vector); 170163219Sjhbint intr_register_pic(struct pic *pic); 171121982Sjhbint intr_register_source(struct intsrc *isrc); 172121982Sjhbint intr_remove_handler(void *cookie); 173255726Sgibbsvoid intr_resume(bool suspend_cancelled); 174121982Sjhbvoid intr_suspend(void); 175140555Spetervoid intrcnt_add(const char *name, u_long **countp); 176169391Sjhbvoid nexus_add_irq(u_long irq); 177169391Sjhbint msi_alloc(device_t dev, int count, int maxcount, int *irqs); 178165127Sjhbvoid msi_init(void); 179169221Sjhbint msi_map(int irq, uint64_t *addr, uint32_t *data); 180164265Sjhbint msi_release(int *irqs, int count); 181169391Sjhbint msix_alloc(device_t dev, int *irq); 182164265Sjhbint msix_release(int irq); 183121982Sjhb 184121982Sjhb#endif /* !LOCORE */ 185121982Sjhb#endif /* _KERNEL */ 186121982Sjhb#endif /* !__MACHINE_INTR_MACHDEP_H__ */ 187