167117Sdfr.file "__umoddi3.s" 267117Sdfr 367117Sdfr// 467117Sdfr// Copyright (c) 2000, Intel Corporation 567117Sdfr// All rights reserved. 667117Sdfr// 767117Sdfr// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 867117Sdfr// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 967117Sdfr// Intel Corporation. 1067117Sdfr// 1167117Sdfr// WARRANTY DISCLAIMER 1267117Sdfr// 1367117Sdfr// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1467117Sdfr// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1567117Sdfr// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1667117Sdfr// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 1767117Sdfr// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 1867117Sdfr// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1967117Sdfr// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2067117Sdfr// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 2167117Sdfr// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 2267117Sdfr// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 2367117Sdfr// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2467117Sdfr// 2567117Sdfr// Intel Corporation is the author of this code, and requests that all 2667117Sdfr// problem reports or change requests be submitted to it directly at 2767117Sdfr// http://developer.intel.com/opensource. 2867117Sdfr// 2967117Sdfr 30111777Sobrien#include <machine/asm.h> 31111777Sobrien__FBSDID("$FreeBSD: releng/10.3/lib/libc/ia64/gen/__umoddi3.S 111777 2003-03-03 01:09:46Z obrien $"); 32111777Sobrien 3367117Sdfr.section .text 3467117Sdfr 3567117Sdfr // 64-bit unsigned integer remainder 3667117Sdfr 3767117Sdfr.proc __umoddi3# 3867117Sdfr.align 32 3967117Sdfr.global __umoddi3# 4067117Sdfr.align 32 4167117Sdfr 4267117Sdfr__umoddi3: 4367117Sdfr 4467117Sdfr{ .mii 4567117Sdfr alloc r31=ar.pfs,3,0,0,0 4667117Sdfr nop.i 0 4767117Sdfr nop.i 0 4867117Sdfr} { .mmb 4967117Sdfr 5067117Sdfr // 64-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE 5167117Sdfr 5267117Sdfr // general register used: 5367117Sdfr // r32 - 64-bit unsigned integer dividend 5467117Sdfr // r33 - 64-bit unsigned integer divisor 5567117Sdfr // r8 - 64-bit unsigned integer result 5667117Sdfr // floating-point registers used: f6, f7, f8, f9, f10, f11, f12 5767117Sdfr // predicate registers used: p6 5867117Sdfr 59108533Sschweikh setf.sig f12=r32 // holds an in integer form 6067117Sdfr setf.sig f7=r33 6167117Sdfr nop.b 0;; 6267117Sdfr} { .mfi 6367117Sdfr // get 2's complement of b 6467117Sdfr sub r33=r0,r33 6567117Sdfr fcvt.xuf.s1 f6=f12 6667117Sdfr nop.i 0 6767117Sdfr} { .mfi 6867117Sdfr nop.m 0 6967117Sdfr fcvt.xuf.s1 f7=f7 7067117Sdfr nop.i 0;; 7167117Sdfr} { .mfi 7267117Sdfr nop.m 0 7367117Sdfr // Step (1) 7467117Sdfr // y0 = 1 / b in f8 7567117Sdfr frcpa.s1 f8,p6=f6,f7 7667117Sdfr nop.i 0;; 7767117Sdfr} { .mfi 7867117Sdfr nop.m 0 7967117Sdfr // Step (2) 8067117Sdfr // q0 = a * y0 in f10 8167117Sdfr (p6) fma.s1 f10=f6,f8,f0 8267117Sdfr nop.i 0 8367117Sdfr} { .mfi 8467117Sdfr nop.m 0 8567117Sdfr // Step (3) 8667117Sdfr // e0 = 1 - b * y0 in f9 8767117Sdfr (p6) fnma.s1 f9=f7,f8,f1 8867117Sdfr nop.i 0;; 8967117Sdfr} { .mfi 9067117Sdfr nop.m 0 9167117Sdfr // Step (4) 9267117Sdfr // q1 = q0 + e0 * q0 in f10 9367117Sdfr (p6) fma.s1 f10=f9,f10,f10 9467117Sdfr nop.i 0 9567117Sdfr} { .mfi 9667117Sdfr nop.m 0 9767117Sdfr // Step (5) 9867117Sdfr // e1 = e0 * e0 in f11 9967117Sdfr (p6) fma.s1 f11=f9,f9,f0 10067117Sdfr nop.i 0;; 10167117Sdfr} { .mfi 10267117Sdfr nop.m 0 10367117Sdfr // Step (6) 10467117Sdfr // y1 = y0 + e0 * y0 in f8 10567117Sdfr (p6) fma.s1 f8=f9,f8,f8 10667117Sdfr nop.i 0;; 10767117Sdfr} { .mfi 10867117Sdfr nop.m 0 10967117Sdfr // Step (7) 11067117Sdfr // q2 = q1 + e1 * q1 in f9 11167117Sdfr (p6) fma.s1 f9=f11,f10,f10 11267117Sdfr nop.i 0;; 11367117Sdfr} { .mfi 11467117Sdfr nop.m 0 11567117Sdfr // Step (8) 11667117Sdfr // y2 = y1 + e1 * y1 in f8 11767117Sdfr (p6) fma.s1 f8=f11,f8,f8 11867117Sdfr nop.i 0;; 11967117Sdfr} { .mfi 12067117Sdfr nop.m 0 12167117Sdfr // Step (9) 12267117Sdfr // r2 = a - b * q2 in f10 12367117Sdfr (p6) fnma.s1 f10=f7,f9,f6 12467117Sdfr nop.i 0;; 12567117Sdfr} { .mfi 12667117Sdfr // f7=-b 12767117Sdfr setf.sig f7=r33 12867117Sdfr // Step (10) 12967117Sdfr // q3 = q2 + r2 * y2 in f8 13067117Sdfr (p6) fma.s1 f8=f10,f8,f9 13167117Sdfr nop.i 0;; 13267117Sdfr} { .mfi 13367117Sdfr nop.m 0 13467117Sdfr // (11) q = trunc(q3) 13567117Sdfr fcvt.fxu.trunc.s1 f8=f8 13667117Sdfr nop.i 0;; 13767117Sdfr} { .mfi 13867117Sdfr nop.m 0 13967117Sdfr // (12) r = a + (-b) * q 14067117Sdfr xma.l f8=f8,f7,f12 14167117Sdfr nop.i 0;; 14267117Sdfr} { .mib 14367117Sdfr getf.sig r8=f8 14467117Sdfr nop.i 0 14567117Sdfr nop.b 0 14667117Sdfr} 14767117Sdfr 14867117Sdfr // 64-BIT UNSIGNED INTEGER REMAINDER ENDS HERE 14967117Sdfr 15067117Sdfr{ .mib 15167117Sdfr nop.m 0 15267117Sdfr nop.i 0 15367117Sdfr br.ret.sptk b0;; 15467117Sdfr} 15567117Sdfr 15667117Sdfr.endp __umoddi3 157