CodeEmitterGen.cpp revision 243830 
1//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// CodeEmitterGen uses the descriptions of instructions and their fields to
11// construct an automated code emitter: a function that, given a MachineInstr,
12// returns the (currently, 32-bit unsigned) value of the instruction.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CodeGenTarget.h"
17#include "llvm/TableGen/Record.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/TableGen/TableGenBackend.h"
22#include <map>
23#include <string>
24#include <vector>
25using namespace llvm;
26
27// FIXME: Somewhat hackish to use a command line option for this. There should
28// be a CodeEmitter class in the Target.td that controls this sort of thing
29// instead.
30static cl::opt<bool>
31MCEmitter("mc-emitter",
32          cl::desc("Generate CodeEmitter for use with the MC library."),
33          cl::init(false));
34
35namespace {
36
37class CodeEmitterGen {
38  RecordKeeper &Records;
39public:
40  CodeEmitterGen(RecordKeeper &R) : Records(R) {}
41
42  void run(raw_ostream &o);
43private:
44  void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
45  void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
46  void reverseBits(std::vector<Record*> &Insts);
47  int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
48  std::string getInstructionCase(Record *R, CodeGenTarget &Target);
49  void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
50                               const std::string &VarName,
51                               unsigned &NumberedOp,
52                               std::string &Case, CodeGenTarget &Target);
53
54};
55
56void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
57  for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
58       I != E; ++I) {
59    Record *R = *I;
60    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
61        R->getValueAsBit("isPseudo"))
62      continue;
63
64    BitsInit *BI = R->getValueAsBitsInit("Inst");
65
66    unsigned numBits = BI->getNumBits();
67
68    SmallVector<Init *, 16> NewBits(numBits);
69
70    for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
71      unsigned bitSwapIdx = numBits - bit - 1;
72      Init *OrigBit = BI->getBit(bit);
73      Init *BitSwap = BI->getBit(bitSwapIdx);
74      NewBits[bit]        = BitSwap;
75      NewBits[bitSwapIdx] = OrigBit;
76    }
77    if (numBits % 2) {
78      unsigned middle = (numBits + 1) / 2;
79      NewBits[middle] = BI->getBit(middle);
80    }
81
82    BitsInit *NewBI = BitsInit::get(NewBits);
83
84    // Update the bits in reversed order so that emitInstrOpBits will get the
85    // correct endianness.
86    R->getValue("Inst")->setValue(NewBI);
87  }
88}
89
90// If the VarBitInit at position 'bit' matches the specified variable then
91// return the variable bit position.  Otherwise return -1.
92int CodeEmitterGen::getVariableBit(const std::string &VarName,
93                                   BitsInit *BI, int bit) {
94  if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
95    if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
96      if (VI->getName() == VarName)
97        return VBI->getBitNum();
98  } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
99    if (VI->getName() == VarName)
100      return 0;
101  }
102
103  return -1;
104}
105
106void CodeEmitterGen::
107AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
108                        unsigned &NumberedOp,
109                        std::string &Case, CodeGenTarget &Target) {
110  CodeGenInstruction &CGI = Target.getInstruction(R);
111
112  // Determine if VarName actually contributes to the Inst encoding.
113  int bit = BI->getNumBits()-1;
114
115  // Scan for a bit that this contributed to.
116  for (; bit >= 0; ) {
117    if (getVariableBit(VarName, BI, bit) != -1)
118      break;
119
120    --bit;
121  }
122
123  // If we found no bits, ignore this value, otherwise emit the call to get the
124  // operand encoding.
125  if (bit < 0) return;
126
127  // If the operand matches by name, reference according to that
128  // operand number. Non-matching operands are assumed to be in
129  // order.
130  unsigned OpIdx;
131  if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
132    // Get the machine operand number for the indicated operand.
133    OpIdx = CGI.Operands[OpIdx].MIOperandNo;
134    assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
135           "Explicitly used operand also marked as not emitted!");
136  } else {
137    unsigned NumberOps = CGI.Operands.size();
138    /// If this operand is not supposed to be emitted by the
139    /// generated emitter, skip it.
140    while (NumberedOp < NumberOps &&
141           CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
142      ++NumberedOp;
143
144    OpIdx = NumberedOp++;
145  }
146
147  std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
148  std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
149
150  // If the source operand has a custom encoder, use it. This will
151  // get the encoding for all of the suboperands.
152  if (!EncoderMethodName.empty()) {
153    // A custom encoder has all of the information for the
154    // sub-operands, if there are more than one, so only
155    // query the encoder once per source operand.
156    if (SO.second == 0) {
157      Case += "      // op: " + VarName + "\n" +
158              "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
159      if (MCEmitter)
160        Case += ", Fixups";
161      Case += ");\n";
162    }
163  } else {
164    Case += "      // op: " + VarName + "\n" +
165      "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
166    if (MCEmitter)
167      Case += ", Fixups";
168    Case += ");\n";
169  }
170
171  for (; bit >= 0; ) {
172    int varBit = getVariableBit(VarName, BI, bit);
173
174    // If this bit isn't from a variable, skip it.
175    if (varBit == -1) {
176      --bit;
177      continue;
178    }
179
180    // Figure out the consecutive range of bits covered by this operand, in
181    // order to generate better encoding code.
182    int beginInstBit = bit;
183    int beginVarBit = varBit;
184    int N = 1;
185    for (--bit; bit >= 0;) {
186      varBit = getVariableBit(VarName, BI, bit);
187      if (varBit == -1 || varBit != (beginVarBit - N)) break;
188      ++N;
189      --bit;
190    }
191
192    uint64_t opMask = ~(uint64_t)0 >> (64-N);
193    int opShift = beginVarBit - N + 1;
194    opMask <<= opShift;
195    opShift = beginInstBit - beginVarBit;
196
197    if (opShift > 0) {
198      Case += "      Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
199              itostr(opShift) + ";\n";
200    } else if (opShift < 0) {
201      Case += "      Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
202              itostr(-opShift) + ";\n";
203    } else {
204      Case += "      Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
205    }
206  }
207}
208
209
210std::string CodeEmitterGen::getInstructionCase(Record *R,
211                                               CodeGenTarget &Target) {
212  std::string Case;
213
214  BitsInit *BI = R->getValueAsBitsInit("Inst");
215  const std::vector<RecordVal> &Vals = R->getValues();
216  unsigned NumberedOp = 0;
217
218  // Loop over all of the fields in the instruction, determining which are the
219  // operands to the instruction.
220  for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
221    // Ignore fixed fields in the record, we're looking for values like:
222    //    bits<5> RST = { ?, ?, ?, ?, ? };
223    if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
224      continue;
225
226    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
227  }
228
229  std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
230  if (!PostEmitter.empty())
231    Case += "      Value = " + PostEmitter + "(MI, Value);\n";
232
233  return Case;
234}
235
236void CodeEmitterGen::run(raw_ostream &o) {
237  CodeGenTarget Target(Records);
238  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
239
240  // For little-endian instruction bit encodings, reverse the bit order
241  if (Target.isLittleEndianEncoding()) reverseBits(Insts);
242
243
244  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
245    Target.getInstructionsByEnumValue();
246
247  // Emit function declaration
248  o << "uint64_t " << Target.getName();
249  if (MCEmitter)
250    o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
251      << "    SmallVectorImpl<MCFixup> &Fixups) const {\n";
252  else
253    o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
254
255  // Emit instruction base values
256  o << "  static const uint64_t InstBits[] = {\n";
257  for (std::vector<const CodeGenInstruction*>::const_iterator
258          IN = NumberedInstructions.begin(),
259          EN = NumberedInstructions.end();
260       IN != EN; ++IN) {
261    const CodeGenInstruction *CGI = *IN;
262    Record *R = CGI->TheDef;
263
264    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
265        R->getValueAsBit("isPseudo")) {
266      o << "    UINT64_C(0),\n";
267      continue;
268    }
269
270    BitsInit *BI = R->getValueAsBitsInit("Inst");
271
272    // Start by filling in fixed values.
273    uint64_t Value = 0;
274    for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
275      if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
276        Value |= (uint64_t)B->getValue() << (e-i-1);
277    }
278    o << "    UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
279  }
280  o << "    UINT64_C(0)\n  };\n";
281
282  // Map to accumulate all the cases.
283  std::map<std::string, std::vector<std::string> > CaseMap;
284
285  // Construct all cases statement for each opcode
286  for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
287        IC != EC; ++IC) {
288    Record *R = *IC;
289    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
290        R->getValueAsBit("isPseudo"))
291      continue;
292    const std::string &InstName = R->getValueAsString("Namespace") + "::"
293      + R->getName();
294    std::string Case = getInstructionCase(R, Target);
295
296    CaseMap[Case].push_back(InstName);
297  }
298
299  // Emit initial function code
300  o << "  const unsigned opcode = MI.getOpcode();\n"
301    << "  uint64_t Value = InstBits[opcode];\n"
302    << "  uint64_t op = 0;\n"
303    << "  (void)op;  // suppress warning\n"
304    << "  switch (opcode) {\n";
305
306  // Emit each case statement
307  std::map<std::string, std::vector<std::string> >::iterator IE, EE;
308  for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
309    const std::string &Case = IE->first;
310    std::vector<std::string> &InstList = IE->second;
311
312    for (int i = 0, N = InstList.size(); i < N; i++) {
313      if (i) o << "\n";
314      o << "    case " << InstList[i]  << ":";
315    }
316    o << " {\n";
317    o << Case;
318    o << "      break;\n"
319      << "    }\n";
320  }
321
322  // Default case: unhandled opcode
323  o << "  default:\n"
324    << "    std::string msg;\n"
325    << "    raw_string_ostream Msg(msg);\n"
326    << "    Msg << \"Not supported instr: \" << MI;\n"
327    << "    report_fatal_error(Msg.str());\n"
328    << "  }\n"
329    << "  return Value;\n"
330    << "}\n\n";
331}
332
333} // End anonymous namespace
334
335namespace llvm {
336
337void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
338  emitSourceFileHeader("Machine Code Emitter", OS);
339  CodeEmitterGen(RK).run(OS);
340}
341
342} // End llvm namespace
343