1254721Semaste//===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 2254721Semaste// 3254721Semaste// The LLVM Compiler Infrastructure 4254721Semaste// 5254721Semaste// This file is distributed under the University of Illinois Open Source 6254721Semaste// License. See LICENSE.TXT for details. 7254721Semaste// 8254721Semaste//===----------------------------------------------------------------------===// 9254721Semaste 10254721Semaste#if defined(__APPLE__) 11254721Semaste 12254721Semaste#include "RegisterContextDarwin_arm.h" 13254721Semaste 14254721Semaste// C Includes 15254721Semaste#include <mach/mach_types.h> 16254721Semaste#include <mach/thread_act.h> 17254721Semaste 18254721Semaste// C++ Includes 19254721Semaste// Other libraries and framework includes 20254721Semaste#include "lldb/Core/DataBufferHeap.h" 21254721Semaste#include "lldb/Core/DataExtractor.h" 22254721Semaste#include "lldb/Core/Log.h" 23254721Semaste#include "lldb/Core/RegisterValue.h" 24254721Semaste#include "lldb/Core/Scalar.h" 25254721Semaste#include "lldb/Host/Endian.h" 26254721Semaste#include "llvm/Support/Compiler.h" 27254721Semaste 28254721Semaste#include "Plugins/Process/Utility/InstructionUtils.h" 29254721Semaste 30254721Semaste// Support building against older versions of LLVM, this macro was added 31254721Semaste// recently. 32254721Semaste#ifndef LLVM_EXTENSION 33254721Semaste#define LLVM_EXTENSION 34254721Semaste#endif 35254721Semaste 36254721Semaste// Project includes 37254721Semaste#include "ARM_GCC_Registers.h" 38254721Semaste#include "ARM_DWARF_Registers.h" 39254721Semaste 40254721Semasteusing namespace lldb; 41254721Semasteusing namespace lldb_private; 42254721Semaste 43254721Semasteenum 44254721Semaste{ 45254721Semaste gpr_r0 = 0, 46254721Semaste gpr_r1, 47254721Semaste gpr_r2, 48254721Semaste gpr_r3, 49254721Semaste gpr_r4, 50254721Semaste gpr_r5, 51254721Semaste gpr_r6, 52254721Semaste gpr_r7, 53254721Semaste gpr_r8, 54254721Semaste gpr_r9, 55254721Semaste gpr_r10, 56254721Semaste gpr_r11, 57254721Semaste gpr_r12, 58254721Semaste gpr_r13, gpr_sp = gpr_r13, 59254721Semaste gpr_r14, gpr_lr = gpr_r14, 60254721Semaste gpr_r15, gpr_pc = gpr_r15, 61254721Semaste gpr_cpsr, 62254721Semaste 63254721Semaste fpu_s0, 64254721Semaste fpu_s1, 65254721Semaste fpu_s2, 66254721Semaste fpu_s3, 67254721Semaste fpu_s4, 68254721Semaste fpu_s5, 69254721Semaste fpu_s6, 70254721Semaste fpu_s7, 71254721Semaste fpu_s8, 72254721Semaste fpu_s9, 73254721Semaste fpu_s10, 74254721Semaste fpu_s11, 75254721Semaste fpu_s12, 76254721Semaste fpu_s13, 77254721Semaste fpu_s14, 78254721Semaste fpu_s15, 79254721Semaste fpu_s16, 80254721Semaste fpu_s17, 81254721Semaste fpu_s18, 82254721Semaste fpu_s19, 83254721Semaste fpu_s20, 84254721Semaste fpu_s21, 85254721Semaste fpu_s22, 86254721Semaste fpu_s23, 87254721Semaste fpu_s24, 88254721Semaste fpu_s25, 89254721Semaste fpu_s26, 90254721Semaste fpu_s27, 91254721Semaste fpu_s28, 92254721Semaste fpu_s29, 93254721Semaste fpu_s30, 94254721Semaste fpu_s31, 95254721Semaste fpu_fpscr, 96254721Semaste 97254721Semaste exc_exception, 98254721Semaste exc_fsr, 99254721Semaste exc_far, 100254721Semaste 101254721Semaste dbg_bvr0, 102254721Semaste dbg_bvr1, 103254721Semaste dbg_bvr2, 104254721Semaste dbg_bvr3, 105254721Semaste dbg_bvr4, 106254721Semaste dbg_bvr5, 107254721Semaste dbg_bvr6, 108254721Semaste dbg_bvr7, 109254721Semaste dbg_bvr8, 110254721Semaste dbg_bvr9, 111254721Semaste dbg_bvr10, 112254721Semaste dbg_bvr11, 113254721Semaste dbg_bvr12, 114254721Semaste dbg_bvr13, 115254721Semaste dbg_bvr14, 116254721Semaste dbg_bvr15, 117254721Semaste 118254721Semaste dbg_bcr0, 119254721Semaste dbg_bcr1, 120254721Semaste dbg_bcr2, 121254721Semaste dbg_bcr3, 122254721Semaste dbg_bcr4, 123254721Semaste dbg_bcr5, 124254721Semaste dbg_bcr6, 125254721Semaste dbg_bcr7, 126254721Semaste dbg_bcr8, 127254721Semaste dbg_bcr9, 128254721Semaste dbg_bcr10, 129254721Semaste dbg_bcr11, 130254721Semaste dbg_bcr12, 131254721Semaste dbg_bcr13, 132254721Semaste dbg_bcr14, 133254721Semaste dbg_bcr15, 134254721Semaste 135254721Semaste dbg_wvr0, 136254721Semaste dbg_wvr1, 137254721Semaste dbg_wvr2, 138254721Semaste dbg_wvr3, 139254721Semaste dbg_wvr4, 140254721Semaste dbg_wvr5, 141254721Semaste dbg_wvr6, 142254721Semaste dbg_wvr7, 143254721Semaste dbg_wvr8, 144254721Semaste dbg_wvr9, 145254721Semaste dbg_wvr10, 146254721Semaste dbg_wvr11, 147254721Semaste dbg_wvr12, 148254721Semaste dbg_wvr13, 149254721Semaste dbg_wvr14, 150254721Semaste dbg_wvr15, 151254721Semaste 152254721Semaste dbg_wcr0, 153254721Semaste dbg_wcr1, 154254721Semaste dbg_wcr2, 155254721Semaste dbg_wcr3, 156254721Semaste dbg_wcr4, 157254721Semaste dbg_wcr5, 158254721Semaste dbg_wcr6, 159254721Semaste dbg_wcr7, 160254721Semaste dbg_wcr8, 161254721Semaste dbg_wcr9, 162254721Semaste dbg_wcr10, 163254721Semaste dbg_wcr11, 164254721Semaste dbg_wcr12, 165254721Semaste dbg_wcr13, 166254721Semaste dbg_wcr14, 167254721Semaste dbg_wcr15, 168254721Semaste 169254721Semaste k_num_registers 170254721Semaste}; 171254721Semaste 172254721Semaste 173254721SemasteRegisterContextDarwin_arm::RegisterContextDarwin_arm(Thread &thread, uint32_t concrete_frame_idx) : 174254721Semaste RegisterContext(thread, concrete_frame_idx), 175254721Semaste gpr(), 176254721Semaste fpu(), 177254721Semaste exc() 178254721Semaste{ 179254721Semaste uint32_t i; 180254721Semaste for (i=0; i<kNumErrors; i++) 181254721Semaste { 182254721Semaste gpr_errs[i] = -1; 183254721Semaste fpu_errs[i] = -1; 184254721Semaste exc_errs[i] = -1; 185254721Semaste } 186254721Semaste} 187254721Semaste 188254721SemasteRegisterContextDarwin_arm::~RegisterContextDarwin_arm() 189254721Semaste{ 190254721Semaste} 191254721Semaste 192254721Semaste 193254721Semaste#define GPR_OFFSET(idx) ((idx) * 4) 194254721Semaste#define FPU_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR)) 195254721Semaste#define EXC_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU)) 196254721Semaste#define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextDarwin_arm::DBG, reg) + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC))) 197254721Semaste 198254721Semaste#define DEFINE_DBG(reg, i) #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, dbg_##reg##i }, NULL, NULL 199254721Semaste#define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC)) 200254721Semaste 201254721Semastestatic RegisterInfo g_register_infos[] = { 202254721Semaste// General purpose registers 203254721Semaste// NAME ALT SZ OFFSET ENCODING FORMAT COMPILER DWARF GENERIC GDB LLDB NATIVE VALUE REGS INVALIDATE REGS 204254721Semaste// ====== ======= == ============= ============= ============ =============== =============== ========================= ===================== ============= ========== =============== 205254721Semaste{ "r0", NULL, 4, GPR_OFFSET(0), eEncodingUint, eFormatHex, { gcc_r0, dwarf_r0, LLDB_INVALID_REGNUM, gdb_arm_r0, gpr_r0 }, NULL, NULL}, 206254721Semaste{ "r1", NULL, 4, GPR_OFFSET(1), eEncodingUint, eFormatHex, { gcc_r1, dwarf_r1, LLDB_INVALID_REGNUM, gdb_arm_r1, gpr_r1 }, NULL, NULL}, 207254721Semaste{ "r2", NULL, 4, GPR_OFFSET(2), eEncodingUint, eFormatHex, { gcc_r2, dwarf_r2, LLDB_INVALID_REGNUM, gdb_arm_r2, gpr_r2 }, NULL, NULL}, 208254721Semaste{ "r3", NULL, 4, GPR_OFFSET(3), eEncodingUint, eFormatHex, { gcc_r3, dwarf_r3, LLDB_INVALID_REGNUM, gdb_arm_r3, gpr_r3 }, NULL, NULL}, 209254721Semaste{ "r4", NULL, 4, GPR_OFFSET(4), eEncodingUint, eFormatHex, { gcc_r4, dwarf_r4, LLDB_INVALID_REGNUM, gdb_arm_r4, gpr_r4 }, NULL, NULL}, 210254721Semaste{ "r5", NULL, 4, GPR_OFFSET(5), eEncodingUint, eFormatHex, { gcc_r5, dwarf_r5, LLDB_INVALID_REGNUM, gdb_arm_r5, gpr_r5 }, NULL, NULL}, 211254721Semaste{ "r6", NULL, 4, GPR_OFFSET(6), eEncodingUint, eFormatHex, { gcc_r6, dwarf_r6, LLDB_INVALID_REGNUM, gdb_arm_r6, gpr_r6 }, NULL, NULL}, 212254721Semaste{ "r7", NULL, 4, GPR_OFFSET(7), eEncodingUint, eFormatHex, { gcc_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, gdb_arm_r7, gpr_r7 }, NULL, NULL}, 213254721Semaste{ "r8", NULL, 4, GPR_OFFSET(8), eEncodingUint, eFormatHex, { gcc_r8, dwarf_r8, LLDB_INVALID_REGNUM, gdb_arm_r8, gpr_r8 }, NULL, NULL}, 214254721Semaste{ "r9", NULL, 4, GPR_OFFSET(9), eEncodingUint, eFormatHex, { gcc_r9, dwarf_r9, LLDB_INVALID_REGNUM, gdb_arm_r9, gpr_r9 }, NULL, NULL}, 215254721Semaste{ "r10", NULL, 4, GPR_OFFSET(10), eEncodingUint, eFormatHex, { gcc_r10, dwarf_r10, LLDB_INVALID_REGNUM, gdb_arm_r10, gpr_r10 }, NULL, NULL}, 216254721Semaste{ "r11", NULL, 4, GPR_OFFSET(11), eEncodingUint, eFormatHex, { gcc_r11, dwarf_r11, LLDB_INVALID_REGNUM, gdb_arm_r11, gpr_r11 }, NULL, NULL}, 217254721Semaste{ "r12", NULL, 4, GPR_OFFSET(12), eEncodingUint, eFormatHex, { gcc_r12, dwarf_r12, LLDB_INVALID_REGNUM, gdb_arm_r12, gpr_r12 }, NULL, NULL}, 218254721Semaste{ "sp", "r13", 4, GPR_OFFSET(13), eEncodingUint, eFormatHex, { gcc_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, gdb_arm_sp, gpr_sp }, NULL, NULL}, 219254721Semaste{ "lr", "r14", 4, GPR_OFFSET(14), eEncodingUint, eFormatHex, { gcc_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, gdb_arm_lr, gpr_lr }, NULL, NULL}, 220254721Semaste{ "pc", "r15", 4, GPR_OFFSET(15), eEncodingUint, eFormatHex, { gcc_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, gdb_arm_pc, gpr_pc }, NULL, NULL}, 221254721Semaste{ "cpsr", "psr", 4, GPR_OFFSET(16), eEncodingUint, eFormatHex, { gcc_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, gdb_arm_cpsr, gpr_cpsr }, NULL, NULL}, 222254721Semaste 223254721Semaste{ "s0", NULL, 4, FPU_OFFSET(0), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, gdb_arm_s0, fpu_s0 }, NULL, NULL}, 224254721Semaste{ "s1", NULL, 4, FPU_OFFSET(1), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, gdb_arm_s1, fpu_s1 }, NULL, NULL}, 225254721Semaste{ "s2", NULL, 4, FPU_OFFSET(2), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, gdb_arm_s2, fpu_s2 }, NULL, NULL}, 226254721Semaste{ "s3", NULL, 4, FPU_OFFSET(3), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, gdb_arm_s3, fpu_s3 }, NULL, NULL}, 227254721Semaste{ "s4", NULL, 4, FPU_OFFSET(4), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, gdb_arm_s4, fpu_s4 }, NULL, NULL}, 228254721Semaste{ "s5", NULL, 4, FPU_OFFSET(5), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, gdb_arm_s5, fpu_s5 }, NULL, NULL}, 229254721Semaste{ "s6", NULL, 4, FPU_OFFSET(6), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, gdb_arm_s6, fpu_s6 }, NULL, NULL}, 230254721Semaste{ "s7", NULL, 4, FPU_OFFSET(7), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, gdb_arm_s7, fpu_s7 }, NULL, NULL}, 231254721Semaste{ "s8", NULL, 4, FPU_OFFSET(8), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, gdb_arm_s8, fpu_s8 }, NULL, NULL}, 232254721Semaste{ "s9", NULL, 4, FPU_OFFSET(9), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, gdb_arm_s9, fpu_s9 }, NULL, NULL}, 233254721Semaste{ "s10", NULL, 4, FPU_OFFSET(10), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, gdb_arm_s10, fpu_s10 }, NULL, NULL}, 234254721Semaste{ "s11", NULL, 4, FPU_OFFSET(11), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, gdb_arm_s11, fpu_s11 }, NULL, NULL}, 235254721Semaste{ "s12", NULL, 4, FPU_OFFSET(12), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, gdb_arm_s12, fpu_s12 }, NULL, NULL}, 236254721Semaste{ "s13", NULL, 4, FPU_OFFSET(13), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, gdb_arm_s13, fpu_s13 }, NULL, NULL}, 237254721Semaste{ "s14", NULL, 4, FPU_OFFSET(14), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, gdb_arm_s14, fpu_s14 }, NULL, NULL}, 238254721Semaste{ "s15", NULL, 4, FPU_OFFSET(15), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, gdb_arm_s15, fpu_s15 }, NULL, NULL}, 239254721Semaste{ "s16", NULL, 4, FPU_OFFSET(16), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, gdb_arm_s16, fpu_s16 }, NULL, NULL}, 240254721Semaste{ "s17", NULL, 4, FPU_OFFSET(17), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, gdb_arm_s17, fpu_s17 }, NULL, NULL}, 241254721Semaste{ "s18", NULL, 4, FPU_OFFSET(18), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, gdb_arm_s18, fpu_s18 }, NULL, NULL}, 242254721Semaste{ "s19", NULL, 4, FPU_OFFSET(19), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, gdb_arm_s19, fpu_s19 }, NULL, NULL}, 243254721Semaste{ "s20", NULL, 4, FPU_OFFSET(20), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, gdb_arm_s20, fpu_s20 }, NULL, NULL}, 244254721Semaste{ "s21", NULL, 4, FPU_OFFSET(21), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, gdb_arm_s21, fpu_s21 }, NULL, NULL}, 245254721Semaste{ "s22", NULL, 4, FPU_OFFSET(22), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, gdb_arm_s22, fpu_s22 }, NULL, NULL}, 246254721Semaste{ "s23", NULL, 4, FPU_OFFSET(23), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, gdb_arm_s23, fpu_s23 }, NULL, NULL}, 247254721Semaste{ "s24", NULL, 4, FPU_OFFSET(24), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, gdb_arm_s24, fpu_s24 }, NULL, NULL}, 248254721Semaste{ "s25", NULL, 4, FPU_OFFSET(25), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, gdb_arm_s25, fpu_s25 }, NULL, NULL}, 249254721Semaste{ "s26", NULL, 4, FPU_OFFSET(26), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, gdb_arm_s26, fpu_s26 }, NULL, NULL}, 250254721Semaste{ "s27", NULL, 4, FPU_OFFSET(27), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, gdb_arm_s27, fpu_s27 }, NULL, NULL}, 251254721Semaste{ "s28", NULL, 4, FPU_OFFSET(28), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, gdb_arm_s28, fpu_s28 }, NULL, NULL}, 252254721Semaste{ "s29", NULL, 4, FPU_OFFSET(29), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, gdb_arm_s29, fpu_s29 }, NULL, NULL}, 253254721Semaste{ "s30", NULL, 4, FPU_OFFSET(30), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, gdb_arm_s30, fpu_s30 }, NULL, NULL}, 254254721Semaste{ "s31", NULL, 4, FPU_OFFSET(31), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, gdb_arm_s31, fpu_s31 }, NULL, NULL}, 255254721Semaste{ "fpscr", NULL, 4, FPU_OFFSET(32), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, gdb_arm_fpscr, fpu_fpscr }, NULL, NULL}, 256254721Semaste 257254721Semaste{ "exception",NULL, 4, EXC_OFFSET(0), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception }, NULL, NULL}, 258254721Semaste{ "fsr", NULL, 4, EXC_OFFSET(1), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_fsr }, NULL, NULL}, 259254721Semaste{ "far", NULL, 4, EXC_OFFSET(2), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far }, NULL, NULL}, 260254721Semaste 261254721Semaste{ DEFINE_DBG (bvr, 0) }, 262254721Semaste{ DEFINE_DBG (bvr, 1) }, 263254721Semaste{ DEFINE_DBG (bvr, 2) }, 264254721Semaste{ DEFINE_DBG (bvr, 3) }, 265254721Semaste{ DEFINE_DBG (bvr, 4) }, 266254721Semaste{ DEFINE_DBG (bvr, 5) }, 267254721Semaste{ DEFINE_DBG (bvr, 6) }, 268254721Semaste{ DEFINE_DBG (bvr, 7) }, 269254721Semaste{ DEFINE_DBG (bvr, 8) }, 270254721Semaste{ DEFINE_DBG (bvr, 9) }, 271254721Semaste{ DEFINE_DBG (bvr, 10) }, 272254721Semaste{ DEFINE_DBG (bvr, 11) }, 273254721Semaste{ DEFINE_DBG (bvr, 12) }, 274254721Semaste{ DEFINE_DBG (bvr, 13) }, 275254721Semaste{ DEFINE_DBG (bvr, 14) }, 276254721Semaste{ DEFINE_DBG (bvr, 15) }, 277254721Semaste 278254721Semaste{ DEFINE_DBG (bcr, 0) }, 279254721Semaste{ DEFINE_DBG (bcr, 1) }, 280254721Semaste{ DEFINE_DBG (bcr, 2) }, 281254721Semaste{ DEFINE_DBG (bcr, 3) }, 282254721Semaste{ DEFINE_DBG (bcr, 4) }, 283254721Semaste{ DEFINE_DBG (bcr, 5) }, 284254721Semaste{ DEFINE_DBG (bcr, 6) }, 285254721Semaste{ DEFINE_DBG (bcr, 7) }, 286254721Semaste{ DEFINE_DBG (bcr, 8) }, 287254721Semaste{ DEFINE_DBG (bcr, 9) }, 288254721Semaste{ DEFINE_DBG (bcr, 10) }, 289254721Semaste{ DEFINE_DBG (bcr, 11) }, 290254721Semaste{ DEFINE_DBG (bcr, 12) }, 291254721Semaste{ DEFINE_DBG (bcr, 13) }, 292254721Semaste{ DEFINE_DBG (bcr, 14) }, 293254721Semaste{ DEFINE_DBG (bcr, 15) }, 294254721Semaste 295254721Semaste{ DEFINE_DBG (wvr, 0) }, 296254721Semaste{ DEFINE_DBG (wvr, 1) }, 297254721Semaste{ DEFINE_DBG (wvr, 2) }, 298254721Semaste{ DEFINE_DBG (wvr, 3) }, 299254721Semaste{ DEFINE_DBG (wvr, 4) }, 300254721Semaste{ DEFINE_DBG (wvr, 5) }, 301254721Semaste{ DEFINE_DBG (wvr, 6) }, 302254721Semaste{ DEFINE_DBG (wvr, 7) }, 303254721Semaste{ DEFINE_DBG (wvr, 8) }, 304254721Semaste{ DEFINE_DBG (wvr, 9) }, 305254721Semaste{ DEFINE_DBG (wvr, 10) }, 306254721Semaste{ DEFINE_DBG (wvr, 11) }, 307254721Semaste{ DEFINE_DBG (wvr, 12) }, 308254721Semaste{ DEFINE_DBG (wvr, 13) }, 309254721Semaste{ DEFINE_DBG (wvr, 14) }, 310254721Semaste{ DEFINE_DBG (wvr, 15) }, 311254721Semaste 312254721Semaste{ DEFINE_DBG (wcr, 0) }, 313254721Semaste{ DEFINE_DBG (wcr, 1) }, 314254721Semaste{ DEFINE_DBG (wcr, 2) }, 315254721Semaste{ DEFINE_DBG (wcr, 3) }, 316254721Semaste{ DEFINE_DBG (wcr, 4) }, 317254721Semaste{ DEFINE_DBG (wcr, 5) }, 318254721Semaste{ DEFINE_DBG (wcr, 6) }, 319254721Semaste{ DEFINE_DBG (wcr, 7) }, 320254721Semaste{ DEFINE_DBG (wcr, 8) }, 321254721Semaste{ DEFINE_DBG (wcr, 9) }, 322254721Semaste{ DEFINE_DBG (wcr, 10) }, 323254721Semaste{ DEFINE_DBG (wcr, 11) }, 324254721Semaste{ DEFINE_DBG (wcr, 12) }, 325254721Semaste{ DEFINE_DBG (wcr, 13) }, 326254721Semaste{ DEFINE_DBG (wcr, 14) }, 327254721Semaste{ DEFINE_DBG (wcr, 15) } 328254721Semaste}; 329254721Semaste 330254721Semaste// General purpose registers 331254721Semastestatic uint32_t 332254721Semasteg_gpr_regnums[] = 333254721Semaste{ 334254721Semaste gpr_r0, 335254721Semaste gpr_r1, 336254721Semaste gpr_r2, 337254721Semaste gpr_r3, 338254721Semaste gpr_r4, 339254721Semaste gpr_r5, 340254721Semaste gpr_r6, 341254721Semaste gpr_r7, 342254721Semaste gpr_r8, 343254721Semaste gpr_r9, 344254721Semaste gpr_r10, 345254721Semaste gpr_r11, 346254721Semaste gpr_r12, 347254721Semaste gpr_sp, 348254721Semaste gpr_lr, 349254721Semaste gpr_pc, 350254721Semaste gpr_cpsr 351254721Semaste}; 352254721Semaste 353254721Semaste// Floating point registers 354254721Semastestatic uint32_t 355254721Semasteg_fpu_regnums[] = 356254721Semaste{ 357254721Semaste fpu_s0, 358254721Semaste fpu_s1, 359254721Semaste fpu_s2, 360254721Semaste fpu_s3, 361254721Semaste fpu_s4, 362254721Semaste fpu_s5, 363254721Semaste fpu_s6, 364254721Semaste fpu_s7, 365254721Semaste fpu_s8, 366254721Semaste fpu_s9, 367254721Semaste fpu_s10, 368254721Semaste fpu_s11, 369254721Semaste fpu_s12, 370254721Semaste fpu_s13, 371254721Semaste fpu_s14, 372254721Semaste fpu_s15, 373254721Semaste fpu_s16, 374254721Semaste fpu_s17, 375254721Semaste fpu_s18, 376254721Semaste fpu_s19, 377254721Semaste fpu_s20, 378254721Semaste fpu_s21, 379254721Semaste fpu_s22, 380254721Semaste fpu_s23, 381254721Semaste fpu_s24, 382254721Semaste fpu_s25, 383254721Semaste fpu_s26, 384254721Semaste fpu_s27, 385254721Semaste fpu_s28, 386254721Semaste fpu_s29, 387254721Semaste fpu_s30, 388254721Semaste fpu_s31, 389254721Semaste fpu_fpscr, 390254721Semaste}; 391254721Semaste 392254721Semaste// Exception registers 393254721Semaste 394254721Semastestatic uint32_t 395254721Semasteg_exc_regnums[] = 396254721Semaste{ 397254721Semaste exc_exception, 398254721Semaste exc_fsr, 399254721Semaste exc_far, 400254721Semaste}; 401254721Semaste 402254721Semastestatic size_t k_num_register_infos = (sizeof(g_register_infos)/sizeof(RegisterInfo)); 403254721Semaste 404254721Semastevoid 405254721SemasteRegisterContextDarwin_arm::InvalidateAllRegisters () 406254721Semaste{ 407254721Semaste InvalidateAllRegisterStates(); 408254721Semaste} 409254721Semaste 410254721Semaste 411254721Semastesize_t 412254721SemasteRegisterContextDarwin_arm::GetRegisterCount () 413254721Semaste{ 414254721Semaste assert(k_num_register_infos == k_num_registers); 415254721Semaste return k_num_registers; 416254721Semaste} 417254721Semaste 418254721Semasteconst RegisterInfo * 419254721SemasteRegisterContextDarwin_arm::GetRegisterInfoAtIndex (size_t reg) 420254721Semaste{ 421254721Semaste assert(k_num_register_infos == k_num_registers); 422254721Semaste if (reg < k_num_registers) 423254721Semaste return &g_register_infos[reg]; 424254721Semaste return NULL; 425254721Semaste} 426254721Semaste 427254721Semastesize_t 428254721SemasteRegisterContextDarwin_arm::GetRegisterInfosCount () 429254721Semaste{ 430254721Semaste return k_num_register_infos; 431254721Semaste} 432254721Semaste 433254721Semasteconst RegisterInfo * 434254721SemasteRegisterContextDarwin_arm::GetRegisterInfos () 435254721Semaste{ 436254721Semaste return g_register_infos; 437254721Semaste} 438254721Semaste 439254721Semaste 440254721Semaste// Number of registers in each register set 441254721Semasteconst size_t k_num_gpr_registers = sizeof(g_gpr_regnums) / sizeof(uint32_t); 442254721Semasteconst size_t k_num_fpu_registers = sizeof(g_fpu_regnums) / sizeof(uint32_t); 443254721Semasteconst size_t k_num_exc_registers = sizeof(g_exc_regnums) / sizeof(uint32_t); 444254721Semaste 445254721Semaste//---------------------------------------------------------------------- 446254721Semaste// Register set definitions. The first definitions at register set index 447254721Semaste// of zero is for all registers, followed by other registers sets. The 448254721Semaste// register information for the all register set need not be filled in. 449254721Semaste//---------------------------------------------------------------------- 450254721Semastestatic const RegisterSet g_reg_sets[] = 451254721Semaste{ 452254721Semaste { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, }, 453254721Semaste { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums }, 454254721Semaste { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums } 455254721Semaste}; 456254721Semaste 457254721Semasteconst size_t k_num_regsets = sizeof(g_reg_sets) / sizeof(RegisterSet); 458254721Semaste 459254721Semaste 460254721Semastesize_t 461254721SemasteRegisterContextDarwin_arm::GetRegisterSetCount () 462254721Semaste{ 463254721Semaste return k_num_regsets; 464254721Semaste} 465254721Semaste 466254721Semasteconst RegisterSet * 467254721SemasteRegisterContextDarwin_arm::GetRegisterSet (size_t reg_set) 468254721Semaste{ 469254721Semaste if (reg_set < k_num_regsets) 470254721Semaste return &g_reg_sets[reg_set]; 471254721Semaste return NULL; 472254721Semaste} 473254721Semaste 474254721Semaste 475254721Semaste//---------------------------------------------------------------------- 476254721Semaste// Register information defintions for 32 bit i386. 477254721Semaste//---------------------------------------------------------------------- 478254721Semasteint 479254721SemasteRegisterContextDarwin_arm::GetSetForNativeRegNum (int reg) 480254721Semaste{ 481254721Semaste if (reg < fpu_s0) 482254721Semaste return GPRRegSet; 483254721Semaste else if (reg < exc_exception) 484254721Semaste return FPURegSet; 485254721Semaste else if (reg < k_num_registers) 486254721Semaste return EXCRegSet; 487254721Semaste return -1; 488254721Semaste} 489254721Semaste 490254721Semasteint 491254721SemasteRegisterContextDarwin_arm::ReadGPR (bool force) 492254721Semaste{ 493254721Semaste int set = GPRRegSet; 494254721Semaste if (force || !RegisterSetIsCached(set)) 495254721Semaste { 496254721Semaste SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 497254721Semaste } 498254721Semaste return GetError(GPRRegSet, Read); 499254721Semaste} 500254721Semaste 501254721Semasteint 502254721SemasteRegisterContextDarwin_arm::ReadFPU (bool force) 503254721Semaste{ 504254721Semaste int set = FPURegSet; 505254721Semaste if (force || !RegisterSetIsCached(set)) 506254721Semaste { 507254721Semaste SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 508254721Semaste } 509254721Semaste return GetError(FPURegSet, Read); 510254721Semaste} 511254721Semaste 512254721Semasteint 513254721SemasteRegisterContextDarwin_arm::ReadEXC (bool force) 514254721Semaste{ 515254721Semaste int set = EXCRegSet; 516254721Semaste if (force || !RegisterSetIsCached(set)) 517254721Semaste { 518254721Semaste SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 519254721Semaste } 520254721Semaste return GetError(EXCRegSet, Read); 521254721Semaste} 522254721Semaste 523254721Semasteint 524254721SemasteRegisterContextDarwin_arm::ReadDBG (bool force) 525254721Semaste{ 526254721Semaste int set = DBGRegSet; 527254721Semaste if (force || !RegisterSetIsCached(set)) 528254721Semaste { 529254721Semaste SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 530254721Semaste } 531254721Semaste return GetError(DBGRegSet, Read); 532254721Semaste} 533254721Semaste 534254721Semasteint 535254721SemasteRegisterContextDarwin_arm::WriteGPR () 536254721Semaste{ 537254721Semaste int set = GPRRegSet; 538254721Semaste if (!RegisterSetIsCached(set)) 539254721Semaste { 540254721Semaste SetError (set, Write, -1); 541254721Semaste return KERN_INVALID_ARGUMENT; 542254721Semaste } 543254721Semaste SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 544254721Semaste SetError (set, Read, -1); 545254721Semaste return GetError(GPRRegSet, Write); 546254721Semaste} 547254721Semaste 548254721Semasteint 549254721SemasteRegisterContextDarwin_arm::WriteFPU () 550254721Semaste{ 551254721Semaste int set = FPURegSet; 552254721Semaste if (!RegisterSetIsCached(set)) 553254721Semaste { 554254721Semaste SetError (set, Write, -1); 555254721Semaste return KERN_INVALID_ARGUMENT; 556254721Semaste } 557254721Semaste SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 558254721Semaste SetError (set, Read, -1); 559254721Semaste return GetError(FPURegSet, Write); 560254721Semaste} 561254721Semaste 562254721Semasteint 563254721SemasteRegisterContextDarwin_arm::WriteEXC () 564254721Semaste{ 565254721Semaste int set = EXCRegSet; 566254721Semaste if (!RegisterSetIsCached(set)) 567254721Semaste { 568254721Semaste SetError (set, Write, -1); 569254721Semaste return KERN_INVALID_ARGUMENT; 570254721Semaste } 571254721Semaste SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc)); 572254721Semaste SetError (set, Read, -1); 573254721Semaste return GetError(EXCRegSet, Write); 574254721Semaste} 575254721Semaste 576254721Semasteint 577254721SemasteRegisterContextDarwin_arm::WriteDBG () 578254721Semaste{ 579254721Semaste int set = DBGRegSet; 580254721Semaste if (!RegisterSetIsCached(set)) 581254721Semaste { 582254721Semaste SetError (set, Write, -1); 583254721Semaste return KERN_INVALID_ARGUMENT; 584254721Semaste } 585254721Semaste SetError (set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 586254721Semaste SetError (set, Read, -1); 587254721Semaste return GetError(DBGRegSet, Write); 588254721Semaste} 589254721Semaste 590254721Semaste 591254721Semasteint 592254721SemasteRegisterContextDarwin_arm::ReadRegisterSet (uint32_t set, bool force) 593254721Semaste{ 594254721Semaste switch (set) 595254721Semaste { 596254721Semaste case GPRRegSet: return ReadGPR(force); 597254721Semaste case FPURegSet: return ReadFPU(force); 598254721Semaste case EXCRegSet: return ReadEXC(force); 599254721Semaste case DBGRegSet: return ReadDBG(force); 600254721Semaste default: break; 601254721Semaste } 602254721Semaste return KERN_INVALID_ARGUMENT; 603254721Semaste} 604254721Semaste 605254721Semasteint 606254721SemasteRegisterContextDarwin_arm::WriteRegisterSet (uint32_t set) 607254721Semaste{ 608254721Semaste // Make sure we have a valid context to set. 609254721Semaste if (RegisterSetIsCached(set)) 610254721Semaste { 611254721Semaste switch (set) 612254721Semaste { 613254721Semaste case GPRRegSet: return WriteGPR(); 614254721Semaste case FPURegSet: return WriteFPU(); 615254721Semaste case EXCRegSet: return WriteEXC(); 616254721Semaste case DBGRegSet: return WriteDBG(); 617254721Semaste default: break; 618254721Semaste } 619254721Semaste } 620254721Semaste return KERN_INVALID_ARGUMENT; 621254721Semaste} 622254721Semaste 623254721Semastevoid 624254721SemasteRegisterContextDarwin_arm::LogDBGRegisters (Log *log, const DBG& dbg) 625254721Semaste{ 626254721Semaste if (log) 627254721Semaste { 628254721Semaste for (uint32_t i=0; i<16; i++) 629254721Semaste log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 630254721Semaste i, i, dbg.bvr[i], dbg.bcr[i], 631254721Semaste i, i, dbg.wvr[i], dbg.wcr[i]); 632254721Semaste } 633254721Semaste} 634254721Semaste 635254721Semaste 636254721Semastebool 637254721SemasteRegisterContextDarwin_arm::ReadRegister (const RegisterInfo *reg_info, RegisterValue &value) 638254721Semaste{ 639254721Semaste const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 640254721Semaste int set = RegisterContextDarwin_arm::GetSetForNativeRegNum (reg); 641254721Semaste 642254721Semaste if (set == -1) 643254721Semaste return false; 644254721Semaste 645254721Semaste if (ReadRegisterSet(set, false) != KERN_SUCCESS) 646254721Semaste return false; 647254721Semaste 648254721Semaste switch (reg) 649254721Semaste { 650254721Semaste case gpr_r0: 651254721Semaste case gpr_r1: 652254721Semaste case gpr_r2: 653254721Semaste case gpr_r3: 654254721Semaste case gpr_r4: 655254721Semaste case gpr_r5: 656254721Semaste case gpr_r6: 657254721Semaste case gpr_r7: 658254721Semaste case gpr_r8: 659254721Semaste case gpr_r9: 660254721Semaste case gpr_r10: 661254721Semaste case gpr_r11: 662254721Semaste case gpr_r12: 663254721Semaste case gpr_sp: 664254721Semaste case gpr_lr: 665254721Semaste case gpr_pc: 666254721Semaste case gpr_cpsr: 667254721Semaste value.SetUInt32 (gpr.r[reg - gpr_r0]); 668254721Semaste break; 669254721Semaste 670254721Semaste case fpu_s0: 671254721Semaste case fpu_s1: 672254721Semaste case fpu_s2: 673254721Semaste case fpu_s3: 674254721Semaste case fpu_s4: 675254721Semaste case fpu_s5: 676254721Semaste case fpu_s6: 677254721Semaste case fpu_s7: 678254721Semaste case fpu_s8: 679254721Semaste case fpu_s9: 680254721Semaste case fpu_s10: 681254721Semaste case fpu_s11: 682254721Semaste case fpu_s12: 683254721Semaste case fpu_s13: 684254721Semaste case fpu_s14: 685254721Semaste case fpu_s15: 686254721Semaste case fpu_s16: 687254721Semaste case fpu_s17: 688254721Semaste case fpu_s18: 689254721Semaste case fpu_s19: 690254721Semaste case fpu_s20: 691254721Semaste case fpu_s21: 692254721Semaste case fpu_s22: 693254721Semaste case fpu_s23: 694254721Semaste case fpu_s24: 695254721Semaste case fpu_s25: 696254721Semaste case fpu_s26: 697254721Semaste case fpu_s27: 698254721Semaste case fpu_s28: 699254721Semaste case fpu_s29: 700254721Semaste case fpu_s30: 701254721Semaste case fpu_s31: 702254721Semaste value.SetUInt32 (fpu.floats.s[reg], RegisterValue::eTypeFloat); 703254721Semaste break; 704254721Semaste 705254721Semaste case fpu_fpscr: 706254721Semaste value.SetUInt32 (fpu.fpscr); 707254721Semaste break; 708254721Semaste 709254721Semaste case exc_exception: 710254721Semaste value.SetUInt32 (exc.exception); 711254721Semaste break; 712254721Semaste case exc_fsr: 713254721Semaste value.SetUInt32 (exc.fsr); 714254721Semaste break; 715254721Semaste case exc_far: 716254721Semaste value.SetUInt32 (exc.far); 717254721Semaste break; 718254721Semaste 719254721Semaste default: 720254721Semaste value.SetValueToInvalid(); 721254721Semaste return false; 722254721Semaste 723254721Semaste } 724254721Semaste return true; 725254721Semaste} 726254721Semaste 727254721Semaste 728254721Semastebool 729254721SemasteRegisterContextDarwin_arm::WriteRegister (const RegisterInfo *reg_info, 730254721Semaste const RegisterValue &value) 731254721Semaste{ 732254721Semaste const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 733254721Semaste int set = GetSetForNativeRegNum (reg); 734254721Semaste 735254721Semaste if (set == -1) 736254721Semaste return false; 737254721Semaste 738254721Semaste if (ReadRegisterSet(set, false) != KERN_SUCCESS) 739254721Semaste return false; 740254721Semaste 741254721Semaste switch (reg) 742254721Semaste { 743254721Semaste case gpr_r0: 744254721Semaste case gpr_r1: 745254721Semaste case gpr_r2: 746254721Semaste case gpr_r3: 747254721Semaste case gpr_r4: 748254721Semaste case gpr_r5: 749254721Semaste case gpr_r6: 750254721Semaste case gpr_r7: 751254721Semaste case gpr_r8: 752254721Semaste case gpr_r9: 753254721Semaste case gpr_r10: 754254721Semaste case gpr_r11: 755254721Semaste case gpr_r12: 756254721Semaste case gpr_sp: 757254721Semaste case gpr_lr: 758254721Semaste case gpr_pc: 759254721Semaste case gpr_cpsr: 760254721Semaste gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 761254721Semaste break; 762254721Semaste 763254721Semaste case fpu_s0: 764254721Semaste case fpu_s1: 765254721Semaste case fpu_s2: 766254721Semaste case fpu_s3: 767254721Semaste case fpu_s4: 768254721Semaste case fpu_s5: 769254721Semaste case fpu_s6: 770254721Semaste case fpu_s7: 771254721Semaste case fpu_s8: 772254721Semaste case fpu_s9: 773254721Semaste case fpu_s10: 774254721Semaste case fpu_s11: 775254721Semaste case fpu_s12: 776254721Semaste case fpu_s13: 777254721Semaste case fpu_s14: 778254721Semaste case fpu_s15: 779254721Semaste case fpu_s16: 780254721Semaste case fpu_s17: 781254721Semaste case fpu_s18: 782254721Semaste case fpu_s19: 783254721Semaste case fpu_s20: 784254721Semaste case fpu_s21: 785254721Semaste case fpu_s22: 786254721Semaste case fpu_s23: 787254721Semaste case fpu_s24: 788254721Semaste case fpu_s25: 789254721Semaste case fpu_s26: 790254721Semaste case fpu_s27: 791254721Semaste case fpu_s28: 792254721Semaste case fpu_s29: 793254721Semaste case fpu_s30: 794254721Semaste case fpu_s31: 795254721Semaste fpu.floats.s[reg] = value.GetAsUInt32(); 796254721Semaste break; 797254721Semaste 798254721Semaste case fpu_fpscr: 799254721Semaste fpu.fpscr = value.GetAsUInt32(); 800254721Semaste break; 801254721Semaste 802254721Semaste case exc_exception: 803254721Semaste exc.exception = value.GetAsUInt32(); 804254721Semaste break; 805254721Semaste case exc_fsr: 806254721Semaste exc.fsr = value.GetAsUInt32(); 807254721Semaste break; 808254721Semaste case exc_far: 809254721Semaste exc.far = value.GetAsUInt32(); 810254721Semaste break; 811254721Semaste 812254721Semaste default: 813254721Semaste return false; 814254721Semaste 815254721Semaste } 816254721Semaste return WriteRegisterSet(set) == KERN_SUCCESS; 817254721Semaste} 818254721Semaste 819254721Semastebool 820254721SemasteRegisterContextDarwin_arm::ReadAllRegisterValues (lldb::DataBufferSP &data_sp) 821254721Semaste{ 822254721Semaste data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0)); 823254721Semaste if (data_sp && 824254721Semaste ReadGPR (false) == KERN_SUCCESS && 825254721Semaste ReadFPU (false) == KERN_SUCCESS && 826254721Semaste ReadEXC (false) == KERN_SUCCESS) 827254721Semaste { 828254721Semaste uint8_t *dst = data_sp->GetBytes(); 829254721Semaste ::memcpy (dst, &gpr, sizeof(gpr)); 830254721Semaste dst += sizeof(gpr); 831254721Semaste 832254721Semaste ::memcpy (dst, &fpu, sizeof(fpu)); 833254721Semaste dst += sizeof(gpr); 834254721Semaste 835254721Semaste ::memcpy (dst, &exc, sizeof(exc)); 836254721Semaste return true; 837254721Semaste } 838254721Semaste return false; 839254721Semaste} 840254721Semaste 841254721Semastebool 842254721SemasteRegisterContextDarwin_arm::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp) 843254721Semaste{ 844254721Semaste if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) 845254721Semaste { 846254721Semaste const uint8_t *src = data_sp->GetBytes(); 847254721Semaste ::memcpy (&gpr, src, sizeof(gpr)); 848254721Semaste src += sizeof(gpr); 849254721Semaste 850254721Semaste ::memcpy (&fpu, src, sizeof(fpu)); 851254721Semaste src += sizeof(gpr); 852254721Semaste 853254721Semaste ::memcpy (&exc, src, sizeof(exc)); 854254721Semaste uint32_t success_count = 0; 855254721Semaste if (WriteGPR() == KERN_SUCCESS) 856254721Semaste ++success_count; 857254721Semaste if (WriteFPU() == KERN_SUCCESS) 858254721Semaste ++success_count; 859254721Semaste if (WriteEXC() == KERN_SUCCESS) 860254721Semaste ++success_count; 861254721Semaste return success_count == 3; 862254721Semaste } 863254721Semaste return false; 864254721Semaste} 865254721Semaste 866254721Semasteuint32_t 867254721SemasteRegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber (uint32_t kind, uint32_t reg) 868254721Semaste{ 869254721Semaste if (kind == eRegisterKindGeneric) 870254721Semaste { 871254721Semaste switch (reg) 872254721Semaste { 873254721Semaste case LLDB_REGNUM_GENERIC_PC: return gpr_pc; 874254721Semaste case LLDB_REGNUM_GENERIC_SP: return gpr_sp; 875254721Semaste case LLDB_REGNUM_GENERIC_FP: return gpr_r7; 876254721Semaste case LLDB_REGNUM_GENERIC_RA: return gpr_lr; 877254721Semaste case LLDB_REGNUM_GENERIC_FLAGS: return gpr_cpsr; 878254721Semaste default: 879254721Semaste break; 880254721Semaste } 881254721Semaste } 882254721Semaste else if (kind == eRegisterKindDWARF) 883254721Semaste { 884254721Semaste switch (reg) 885254721Semaste { 886254721Semaste case dwarf_r0: return gpr_r0; 887254721Semaste case dwarf_r1: return gpr_r1; 888254721Semaste case dwarf_r2: return gpr_r2; 889254721Semaste case dwarf_r3: return gpr_r3; 890254721Semaste case dwarf_r4: return gpr_r4; 891254721Semaste case dwarf_r5: return gpr_r5; 892254721Semaste case dwarf_r6: return gpr_r6; 893254721Semaste case dwarf_r7: return gpr_r7; 894254721Semaste case dwarf_r8: return gpr_r8; 895254721Semaste case dwarf_r9: return gpr_r9; 896254721Semaste case dwarf_r10: return gpr_r10; 897254721Semaste case dwarf_r11: return gpr_r11; 898254721Semaste case dwarf_r12: return gpr_r12; 899254721Semaste case dwarf_sp: return gpr_sp; 900254721Semaste case dwarf_lr: return gpr_lr; 901254721Semaste case dwarf_pc: return gpr_pc; 902254721Semaste case dwarf_spsr: return gpr_cpsr; 903254721Semaste 904254721Semaste case dwarf_s0: return fpu_s0; 905254721Semaste case dwarf_s1: return fpu_s1; 906254721Semaste case dwarf_s2: return fpu_s2; 907254721Semaste case dwarf_s3: return fpu_s3; 908254721Semaste case dwarf_s4: return fpu_s4; 909254721Semaste case dwarf_s5: return fpu_s5; 910254721Semaste case dwarf_s6: return fpu_s6; 911254721Semaste case dwarf_s7: return fpu_s7; 912254721Semaste case dwarf_s8: return fpu_s8; 913254721Semaste case dwarf_s9: return fpu_s9; 914254721Semaste case dwarf_s10: return fpu_s10; 915254721Semaste case dwarf_s11: return fpu_s11; 916254721Semaste case dwarf_s12: return fpu_s12; 917254721Semaste case dwarf_s13: return fpu_s13; 918254721Semaste case dwarf_s14: return fpu_s14; 919254721Semaste case dwarf_s15: return fpu_s15; 920254721Semaste case dwarf_s16: return fpu_s16; 921254721Semaste case dwarf_s17: return fpu_s17; 922254721Semaste case dwarf_s18: return fpu_s18; 923254721Semaste case dwarf_s19: return fpu_s19; 924254721Semaste case dwarf_s20: return fpu_s20; 925254721Semaste case dwarf_s21: return fpu_s21; 926254721Semaste case dwarf_s22: return fpu_s22; 927254721Semaste case dwarf_s23: return fpu_s23; 928254721Semaste case dwarf_s24: return fpu_s24; 929254721Semaste case dwarf_s25: return fpu_s25; 930254721Semaste case dwarf_s26: return fpu_s26; 931254721Semaste case dwarf_s27: return fpu_s27; 932254721Semaste case dwarf_s28: return fpu_s28; 933254721Semaste case dwarf_s29: return fpu_s29; 934254721Semaste case dwarf_s30: return fpu_s30; 935254721Semaste case dwarf_s31: return fpu_s31; 936254721Semaste 937254721Semaste default: 938254721Semaste break; 939254721Semaste } 940254721Semaste } 941254721Semaste else if (kind == eRegisterKindGCC) 942254721Semaste { 943254721Semaste switch (reg) 944254721Semaste { 945254721Semaste case gcc_r0: return gpr_r0; 946254721Semaste case gcc_r1: return gpr_r1; 947254721Semaste case gcc_r2: return gpr_r2; 948254721Semaste case gcc_r3: return gpr_r3; 949254721Semaste case gcc_r4: return gpr_r4; 950254721Semaste case gcc_r5: return gpr_r5; 951254721Semaste case gcc_r6: return gpr_r6; 952254721Semaste case gcc_r7: return gpr_r7; 953254721Semaste case gcc_r8: return gpr_r8; 954254721Semaste case gcc_r9: return gpr_r9; 955254721Semaste case gcc_r10: return gpr_r10; 956254721Semaste case gcc_r11: return gpr_r11; 957254721Semaste case gcc_r12: return gpr_r12; 958254721Semaste case gcc_sp: return gpr_sp; 959254721Semaste case gcc_lr: return gpr_lr; 960254721Semaste case gcc_pc: return gpr_pc; 961254721Semaste case gcc_cpsr: return gpr_cpsr; 962254721Semaste } 963254721Semaste } 964254721Semaste else if (kind == eRegisterKindLLDB) 965254721Semaste { 966254721Semaste return reg; 967254721Semaste } 968254721Semaste return LLDB_INVALID_REGNUM; 969254721Semaste} 970254721Semaste 971254721Semaste 972254721Semasteuint32_t 973254721SemasteRegisterContextDarwin_arm::NumSupportedHardwareBreakpoints () 974254721Semaste{ 975254721Semaste#if defined (__arm__) 976254721Semaste // Set the init value to something that will let us know that we need to 977254721Semaste // autodetect how many breakpoints are supported dynamically... 978254721Semaste static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 979254721Semaste if (g_num_supported_hw_breakpoints == UINT32_MAX) 980254721Semaste { 981254721Semaste // Set this to zero in case we can't tell if there are any HW breakpoints 982254721Semaste g_num_supported_hw_breakpoints = 0; 983254721Semaste 984254721Semaste uint32_t register_DBGDIDR; 985254721Semaste 986254721Semaste asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR)); 987254721Semaste g_num_supported_hw_breakpoints = Bits32 (register_DBGDIDR, 27, 24); 988254721Semaste // Zero is reserved for the BRP count, so don't increment it if it is zero 989254721Semaste if (g_num_supported_hw_breakpoints > 0) 990254721Semaste g_num_supported_hw_breakpoints++; 991254721Semaste// if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_breakpoints); 992254721Semaste 993254721Semaste } 994254721Semaste return g_num_supported_hw_breakpoints; 995254721Semaste#else 996254721Semaste // TODO: figure out remote case here! 997254721Semaste return 6; 998254721Semaste#endif 999254721Semaste} 1000254721Semaste 1001254721Semasteuint32_t 1002254721SemasteRegisterContextDarwin_arm::SetHardwareBreakpoint (lldb::addr_t addr, size_t size) 1003254721Semaste{ 1004254721Semaste // Make sure our address isn't bogus 1005254721Semaste if (addr & 1) 1006254721Semaste return LLDB_INVALID_INDEX32; 1007254721Semaste 1008254721Semaste int kret = ReadDBG (false); 1009254721Semaste 1010254721Semaste if (kret == KERN_SUCCESS) 1011254721Semaste { 1012254721Semaste const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1013254721Semaste uint32_t i; 1014254721Semaste for (i=0; i<num_hw_breakpoints; ++i) 1015254721Semaste { 1016254721Semaste if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1017254721Semaste break; // We found an available hw breakpoint slot (in i) 1018254721Semaste } 1019254721Semaste 1020254721Semaste // See if we found an available hw breakpoint slot above 1021254721Semaste if (i < num_hw_breakpoints) 1022254721Semaste { 1023254721Semaste // Make sure bits 1:0 are clear in our address 1024254721Semaste dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1025254721Semaste 1026254721Semaste if (size == 2 || addr & 2) 1027254721Semaste { 1028254721Semaste uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1029254721Semaste 1030254721Semaste // We have a thumb breakpoint 1031254721Semaste // We have an ARM breakpoint 1032254721Semaste dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1033254721Semaste byte_addr_select | // Set the correct byte address select so we only trigger on the correct opcode 1034254721Semaste S_USER | // Which modes should this breakpoint stop in? 1035254721Semaste BCR_ENABLE; // Enable this hardware breakpoint 1036254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (Thumb)", 1037254721Semaste// addr, 1038254721Semaste// size, 1039254721Semaste// i, 1040254721Semaste// i, 1041254721Semaste// dbg.bvr[i], 1042254721Semaste// dbg.bcr[i]); 1043254721Semaste } 1044254721Semaste else if (size == 4) 1045254721Semaste { 1046254721Semaste // We have an ARM breakpoint 1047254721Semaste dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1048254721Semaste BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1049254721Semaste S_USER | // Which modes should this breakpoint stop in? 1050254721Semaste BCR_ENABLE; // Enable this hardware breakpoint 1051254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (ARM)", 1052254721Semaste// addr, 1053254721Semaste// size, 1054254721Semaste// i, 1055254721Semaste// i, 1056254721Semaste// dbg.bvr[i], 1057254721Semaste// dbg.bcr[i]); 1058254721Semaste } 1059254721Semaste 1060254721Semaste kret = WriteDBG(); 1061254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() WriteDBG() => 0x%8.8x.", kret); 1062254721Semaste 1063254721Semaste if (kret == KERN_SUCCESS) 1064254721Semaste return i; 1065254721Semaste } 1066254721Semaste// else 1067254721Semaste// { 1068254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = %8.8p, size = %u) => all hardware breakpoint resources are being used.", addr, size); 1069254721Semaste// } 1070254721Semaste } 1071254721Semaste 1072254721Semaste return LLDB_INVALID_INDEX32; 1073254721Semaste} 1074254721Semaste 1075254721Semastebool 1076254721SemasteRegisterContextDarwin_arm::ClearHardwareBreakpoint (uint32_t hw_index) 1077254721Semaste{ 1078254721Semaste int kret = ReadDBG (false); 1079254721Semaste 1080254721Semaste const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1081254721Semaste if (kret == KERN_SUCCESS) 1082254721Semaste { 1083254721Semaste if (hw_index < num_hw_points) 1084254721Semaste { 1085254721Semaste dbg.bcr[hw_index] = 0; 1086254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 1087254721Semaste// hw_index, 1088254721Semaste// hw_index, 1089254721Semaste// dbg.bvr[hw_index], 1090254721Semaste// hw_index, 1091254721Semaste// dbg.bcr[hw_index]); 1092254721Semaste 1093254721Semaste kret = WriteDBG(); 1094254721Semaste 1095254721Semaste if (kret == KERN_SUCCESS) 1096254721Semaste return true; 1097254721Semaste } 1098254721Semaste } 1099254721Semaste return false; 1100254721Semaste} 1101254721Semaste 1102254721Semasteuint32_t 1103254721SemasteRegisterContextDarwin_arm::NumSupportedHardwareWatchpoints () 1104254721Semaste{ 1105254721Semaste#if defined (__arm__) 1106254721Semaste // Set the init value to something that will let us know that we need to 1107254721Semaste // autodetect how many watchpoints are supported dynamically... 1108254721Semaste static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1109254721Semaste if (g_num_supported_hw_watchpoints == UINT32_MAX) 1110254721Semaste { 1111254721Semaste // Set this to zero in case we can't tell if there are any HW breakpoints 1112254721Semaste g_num_supported_hw_watchpoints = 0; 1113254721Semaste 1114254721Semaste uint32_t register_DBGDIDR; 1115254721Semaste asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR)); 1116254721Semaste g_num_supported_hw_watchpoints = Bits32 (register_DBGDIDR, 31, 28) + 1; 1117254721Semaste// if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_watchpoints); 1118254721Semaste } 1119254721Semaste return g_num_supported_hw_watchpoints; 1120254721Semaste#else 1121254721Semaste // TODO: figure out remote case here! 1122254721Semaste return 2; 1123254721Semaste#endif 1124254721Semaste} 1125254721Semaste 1126254721Semaste 1127254721Semasteuint32_t 1128254721SemasteRegisterContextDarwin_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t size, bool read, bool write) 1129254721Semaste{ 1130254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write); 1131254721Semaste 1132254721Semaste const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1133254721Semaste 1134254721Semaste // Can't watch zero bytes 1135254721Semaste if (size == 0) 1136254721Semaste return LLDB_INVALID_INDEX32; 1137254721Semaste 1138254721Semaste // We must watch for either read or write 1139254721Semaste if (read == false && write == false) 1140254721Semaste return LLDB_INVALID_INDEX32; 1141254721Semaste 1142254721Semaste // Can't watch more than 4 bytes per WVR/WCR pair 1143254721Semaste if (size > 4) 1144254721Semaste return LLDB_INVALID_INDEX32; 1145254721Semaste 1146254721Semaste // We can only watch up to four bytes that follow a 4 byte aligned address 1147254721Semaste // per watchpoint register pair. Since we have at most so we can only watch 1148254721Semaste // until the next 4 byte boundary and we need to make sure we can properly 1149254721Semaste // encode this. 1150254721Semaste uint32_t addr_word_offset = addr % 4; 1151254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - addr_word_offset = 0x%8.8x", addr_word_offset); 1152254721Semaste 1153254721Semaste uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1154254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 0x%8.8x", byte_mask); 1155254721Semaste if (byte_mask > 0xfu) 1156254721Semaste return LLDB_INVALID_INDEX32; 1157254721Semaste 1158254721Semaste // Read the debug state 1159254721Semaste int kret = ReadDBG (false); 1160254721Semaste 1161254721Semaste if (kret == KERN_SUCCESS) 1162254721Semaste { 1163254721Semaste // Check to make sure we have the needed hardware support 1164254721Semaste uint32_t i = 0; 1165254721Semaste 1166254721Semaste for (i=0; i<num_hw_watchpoints; ++i) 1167254721Semaste { 1168254721Semaste if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1169254721Semaste break; // We found an available hw breakpoint slot (in i) 1170254721Semaste } 1171254721Semaste 1172254721Semaste // See if we found an available hw breakpoint slot above 1173254721Semaste if (i < num_hw_watchpoints) 1174254721Semaste { 1175254721Semaste // Make the byte_mask into a valid Byte Address Select mask 1176254721Semaste uint32_t byte_address_select = byte_mask << 5; 1177254721Semaste // Make sure bits 1:0 are clear in our address 1178254721Semaste dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1179254721Semaste dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA that we will watch 1180254721Semaste S_USER | // Stop only in user mode 1181254721Semaste (read ? WCR_LOAD : 0) | // Stop on read access? 1182254721Semaste (write ? WCR_STORE : 0) | // Stop on write access? 1183254721Semaste WCR_ENABLE; // Enable this watchpoint; 1184254721Semaste 1185254721Semaste kret = WriteDBG(); 1186254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() WriteDBG() => 0x%8.8x.", kret); 1187254721Semaste 1188254721Semaste if (kret == KERN_SUCCESS) 1189254721Semaste return i; 1190254721Semaste } 1191254721Semaste else 1192254721Semaste { 1193254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 1194254721Semaste } 1195254721Semaste } 1196254721Semaste return LLDB_INVALID_INDEX32; 1197254721Semaste} 1198254721Semaste 1199254721Semastebool 1200254721SemasteRegisterContextDarwin_arm::ClearHardwareWatchpoint (uint32_t hw_index) 1201254721Semaste{ 1202254721Semaste int kret = ReadDBG (false); 1203254721Semaste 1204254721Semaste const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1205254721Semaste if (kret == KERN_SUCCESS) 1206254721Semaste { 1207254721Semaste if (hw_index < num_hw_points) 1208254721Semaste { 1209254721Semaste dbg.wcr[hw_index] = 0; 1210254721Semaste// if (log) log->Printf ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 1211254721Semaste// hw_index, 1212254721Semaste// hw_index, 1213254721Semaste// dbg.wvr[hw_index], 1214254721Semaste// hw_index, 1215254721Semaste// dbg.wcr[hw_index]); 1216254721Semaste 1217254721Semaste kret = WriteDBG(); 1218254721Semaste 1219254721Semaste if (kret == KERN_SUCCESS) 1220254721Semaste return true; 1221254721Semaste } 1222254721Semaste } 1223254721Semaste return false; 1224254721Semaste} 1225254721Semaste 1226254721Semaste#endif 1227