SIRegisterInfo.cpp revision 249259
1249259Sdim//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief SI implementation of the TargetRegisterInfo class. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim 16249259Sdim#include "SIRegisterInfo.h" 17249259Sdim#include "AMDGPUTargetMachine.h" 18249259Sdim 19249259Sdimusing namespace llvm; 20249259Sdim 21249259SdimSIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm, 22249259Sdim const TargetInstrInfo &tii) 23249259Sdim: AMDGPURegisterInfo(tm, tii), 24249259Sdim TM(tm), 25249259Sdim TII(tii) 26249259Sdim { } 27249259Sdim 28249259SdimBitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 29249259Sdim BitVector Reserved(getNumRegs()); 30249259Sdim return Reserved; 31249259Sdim} 32249259Sdim 33249259Sdimunsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 34249259Sdim MachineFunction &MF) const { 35249259Sdim return RC->getNumRegs(); 36249259Sdim} 37249259Sdim 38249259Sdimconst TargetRegisterClass * 39249259SdimSIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const { 40249259Sdim switch (rc->getID()) { 41249259Sdim case AMDGPU::GPRF32RegClassID: 42249259Sdim return &AMDGPU::VReg_32RegClass; 43249259Sdim default: return rc; 44249259Sdim } 45249259Sdim} 46249259Sdim 47249259Sdimconst TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( 48249259Sdim MVT VT) const { 49249259Sdim switch(VT.SimpleTy) { 50249259Sdim default: 51249259Sdim case MVT::i32: return &AMDGPU::VReg_32RegClass; 52249259Sdim } 53249259Sdim} 54