1249259Sdim//===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief R600 Machine Scheduler interface 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#ifndef R600MACHINESCHEDULER_H_ 16249259Sdim#define R600MACHINESCHEDULER_H_ 17249259Sdim 18249259Sdim#include "R600InstrInfo.h" 19263508Sdim#include "llvm/ADT/PriorityQueue.h" 20249259Sdim#include "llvm/CodeGen/MachineScheduler.h" 21249259Sdim#include "llvm/Support/Debug.h" 22249259Sdim 23249259Sdimusing namespace llvm; 24249259Sdim 25249259Sdimnamespace llvm { 26249259Sdim 27249259Sdimclass R600SchedStrategy : public MachineSchedStrategy { 28249259Sdim 29249259Sdim const ScheduleDAGMI *DAG; 30249259Sdim const R600InstrInfo *TII; 31249259Sdim const R600RegisterInfo *TRI; 32249259Sdim MachineRegisterInfo *MRI; 33249259Sdim 34249259Sdim enum InstKind { 35249259Sdim IDAlu, 36249259Sdim IDFetch, 37249259Sdim IDOther, 38249259Sdim IDLast 39249259Sdim }; 40249259Sdim 41249259Sdim enum AluKind { 42249259Sdim AluAny, 43249259Sdim AluT_X, 44249259Sdim AluT_Y, 45249259Sdim AluT_Z, 46249259Sdim AluT_W, 47249259Sdim AluT_XYZW, 48263508Sdim AluPredX, 49263508Sdim AluTrans, 50249259Sdim AluDiscarded, // LLVM Instructions that are going to be eliminated 51249259Sdim AluLast 52249259Sdim }; 53249259Sdim 54263508Sdim std::vector<SUnit *> Available[IDLast], Pending[IDLast]; 55263508Sdim std::vector<SUnit *> AvailableAlus[AluLast]; 56263508Sdim std::vector<SUnit *> PhysicalRegCopy; 57249259Sdim 58249259Sdim InstKind CurInstKind; 59249259Sdim int CurEmitted; 60249259Sdim InstKind NextInstKind; 61249259Sdim 62263508Sdim unsigned AluInstCount; 63263508Sdim unsigned FetchInstCount; 64263508Sdim 65249259Sdim int InstKindLimit[IDLast]; 66249259Sdim 67249259Sdim int OccupedSlotsMask; 68249259Sdim 69249259Sdimpublic: 70249259Sdim R600SchedStrategy() : 71249259Sdim DAG(0), TII(0), TRI(0), MRI(0) { 72249259Sdim } 73249259Sdim 74249259Sdim virtual ~R600SchedStrategy() { 75249259Sdim } 76249259Sdim 77249259Sdim virtual void initialize(ScheduleDAGMI *dag); 78249259Sdim virtual SUnit *pickNode(bool &IsTopNode); 79249259Sdim virtual void schedNode(SUnit *SU, bool IsTopNode); 80249259Sdim virtual void releaseTopNode(SUnit *SU); 81249259Sdim virtual void releaseBottomNode(SUnit *SU); 82249259Sdim 83249259Sdimprivate: 84249259Sdim std::vector<MachineInstr *> InstructionsGroupCandidate; 85263508Sdim bool VLIW5; 86249259Sdim 87249259Sdim int getInstKind(SUnit *SU); 88249259Sdim bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const; 89249259Sdim AluKind getAluKind(SUnit *SU) const; 90249259Sdim void LoadAlu(); 91263508Sdim unsigned AvailablesAluCount() const; 92263508Sdim SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu); 93249259Sdim void PrepareNextSlot(); 94263508Sdim SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU); 95249259Sdim 96249259Sdim void AssignSlot(MachineInstr *MI, unsigned Slot); 97249259Sdim SUnit* pickAlu(); 98249259Sdim SUnit* pickOther(int QID); 99263508Sdim void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst); 100249259Sdim}; 101249259Sdim 102249259Sdim} // namespace llvm 103249259Sdim 104249259Sdim#endif /* R600MACHINESCHEDULER_H_ */ 105