1214152Sed//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2214152Sed// 3214152Sed// The LLVM Compiler Infrastructure 4214152Sed// 5222656Sed// This file is distributed under the University of Illinois Open Source 6222656Sed// License. See LICENSE.TXT for details. 7214152Sed// 8214152Sed//===----------------------------------------------------------------------===// 9214152Sed// 10214152Sed/// \file 11214152Sed/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets. 12214152Sed// 13214152Sed//===----------------------------------------------------------------------===// 14214152Sed 15263560Sdim#ifndef AMDGPU_TARGET_MACHINE_H 16263560Sdim#define AMDGPU_TARGET_MACHINE_H 17263764Sdim 18214152Sed#include "AMDGPUFrameLowering.h" 19214152Sed#include "AMDGPUInstrInfo.h" 20214152Sed#include "AMDGPUSubtarget.h" 21214152Sed#include "AMDILIntrinsicInfo.h" 22214152Sed#include "R600ISelLowering.h" 23214152Sed#include "llvm/ADT/OwningPtr.h" 24214152Sed#include "llvm/IR/DataLayout.h" 25214152Sed 26214152Sednamespace llvm { 27214152Sed 28214152Sedclass AMDGPUTargetMachine : public LLVMTargetMachine { 29214152Sed 30214152Sed AMDGPUSubtarget Subtarget; 31214152Sed const DataLayout Layout; 32214152Sed AMDGPUFrameLowering FrameLowering; 33263764Sdim AMDGPUIntrinsicInfo IntrinsicInfo; 34 OwningPtr<AMDGPUInstrInfo> InstrInfo; 35 OwningPtr<AMDGPUTargetLowering> TLInfo; 36 const InstrItineraryData *InstrItins; 37 38public: 39 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS, 40 StringRef CPU, TargetOptions Options, Reloc::Model RM, 41 CodeModel::Model CM, CodeGenOpt::Level OL); 42 ~AMDGPUTargetMachine(); 43 virtual const AMDGPUFrameLowering *getFrameLowering() const { 44 return &FrameLowering; 45 } 46 virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { 47 return &IntrinsicInfo; 48 } 49 virtual const AMDGPUInstrInfo *getInstrInfo() const { 50 return InstrInfo.get(); 51 } 52 virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } 53 virtual const AMDGPURegisterInfo *getRegisterInfo() const { 54 return &InstrInfo->getRegisterInfo(); 55 } 56 virtual AMDGPUTargetLowering *getTargetLowering() const { 57 return TLInfo.get(); 58 } 59 virtual const InstrItineraryData *getInstrItineraryData() const { 60 return InstrItins; 61 } 62 virtual const DataLayout *getDataLayout() const { return &Layout; } 63 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); 64 65 /// \brief Register R600 analysis passes with a pass manager. 66 virtual void addAnalysisPasses(PassManagerBase &PM); 67}; 68 69} // End namespace llvm 70 71#endif // AMDGPU_TARGET_MACHINE_H 72