1249259Sdim//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file contains DAG node defintions for the AMDGPU target. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdim//===----------------------------------------------------------------------===// 15249259Sdim// AMDGPU DAG Profiles 16249259Sdim//===----------------------------------------------------------------------===// 17249259Sdim 18249259Sdimdef AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [ 19249259Sdim SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 20249259Sdim]>; 21249259Sdim 22249259Sdim//===----------------------------------------------------------------------===// 23249259Sdim// AMDGPU DAG Nodes 24249259Sdim// 25249259Sdim 26249259Sdim// This argument to this node is a dword address. 27249259Sdimdef AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>; 28249259Sdim 29249259Sdim// out = a - floor(a) 30249259Sdimdef AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; 31249259Sdim 32249259Sdim// out = max(a, b) a and b are floats 33249259Sdimdef AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp, 34249259Sdim [SDNPCommutative, SDNPAssociative] 35249259Sdim>; 36249259Sdim 37249259Sdim// out = max(a, b) a and b are signed ints 38249259Sdimdef AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, 39249259Sdim [SDNPCommutative, SDNPAssociative] 40249259Sdim>; 41249259Sdim 42249259Sdim// out = max(a, b) a and b are unsigned ints 43249259Sdimdef AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp, 44249259Sdim [SDNPCommutative, SDNPAssociative] 45249259Sdim>; 46249259Sdim 47249259Sdim// out = min(a, b) a and b are floats 48249259Sdimdef AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp, 49249259Sdim [SDNPCommutative, SDNPAssociative] 50249259Sdim>; 51249259Sdim 52249259Sdim// out = min(a, b) a snd b are signed ints 53249259Sdimdef AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp, 54249259Sdim [SDNPCommutative, SDNPAssociative] 55249259Sdim>; 56249259Sdim 57249259Sdim// out = min(a, b) a and b are unsigned ints 58249259Sdimdef AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, 59249259Sdim [SDNPCommutative, SDNPAssociative] 60249259Sdim>; 61249259Sdim 62249259Sdim// urecip - This operation is a helper for integer division, it returns the 63249259Sdim// result of 1 / a as a fractional unsigned integer. 64249259Sdim// out = (2^32 / a) + e 65249259Sdim// e is rounding error 66249259Sdimdef AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; 67249259Sdim 68249259Sdimdef AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD", 69249259Sdim SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 70249259Sdim [SDNPHasChain, SDNPMayLoad]>; 71249259Sdim 72249259Sdimdef AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE", 73249259Sdim SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 74249259Sdim [SDNPHasChain, SDNPMayStore]>; 75263508Sdim 76263508Sdim// MSKOR instructions are atomic memory instructions used mainly for storing 77263508Sdim// 8-bit and 16-bit values. The definition is: 78263508Sdim// 79263508Sdim// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src) 80263508Sdim// 81263508Sdim// src0: vec4(src, 0, 0, mask) 82263508Sdim// src1: dst - rat offset (aka pointer) in dwords 83263508Sdimdef AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR", 84263508Sdim SDTypeProfile<0, 2, []>, 85263508Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 86263508Sdim 87263508Sdimdef AMDGPUround : SDNode<"ISD::FROUND", 88263508Sdim SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>; 89