PPCInstrInfo.cpp revision 203954 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/raw_ostream.h"
25#include "llvm/MC/MCAsmInfo.h"
26using namespace llvm;
27
28extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
29extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
30
31PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
32  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
33    RI(*TM.getSubtargetImpl(), *this) {}
34
35bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
36                               unsigned& sourceReg,
37                               unsigned& destReg,
38                               unsigned& sourceSubIdx,
39                               unsigned& destSubIdx) const {
40  sourceSubIdx = destSubIdx = 0; // No sub-registers.
41
42  unsigned oc = MI.getOpcode();
43  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
44      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
45    assert(MI.getNumOperands() >= 3 &&
46           MI.getOperand(0).isReg() &&
47           MI.getOperand(1).isReg() &&
48           MI.getOperand(2).isReg() &&
49           "invalid PPC OR instruction!");
50    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
51      sourceReg = MI.getOperand(1).getReg();
52      destReg = MI.getOperand(0).getReg();
53      return true;
54    }
55  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
56    assert(MI.getNumOperands() >= 3 &&
57           MI.getOperand(0).isReg() &&
58           MI.getOperand(2).isImm() &&
59           "invalid PPC ADDI instruction!");
60    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
61      sourceReg = MI.getOperand(1).getReg();
62      destReg = MI.getOperand(0).getReg();
63      return true;
64    }
65  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
66    assert(MI.getNumOperands() >= 3 &&
67           MI.getOperand(0).isReg() &&
68           MI.getOperand(1).isReg() &&
69           MI.getOperand(2).isImm() &&
70           "invalid PPC ORI instruction!");
71    if (MI.getOperand(2).getImm() == 0) {
72      sourceReg = MI.getOperand(1).getReg();
73      destReg = MI.getOperand(0).getReg();
74      return true;
75    }
76  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
77             oc == PPC::FMRSD) {      // fmr r1, r2
78    assert(MI.getNumOperands() >= 2 &&
79           MI.getOperand(0).isReg() &&
80           MI.getOperand(1).isReg() &&
81           "invalid PPC FMR instruction");
82    sourceReg = MI.getOperand(1).getReg();
83    destReg = MI.getOperand(0).getReg();
84    return true;
85  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
86    assert(MI.getNumOperands() >= 2 &&
87           MI.getOperand(0).isReg() &&
88           MI.getOperand(1).isReg() &&
89           "invalid PPC MCRF instruction");
90    sourceReg = MI.getOperand(1).getReg();
91    destReg = MI.getOperand(0).getReg();
92    return true;
93  }
94  return false;
95}
96
97unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98                                           int &FrameIndex) const {
99  switch (MI->getOpcode()) {
100  default: break;
101  case PPC::LD:
102  case PPC::LWZ:
103  case PPC::LFS:
104  case PPC::LFD:
105    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
106        MI->getOperand(2).isFI()) {
107      FrameIndex = MI->getOperand(2).getIndex();
108      return MI->getOperand(0).getReg();
109    }
110    break;
111  }
112  return 0;
113}
114
115unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116                                          int &FrameIndex) const {
117  switch (MI->getOpcode()) {
118  default: break;
119  case PPC::STD:
120  case PPC::STW:
121  case PPC::STFS:
122  case PPC::STFD:
123    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
124        MI->getOperand(2).isFI()) {
125      FrameIndex = MI->getOperand(2).getIndex();
126      return MI->getOperand(0).getReg();
127    }
128    break;
129  }
130  return 0;
131}
132
133// commuteInstruction - We can commute rlwimi instructions, but only if the
134// rotate amt is zero.  We also have to munge the immediates a bit.
135MachineInstr *
136PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
137  MachineFunction &MF = *MI->getParent()->getParent();
138
139  // Normal instructions can be commuted the obvious way.
140  if (MI->getOpcode() != PPC::RLWIMI)
141    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
142
143  // Cannot commute if it has a non-zero rotate count.
144  if (MI->getOperand(3).getImm() != 0)
145    return 0;
146
147  // If we have a zero rotate count, we have:
148  //   M = mask(MB,ME)
149  //   Op0 = (Op1 & ~M) | (Op2 & M)
150  // Change this to:
151  //   M = mask((ME+1)&31, (MB-1)&31)
152  //   Op0 = (Op2 & ~M) | (Op1 & M)
153
154  // Swap op1/op2
155  unsigned Reg0 = MI->getOperand(0).getReg();
156  unsigned Reg1 = MI->getOperand(1).getReg();
157  unsigned Reg2 = MI->getOperand(2).getReg();
158  bool Reg1IsKill = MI->getOperand(1).isKill();
159  bool Reg2IsKill = MI->getOperand(2).isKill();
160  bool ChangeReg0 = false;
161  // If machine instrs are no longer in two-address forms, update
162  // destination register as well.
163  if (Reg0 == Reg1) {
164    // Must be two address instruction!
165    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
166           "Expecting a two-address instruction!");
167    Reg2IsKill = false;
168    ChangeReg0 = true;
169  }
170
171  // Masks.
172  unsigned MB = MI->getOperand(4).getImm();
173  unsigned ME = MI->getOperand(5).getImm();
174
175  if (NewMI) {
176    // Create a new instruction.
177    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
178    bool Reg0IsDead = MI->getOperand(0).isDead();
179    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
180      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
181      .addReg(Reg2, getKillRegState(Reg2IsKill))
182      .addReg(Reg1, getKillRegState(Reg1IsKill))
183      .addImm((ME+1) & 31)
184      .addImm((MB-1) & 31);
185  }
186
187  if (ChangeReg0)
188    MI->getOperand(0).setReg(Reg2);
189  MI->getOperand(2).setReg(Reg1);
190  MI->getOperand(1).setReg(Reg2);
191  MI->getOperand(2).setIsKill(Reg1IsKill);
192  MI->getOperand(1).setIsKill(Reg2IsKill);
193
194  // Swap the mask around.
195  MI->getOperand(4).setImm((ME+1) & 31);
196  MI->getOperand(5).setImm((MB-1) & 31);
197  return MI;
198}
199
200void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
201                              MachineBasicBlock::iterator MI) const {
202  DebugLoc DL = DebugLoc::getUnknownLoc();
203  if (MI != MBB.end()) DL = MI->getDebugLoc();
204
205  BuildMI(MBB, MI, DL, get(PPC::NOP));
206}
207
208
209// Branch analysis.
210bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
211                                 MachineBasicBlock *&FBB,
212                                 SmallVectorImpl<MachineOperand> &Cond,
213                                 bool AllowModify) const {
214  // If the block has no terminators, it just falls into the block after it.
215  MachineBasicBlock::iterator I = MBB.end();
216  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
217    return false;
218
219  // Get the last instruction in the block.
220  MachineInstr *LastInst = I;
221
222  // If there is only one terminator instruction, process it.
223  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224    if (LastInst->getOpcode() == PPC::B) {
225      if (!LastInst->getOperand(0).isMBB())
226        return true;
227      TBB = LastInst->getOperand(0).getMBB();
228      return false;
229    } else if (LastInst->getOpcode() == PPC::BCC) {
230      if (!LastInst->getOperand(2).isMBB())
231        return true;
232      // Block ends with fall-through condbranch.
233      TBB = LastInst->getOperand(2).getMBB();
234      Cond.push_back(LastInst->getOperand(0));
235      Cond.push_back(LastInst->getOperand(1));
236      return false;
237    }
238    // Otherwise, don't know what this is.
239    return true;
240  }
241
242  // Get the instruction before it if it's a terminator.
243  MachineInstr *SecondLastInst = I;
244
245  // If there are three terminators, we don't know what sort of block this is.
246  if (SecondLastInst && I != MBB.begin() &&
247      isUnpredicatedTerminator(--I))
248    return true;
249
250  // If the block ends with PPC::B and PPC:BCC, handle it.
251  if (SecondLastInst->getOpcode() == PPC::BCC &&
252      LastInst->getOpcode() == PPC::B) {
253    if (!SecondLastInst->getOperand(2).isMBB() ||
254        !LastInst->getOperand(0).isMBB())
255      return true;
256    TBB =  SecondLastInst->getOperand(2).getMBB();
257    Cond.push_back(SecondLastInst->getOperand(0));
258    Cond.push_back(SecondLastInst->getOperand(1));
259    FBB = LastInst->getOperand(0).getMBB();
260    return false;
261  }
262
263  // If the block ends with two PPC:Bs, handle it.  The second one is not
264  // executed, so remove it.
265  if (SecondLastInst->getOpcode() == PPC::B &&
266      LastInst->getOpcode() == PPC::B) {
267    if (!SecondLastInst->getOperand(0).isMBB())
268      return true;
269    TBB = SecondLastInst->getOperand(0).getMBB();
270    I = LastInst;
271    if (AllowModify)
272      I->eraseFromParent();
273    return false;
274  }
275
276  // Otherwise, can't handle this.
277  return true;
278}
279
280unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281  MachineBasicBlock::iterator I = MBB.end();
282  if (I == MBB.begin()) return 0;
283  --I;
284  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
285    return 0;
286
287  // Remove the branch.
288  I->eraseFromParent();
289
290  I = MBB.end();
291
292  if (I == MBB.begin()) return 1;
293  --I;
294  if (I->getOpcode() != PPC::BCC)
295    return 1;
296
297  // Remove the branch.
298  I->eraseFromParent();
299  return 2;
300}
301
302unsigned
303PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
304                           MachineBasicBlock *FBB,
305                           const SmallVectorImpl<MachineOperand> &Cond) const {
306  // FIXME this should probably have a DebugLoc argument
307  DebugLoc dl = DebugLoc::getUnknownLoc();
308  // Shouldn't be a fall through.
309  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
310  assert((Cond.size() == 2 || Cond.size() == 0) &&
311         "PPC branch conditions have two components!");
312
313  // One-way branch.
314  if (FBB == 0) {
315    if (Cond.empty())   // Unconditional branch
316      BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
317    else                // Conditional branch
318      BuildMI(&MBB, dl, get(PPC::BCC))
319        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
320    return 1;
321  }
322
323  // Two-way Conditional Branch.
324  BuildMI(&MBB, dl, get(PPC::BCC))
325    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
326  BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
327  return 2;
328}
329
330bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
331                                   MachineBasicBlock::iterator MI,
332                                   unsigned DestReg, unsigned SrcReg,
333                                   const TargetRegisterClass *DestRC,
334                                   const TargetRegisterClass *SrcRC) const {
335  if (DestRC != SrcRC) {
336    // Not yet supported!
337    return false;
338  }
339
340  DebugLoc DL = DebugLoc::getUnknownLoc();
341  if (MI != MBB.end()) DL = MI->getDebugLoc();
342
343  if (DestRC == PPC::GPRCRegisterClass) {
344    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
345  } else if (DestRC == PPC::G8RCRegisterClass) {
346    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
347  } else if (DestRC == PPC::F4RCRegisterClass) {
348    BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
349  } else if (DestRC == PPC::F8RCRegisterClass) {
350    BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
351  } else if (DestRC == PPC::CRRCRegisterClass) {
352    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
353  } else if (DestRC == PPC::VRRCRegisterClass) {
354    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
355  } else if (DestRC == PPC::CRBITRCRegisterClass) {
356    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
357  } else {
358    // Attempt to copy register that is not GPR or FPR
359    return false;
360  }
361
362  return true;
363}
364
365bool
366PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
367                                  unsigned SrcReg, bool isKill,
368                                  int FrameIdx,
369                                  const TargetRegisterClass *RC,
370                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
371  DebugLoc DL = DebugLoc::getUnknownLoc();
372  if (RC == PPC::GPRCRegisterClass) {
373    if (SrcReg != PPC::LR) {
374      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
375                                         .addReg(SrcReg,
376                                                 getKillRegState(isKill)),
377                                         FrameIdx));
378    } else {
379      // FIXME: this spills LR immediately to memory in one step.  To do this,
380      // we use R11, which we know cannot be used in the prolog/epilog.  This is
381      // a hack.
382      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
383      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
384                                         .addReg(PPC::R11,
385                                                 getKillRegState(isKill)),
386                                         FrameIdx));
387    }
388  } else if (RC == PPC::G8RCRegisterClass) {
389    if (SrcReg != PPC::LR8) {
390      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
391                                         .addReg(SrcReg,
392                                                 getKillRegState(isKill)),
393                                         FrameIdx));
394    } else {
395      // FIXME: this spills LR immediately to memory in one step.  To do this,
396      // we use R11, which we know cannot be used in the prolog/epilog.  This is
397      // a hack.
398      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
399      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
400                                         .addReg(PPC::X11,
401                                                 getKillRegState(isKill)),
402                                         FrameIdx));
403    }
404  } else if (RC == PPC::F8RCRegisterClass) {
405    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
406                                       .addReg(SrcReg,
407                                               getKillRegState(isKill)),
408                                       FrameIdx));
409  } else if (RC == PPC::F4RCRegisterClass) {
410    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
411                                       .addReg(SrcReg,
412                                               getKillRegState(isKill)),
413                                       FrameIdx));
414  } else if (RC == PPC::CRRCRegisterClass) {
415    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
416        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
417      // FIXME (64-bit): Enable
418      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
419                                         .addReg(SrcReg,
420                                                 getKillRegState(isKill)),
421                                         FrameIdx));
422      return true;
423    } else {
424      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
425      // it's possible for the stack frame to be so big the save location is
426      // out of range of immediate offsets, necessitating another register.
427      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
428      // at the moment.
429
430      // We need to store the CR in the low 4-bits of the saved value.  First,
431      // issue a MFCR to save all of the CRBits.
432      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
433                                                           PPC::R2 : PPC::R0;
434      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
435
436      // If the saved register wasn't CR0, shift the bits left so that they are
437      // in CR0's slot.
438      if (SrcReg != PPC::CR0) {
439        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
440        // rlwinm scratch, scratch, ShiftBits, 0, 31.
441        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
442                       .addReg(ScratchReg).addImm(ShiftBits)
443                       .addImm(0).addImm(31));
444      }
445
446      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
447                                         .addReg(ScratchReg,
448                                                 getKillRegState(isKill)),
449                                         FrameIdx));
450    }
451  } else if (RC == PPC::CRBITRCRegisterClass) {
452    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
453    // backend currently only uses CR1EQ as an individual bit, this should
454    // not cause any bug. If we need other uses of CR bits, the following
455    // code may be invalid.
456    unsigned Reg = 0;
457    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
458        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
459      Reg = PPC::CR0;
460    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
461             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
462      Reg = PPC::CR1;
463    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
464             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
465      Reg = PPC::CR2;
466    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
467             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
468      Reg = PPC::CR3;
469    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
470             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
471      Reg = PPC::CR4;
472    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
473             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
474      Reg = PPC::CR5;
475    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
476             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
477      Reg = PPC::CR6;
478    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
479             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
480      Reg = PPC::CR7;
481
482    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
483                               PPC::CRRCRegisterClass, NewMIs);
484
485  } else if (RC == PPC::VRRCRegisterClass) {
486    // We don't have indexed addressing for vector loads.  Emit:
487    // R0 = ADDI FI#
488    // STVX VAL, 0, R0
489    //
490    // FIXME: We use R0 here, because it isn't available for RA.
491    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
492                                       FrameIdx, 0, 0));
493    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
494                     .addReg(SrcReg, getKillRegState(isKill))
495                     .addReg(PPC::R0)
496                     .addReg(PPC::R0));
497  } else {
498    llvm_unreachable("Unknown regclass!");
499  }
500
501  return false;
502}
503
504void
505PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
506                                  MachineBasicBlock::iterator MI,
507                                  unsigned SrcReg, bool isKill, int FrameIdx,
508                                  const TargetRegisterClass *RC) const {
509  MachineFunction &MF = *MBB.getParent();
510  SmallVector<MachineInstr*, 4> NewMIs;
511
512  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
513    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
514    FuncInfo->setSpillsCR();
515  }
516
517  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
518    MBB.insert(MI, NewMIs[i]);
519}
520
521void
522PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
523                                   unsigned DestReg, int FrameIdx,
524                                   const TargetRegisterClass *RC,
525                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
526  if (RC == PPC::GPRCRegisterClass) {
527    if (DestReg != PPC::LR) {
528      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
529                                                 DestReg), FrameIdx));
530    } else {
531      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
532                                                 PPC::R11), FrameIdx));
533      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
534    }
535  } else if (RC == PPC::G8RCRegisterClass) {
536    if (DestReg != PPC::LR8) {
537      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
538                                         FrameIdx));
539    } else {
540      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
541                                                 PPC::R11), FrameIdx));
542      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
543    }
544  } else if (RC == PPC::F8RCRegisterClass) {
545    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
546                                       FrameIdx));
547  } else if (RC == PPC::F4RCRegisterClass) {
548    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
549                                       FrameIdx));
550  } else if (RC == PPC::CRRCRegisterClass) {
551    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
552    // it's possible for the stack frame to be so big the save location is
553    // out of range of immediate offsets, necessitating another register.
554    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
555    // at the moment.
556    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
557                                                          PPC::R2 : PPC::R0;
558    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
559                                       ScratchReg), FrameIdx));
560
561    // If the reloaded register isn't CR0, shift the bits right so that they are
562    // in the right CR's slot.
563    if (DestReg != PPC::CR0) {
564      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
565      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
566      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
567                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
568                    .addImm(31));
569    }
570
571    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
572                     .addReg(ScratchReg));
573  } else if (RC == PPC::CRBITRCRegisterClass) {
574
575    unsigned Reg = 0;
576    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
577        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
578      Reg = PPC::CR0;
579    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
580             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
581      Reg = PPC::CR1;
582    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
583             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
584      Reg = PPC::CR2;
585    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
586             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
587      Reg = PPC::CR3;
588    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
589             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
590      Reg = PPC::CR4;
591    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
592             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
593      Reg = PPC::CR5;
594    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
595             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
596      Reg = PPC::CR6;
597    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
598             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
599      Reg = PPC::CR7;
600
601    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
602                                PPC::CRRCRegisterClass, NewMIs);
603
604  } else if (RC == PPC::VRRCRegisterClass) {
605    // We don't have indexed addressing for vector loads.  Emit:
606    // R0 = ADDI FI#
607    // Dest = LVX 0, R0
608    //
609    // FIXME: We use R0 here, because it isn't available for RA.
610    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
611                                       FrameIdx, 0, 0));
612    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
613                     .addReg(PPC::R0));
614  } else {
615    llvm_unreachable("Unknown regclass!");
616  }
617}
618
619void
620PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
621                                   MachineBasicBlock::iterator MI,
622                                   unsigned DestReg, int FrameIdx,
623                                   const TargetRegisterClass *RC) const {
624  MachineFunction &MF = *MBB.getParent();
625  SmallVector<MachineInstr*, 4> NewMIs;
626  DebugLoc DL = DebugLoc::getUnknownLoc();
627  if (MI != MBB.end()) DL = MI->getDebugLoc();
628  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
629  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
630    MBB.insert(MI, NewMIs[i]);
631}
632
633/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
634/// copy instructions, turning them into load/store instructions.
635MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
636                                                  MachineInstr *MI,
637                                           const SmallVectorImpl<unsigned> &Ops,
638                                                  int FrameIndex) const {
639  if (Ops.size() != 1) return NULL;
640
641  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
642  // it takes more than one instruction to store it.
643  unsigned Opc = MI->getOpcode();
644  unsigned OpNum = Ops[0];
645
646  MachineInstr *NewMI = NULL;
647  if ((Opc == PPC::OR &&
648       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
649    if (OpNum == 0) {  // move -> store
650      unsigned InReg = MI->getOperand(1).getReg();
651      bool isKill = MI->getOperand(1).isKill();
652      bool isUndef = MI->getOperand(1).isUndef();
653      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
654                                .addReg(InReg,
655                                        getKillRegState(isKill) |
656                                        getUndefRegState(isUndef)),
657                                FrameIndex);
658    } else {           // move -> load
659      unsigned OutReg = MI->getOperand(0).getReg();
660      bool isDead = MI->getOperand(0).isDead();
661      bool isUndef = MI->getOperand(0).isUndef();
662      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
663                                .addReg(OutReg,
664                                        RegState::Define |
665                                        getDeadRegState(isDead) |
666                                        getUndefRegState(isUndef)),
667                                FrameIndex);
668    }
669  } else if ((Opc == PPC::OR8 &&
670              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
671    if (OpNum == 0) {  // move -> store
672      unsigned InReg = MI->getOperand(1).getReg();
673      bool isKill = MI->getOperand(1).isKill();
674      bool isUndef = MI->getOperand(1).isUndef();
675      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
676                                .addReg(InReg,
677                                        getKillRegState(isKill) |
678                                        getUndefRegState(isUndef)),
679                                FrameIndex);
680    } else {           // move -> load
681      unsigned OutReg = MI->getOperand(0).getReg();
682      bool isDead = MI->getOperand(0).isDead();
683      bool isUndef = MI->getOperand(0).isUndef();
684      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
685                                .addReg(OutReg,
686                                        RegState::Define |
687                                        getDeadRegState(isDead) |
688                                        getUndefRegState(isUndef)),
689                                FrameIndex);
690    }
691  } else if (Opc == PPC::FMRD) {
692    if (OpNum == 0) {  // move -> store
693      unsigned InReg = MI->getOperand(1).getReg();
694      bool isKill = MI->getOperand(1).isKill();
695      bool isUndef = MI->getOperand(1).isUndef();
696      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
697                                .addReg(InReg,
698                                        getKillRegState(isKill) |
699                                        getUndefRegState(isUndef)),
700                                FrameIndex);
701    } else {           // move -> load
702      unsigned OutReg = MI->getOperand(0).getReg();
703      bool isDead = MI->getOperand(0).isDead();
704      bool isUndef = MI->getOperand(0).isUndef();
705      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
706                                .addReg(OutReg,
707                                        RegState::Define |
708                                        getDeadRegState(isDead) |
709                                        getUndefRegState(isUndef)),
710                                FrameIndex);
711    }
712  } else if (Opc == PPC::FMRS) {
713    if (OpNum == 0) {  // move -> store
714      unsigned InReg = MI->getOperand(1).getReg();
715      bool isKill = MI->getOperand(1).isKill();
716      bool isUndef = MI->getOperand(1).isUndef();
717      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
718                                .addReg(InReg,
719                                        getKillRegState(isKill) |
720                                        getUndefRegState(isUndef)),
721                                FrameIndex);
722    } else {           // move -> load
723      unsigned OutReg = MI->getOperand(0).getReg();
724      bool isDead = MI->getOperand(0).isDead();
725      bool isUndef = MI->getOperand(0).isUndef();
726      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
727                                .addReg(OutReg,
728                                        RegState::Define |
729                                        getDeadRegState(isDead) |
730                                        getUndefRegState(isUndef)),
731                                FrameIndex);
732    }
733  }
734
735  return NewMI;
736}
737
738bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
739                                  const SmallVectorImpl<unsigned> &Ops) const {
740  if (Ops.size() != 1) return false;
741
742  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
743  // it takes more than one instruction to store it.
744  unsigned Opc = MI->getOpcode();
745
746  if ((Opc == PPC::OR &&
747       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
748    return true;
749  else if ((Opc == PPC::OR8 &&
750              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
751    return true;
752  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
753    return true;
754
755  return false;
756}
757
758
759bool PPCInstrInfo::
760ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
761  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
762  // Leave the CR# the same, but invert the condition.
763  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
764  return false;
765}
766
767/// GetInstSize - Return the number of bytes of code the specified
768/// instruction may be.  This returns the maximum number of bytes.
769///
770unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
771  switch (MI->getOpcode()) {
772  case PPC::INLINEASM: {       // Inline Asm: Variable size.
773    const MachineFunction *MF = MI->getParent()->getParent();
774    const char *AsmStr = MI->getOperand(0).getSymbolName();
775    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
776  }
777  case PPC::DBG_LABEL:
778  case PPC::EH_LABEL:
779  case PPC::GC_LABEL:
780    return 0;
781  default:
782    return 4; // PowerPC instructions are all 4 bytes
783  }
784}
785