1193323Sed//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines a pattern matching instruction selector for PowerPC, 11193323Sed// converting from a legalized dag to a PPC dag. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#define DEBUG_TYPE "ppc-codegen" 16193323Sed#include "PPC.h" 17249423Sdim#include "MCTargetDesc/PPCPredicates.h" 18193323Sed#include "PPCTargetMachine.h" 19249423Sdim#include "llvm/CodeGen/MachineFunction.h" 20193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 21193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 22193323Sed#include "llvm/CodeGen/SelectionDAG.h" 23193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 24249423Sdim#include "llvm/IR/Constants.h" 25249423Sdim#include "llvm/IR/Function.h" 26249423Sdim#include "llvm/IR/GlobalAlias.h" 27249423Sdim#include "llvm/IR/GlobalValue.h" 28249423Sdim#include "llvm/IR/GlobalVariable.h" 29249423Sdim#include "llvm/IR/Intrinsics.h" 30193323Sed#include "llvm/Support/Debug.h" 31249423Sdim#include "llvm/Support/ErrorHandling.h" 32193323Sed#include "llvm/Support/MathExtras.h" 33198090Srdivacky#include "llvm/Support/raw_ostream.h" 34249423Sdim#include "llvm/Target/TargetOptions.h" 35193323Sedusing namespace llvm; 36193323Sed 37249423Sdimnamespace llvm { 38249423Sdim void initializePPCDAGToDAGISelPass(PassRegistry&); 39249423Sdim} 40249423Sdim 41193323Sednamespace { 42193323Sed //===--------------------------------------------------------------------===// 43193323Sed /// PPCDAGToDAGISel - PPC specific code to select PPC machine 44193323Sed /// instructions for SelectionDAG operations. 45193323Sed /// 46198892Srdivacky class PPCDAGToDAGISel : public SelectionDAGISel { 47207618Srdivacky const PPCTargetMachine &TM; 48207618Srdivacky const PPCTargetLowering &PPCLowering; 49193323Sed const PPCSubtarget &PPCSubTarget; 50193323Sed unsigned GlobalBaseReg; 51193323Sed public: 52193323Sed explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 53193323Sed : SelectionDAGISel(tm), TM(tm), 54193323Sed PPCLowering(*TM.getTargetLowering()), 55249423Sdim PPCSubTarget(*TM.getSubtargetImpl()) { 56249423Sdim initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry()); 57249423Sdim } 58218893Sdim 59198090Srdivacky virtual bool runOnMachineFunction(MachineFunction &MF) { 60193323Sed // Make sure we re-emit a set of the global base reg if necessary 61193323Sed GlobalBaseReg = 0; 62198090Srdivacky SelectionDAGISel::runOnMachineFunction(MF); 63218893Sdim 64243830Sdim if (!PPCSubTarget.isSVR4ABI()) 65243830Sdim InsertVRSaveCode(MF); 66243830Sdim 67193323Sed return true; 68193323Sed } 69218893Sdim 70249423Sdim virtual void PostprocessISelDAG(); 71249423Sdim 72193323Sed /// getI32Imm - Return a target constant with the specified value, of type 73193323Sed /// i32. 74193323Sed inline SDValue getI32Imm(unsigned Imm) { 75193323Sed return CurDAG->getTargetConstant(Imm, MVT::i32); 76193323Sed } 77193323Sed 78193323Sed /// getI64Imm - Return a target constant with the specified value, of type 79193323Sed /// i64. 80193323Sed inline SDValue getI64Imm(uint64_t Imm) { 81193323Sed return CurDAG->getTargetConstant(Imm, MVT::i64); 82193323Sed } 83218893Sdim 84193323Sed /// getSmallIPtrImm - Return a target constant of pointer type. 85193323Sed inline SDValue getSmallIPtrImm(unsigned Imm) { 86193323Sed return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 87193323Sed } 88218893Sdim 89218893Sdim /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 90193323Sed /// with any number of 0s on either side. The 1s are allowed to wrap from 91193323Sed /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 92193323Sed /// 0x0F0F0000 is not, since all 1s are not contiguous. 93193323Sed static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 94193323Sed 95193323Sed 96193323Sed /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 97193323Sed /// rotate and mask opcode and mask operation. 98199989Srdivacky static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, 99193323Sed unsigned &SH, unsigned &MB, unsigned &ME); 100218893Sdim 101193323Sed /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 102193323Sed /// base register. Return the virtual register that holds this value. 103193323Sed SDNode *getGlobalBaseReg(); 104218893Sdim 105193323Sed // Select - Convert the specified operand from a target-independent to a 106193323Sed // target-specific node if it hasn't already been changed. 107202375Srdivacky SDNode *Select(SDNode *N); 108218893Sdim 109193323Sed SDNode *SelectBitfieldInsert(SDNode *N); 110193323Sed 111193323Sed /// SelectCC - Select a comparison of the specified values with the 112193323Sed /// specified condition code, returning the CR# of the expression. 113263508Sdim SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 114193323Sed 115193323Sed /// SelectAddrImm - Returns true if the address N can be represented by 116193323Sed /// a base register plus a signed 16-bit displacement [r+imm]. 117218893Sdim bool SelectAddrImm(SDValue N, SDValue &Disp, 118193323Sed SDValue &Base) { 119263508Sdim return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, false); 120193323Sed } 121218893Sdim 122193323Sed /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 123249423Sdim /// immediate field. Note that the operand at this point is already the 124249423Sdim /// result of a prior SelectAddressRegImm call. 125218893Sdim bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 126249423Sdim if (N.getOpcode() == ISD::TargetConstant || 127239462Sdim N.getOpcode() == ISD::TargetGlobalAddress) { 128239462Sdim Out = N; 129239462Sdim return true; 130239462Sdim } 131239462Sdim 132239462Sdim return false; 133239462Sdim } 134239462Sdim 135193323Sed /// SelectAddrIdx - Given the specified addressed, check to see if it can be 136193323Sed /// represented as an indexed [r+r] operation. Returns false if it can 137193323Sed /// be represented by [r+imm], which are preferred. 138218893Sdim bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { 139193323Sed return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); 140193323Sed } 141218893Sdim 142193323Sed /// SelectAddrIdxOnly - Given the specified addressed, force it to be 143193323Sed /// represented as an indexed [r+r] operation. 144218893Sdim bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { 145193323Sed return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); 146193323Sed } 147193323Sed 148263508Sdim /// SelectAddrImmX4 - Returns true if the address N can be represented by 149263508Sdim /// a base register plus a signed 16-bit displacement that is a multiple of 4. 150263508Sdim /// Suitable for use by STD and friends. 151263508Sdim bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { 152263508Sdim return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, true); 153193323Sed } 154218893Sdim 155249423Sdim // Select an address into a single register. 156249423Sdim bool SelectAddr(SDValue N, SDValue &Base) { 157249423Sdim Base = N; 158249423Sdim return true; 159249423Sdim } 160249423Sdim 161193323Sed /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 162198090Srdivacky /// inline asm expressions. It is always correct to compute the value into 163198090Srdivacky /// a register. The case of adding a (possibly relocatable) constant to a 164198090Srdivacky /// register can be improved, but it is wrong to substitute Reg+Reg for 165198090Srdivacky /// Reg in an asm, because the load or store opcode would have to change. 166198090Srdivacky virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 167193323Sed char ConstraintCode, 168193323Sed std::vector<SDValue> &OutOps) { 169198090Srdivacky OutOps.push_back(Op); 170193323Sed return false; 171193323Sed } 172218893Sdim 173198090Srdivacky void InsertVRSaveCode(MachineFunction &MF); 174193323Sed 175193323Sed virtual const char *getPassName() const { 176193323Sed return "PowerPC DAG->DAG Pattern Instruction Selection"; 177193323Sed } 178193323Sed 179193323Sed// Include the pieces autogenerated from the target description. 180193323Sed#include "PPCGenDAGISel.inc" 181218893Sdim 182193323Sedprivate: 183202375Srdivacky SDNode *SelectSETCC(SDNode *N); 184193323Sed }; 185193323Sed} 186193323Sed 187193323Sed/// InsertVRSaveCode - Once the entire function has been instruction selected, 188193323Sed/// all virtual registers are created and all machine instructions are built, 189193323Sed/// check to see if we need to save/restore VRSAVE. If so, do it. 190198090Srdivackyvoid PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { 191193323Sed // Check to see if this function uses vector registers, which means we have to 192218893Sdim // save and restore the VRSAVE register and update it with the regs we use. 193193323Sed // 194203954Srdivacky // In this case, there will be virtual registers of vector type created 195193323Sed // by the scheduler. Detect them now. 196193323Sed bool HasVectorVReg = false; 197218893Sdim for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 198218893Sdim unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 199218893Sdim if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 200193323Sed HasVectorVReg = true; 201193323Sed break; 202193323Sed } 203218893Sdim } 204193323Sed if (!HasVectorVReg) return; // nothing to do. 205218893Sdim 206193323Sed // If we have a vector register, we want to emit code into the entry and exit 207193323Sed // blocks to save and restore the VRSAVE register. We do this here (instead 208193323Sed // of marking all vector instructions as clobbering VRSAVE) for two reasons: 209193323Sed // 210193323Sed // 1. This (trivially) reduces the load on the register allocator, by not 211193323Sed // having to represent the live range of the VRSAVE register. 212193323Sed // 2. This (more significantly) allows us to create a temporary virtual 213193323Sed // register to hold the saved VRSAVE value, allowing this temporary to be 214193323Sed // register allocated, instead of forcing it to be spilled to the stack. 215193323Sed 216193323Sed // Create two vregs - one to hold the VRSAVE register that is live-in to the 217193323Sed // function and one for the value after having bits or'd into it. 218193323Sed unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 219193323Sed unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 220218893Sdim 221193323Sed const TargetInstrInfo &TII = *TM.getInstrInfo(); 222193323Sed MachineBasicBlock &EntryBB = *Fn.begin(); 223206124Srdivacky DebugLoc dl; 224193323Sed // Emit the following code into the entry block: 225193323Sed // InVRSAVE = MFVRSAVE 226193323Sed // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 227193323Sed // MTVRSAVE UpdatedVRSAVE 228193323Sed MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 229193323Sed BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 230193323Sed BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 231193323Sed UpdatedVRSAVE).addReg(InVRSAVE); 232193323Sed BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 233218893Sdim 234193323Sed // Find all return blocks, outputting a restore in each epilog. 235193323Sed for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 236234353Sdim if (!BB->empty() && BB->back().isReturn()) { 237193323Sed IP = BB->end(); --IP; 238218893Sdim 239193323Sed // Skip over all terminator instructions, which are part of the return 240193323Sed // sequence. 241193323Sed MachineBasicBlock::iterator I2 = IP; 242234353Sdim while (I2 != BB->begin() && (--I2)->isTerminator()) 243193323Sed IP = I2; 244218893Sdim 245193323Sed // Emit: MTVRSAVE InVRSave 246193323Sed BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 247218893Sdim } 248193323Sed } 249193323Sed} 250193323Sed 251193323Sed 252193323Sed/// getGlobalBaseReg - Output the instructions required to put the 253193323Sed/// base address to use for accessing globals into a register. 254193323Sed/// 255193323SedSDNode *PPCDAGToDAGISel::getGlobalBaseReg() { 256193323Sed if (!GlobalBaseReg) { 257193323Sed const TargetInstrInfo &TII = *TM.getInstrInfo(); 258193323Sed // Insert the set of GlobalBaseReg into the first MBB of the function 259198090Srdivacky MachineBasicBlock &FirstMBB = MF->front(); 260193323Sed MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 261206124Srdivacky DebugLoc dl; 262193323Sed 263193323Sed if (PPCLowering.getPointerTy() == MVT::i32) { 264266715Sdim GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass); 265223017Sdim BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 266193323Sed BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 267193323Sed } else { 268266715Sdim GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass); 269223017Sdim BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 270193323Sed BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 271193323Sed } 272193323Sed } 273193323Sed return CurDAG->getRegister(GlobalBaseReg, 274193323Sed PPCLowering.getPointerTy()).getNode(); 275193323Sed} 276193323Sed 277193323Sed/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 278193323Sed/// or 64-bit immediate, and if the value can be accurately represented as a 279193323Sed/// sign extension from a 16-bit value. If so, this returns true and the 280193323Sed/// immediate. 281193323Sedstatic bool isIntS16Immediate(SDNode *N, short &Imm) { 282193323Sed if (N->getOpcode() != ISD::Constant) 283193323Sed return false; 284193323Sed 285193323Sed Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 286193323Sed if (N->getValueType(0) == MVT::i32) 287193323Sed return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 288193323Sed else 289193323Sed return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 290193323Sed} 291193323Sed 292193323Sedstatic bool isIntS16Immediate(SDValue Op, short &Imm) { 293193323Sed return isIntS16Immediate(Op.getNode(), Imm); 294193323Sed} 295193323Sed 296193323Sed 297193323Sed/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 298193323Sed/// operand. If so Imm will receive the 32-bit value. 299193323Sedstatic bool isInt32Immediate(SDNode *N, unsigned &Imm) { 300193323Sed if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 301193323Sed Imm = cast<ConstantSDNode>(N)->getZExtValue(); 302193323Sed return true; 303193323Sed } 304193323Sed return false; 305193323Sed} 306193323Sed 307193323Sed/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 308193323Sed/// operand. If so Imm will receive the 64-bit value. 309193323Sedstatic bool isInt64Immediate(SDNode *N, uint64_t &Imm) { 310193323Sed if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 311193323Sed Imm = cast<ConstantSDNode>(N)->getZExtValue(); 312193323Sed return true; 313193323Sed } 314193323Sed return false; 315193323Sed} 316193323Sed 317193323Sed// isInt32Immediate - This method tests to see if a constant operand. 318193323Sed// If so Imm will receive the 32 bit value. 319193323Sedstatic bool isInt32Immediate(SDValue N, unsigned &Imm) { 320193323Sed return isInt32Immediate(N.getNode(), Imm); 321193323Sed} 322193323Sed 323193323Sed 324193323Sed// isOpcWithIntImmediate - This method tests to see if the node is a specific 325193323Sed// opcode and that it has a immediate integer right operand. 326193323Sed// If so Imm will receive the 32 bit value. 327193323Sedstatic bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 328193323Sed return N->getOpcode() == Opc 329193323Sed && isInt32Immediate(N->getOperand(1).getNode(), Imm); 330193323Sed} 331193323Sed 332193323Sedbool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 333263508Sdim if (!Val) 334263508Sdim return false; 335263508Sdim 336193323Sed if (isShiftedMask_32(Val)) { 337193323Sed // look for the first non-zero bit 338263508Sdim MB = countLeadingZeros(Val); 339193323Sed // look for the first zero bit after the run of ones 340263508Sdim ME = countLeadingZeros((Val - 1) ^ Val); 341193323Sed return true; 342193323Sed } else { 343193323Sed Val = ~Val; // invert mask 344193323Sed if (isShiftedMask_32(Val)) { 345193323Sed // effectively look for the first zero bit 346263508Sdim ME = countLeadingZeros(Val) - 1; 347193323Sed // effectively look for the first one bit after the run of zeros 348263508Sdim MB = countLeadingZeros((Val - 1) ^ Val) + 1; 349193323Sed return true; 350193323Sed } 351193323Sed } 352193323Sed // no run present 353193323Sed return false; 354193323Sed} 355193323Sed 356218893Sdimbool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, 357218893Sdim bool isShiftMask, unsigned &SH, 358193323Sed unsigned &MB, unsigned &ME) { 359193323Sed // Don't even go down this path for i64, since different logic will be 360193323Sed // necessary for rldicl/rldicr/rldimi. 361193323Sed if (N->getValueType(0) != MVT::i32) 362193323Sed return false; 363193323Sed 364193323Sed unsigned Shift = 32; 365193323Sed unsigned Indeterminant = ~0; // bit mask marking indeterminant results 366193323Sed unsigned Opcode = N->getOpcode(); 367193323Sed if (N->getNumOperands() != 2 || 368193323Sed !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 369193323Sed return false; 370218893Sdim 371193323Sed if (Opcode == ISD::SHL) { 372193323Sed // apply shift left to mask if it comes first 373199989Srdivacky if (isShiftMask) Mask = Mask << Shift; 374193323Sed // determine which bits are made indeterminant by shift 375193323Sed Indeterminant = ~(0xFFFFFFFFu << Shift); 376218893Sdim } else if (Opcode == ISD::SRL) { 377193323Sed // apply shift right to mask if it comes first 378199989Srdivacky if (isShiftMask) Mask = Mask >> Shift; 379193323Sed // determine which bits are made indeterminant by shift 380193323Sed Indeterminant = ~(0xFFFFFFFFu >> Shift); 381193323Sed // adjust for the left rotate 382193323Sed Shift = 32 - Shift; 383193323Sed } else if (Opcode == ISD::ROTL) { 384193323Sed Indeterminant = 0; 385193323Sed } else { 386193323Sed return false; 387193323Sed } 388218893Sdim 389193323Sed // if the mask doesn't intersect any Indeterminant bits 390193323Sed if (Mask && !(Mask & Indeterminant)) { 391193323Sed SH = Shift & 31; 392193323Sed // make sure the mask is still a mask (wrap arounds may not be) 393193323Sed return isRunOfOnes(Mask, MB, ME); 394193323Sed } 395193323Sed return false; 396193323Sed} 397193323Sed 398193323Sed/// SelectBitfieldInsert - turn an or of two masked values into 399193323Sed/// the rotate left word immediate then mask insert (rlwimi) instruction. 400193323SedSDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 401193323Sed SDValue Op0 = N->getOperand(0); 402193323Sed SDValue Op1 = N->getOperand(1); 403263508Sdim SDLoc dl(N); 404218893Sdim 405193323Sed APInt LKZ, LKO, RKZ, RKO; 406234353Sdim CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); 407234353Sdim CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 408218893Sdim 409193323Sed unsigned TargetMask = LKZ.getZExtValue(); 410193323Sed unsigned InsertMask = RKZ.getZExtValue(); 411218893Sdim 412193323Sed if ((TargetMask | InsertMask) == 0xFFFFFFFF) { 413193323Sed unsigned Op0Opc = Op0.getOpcode(); 414193323Sed unsigned Op1Opc = Op1.getOpcode(); 415193323Sed unsigned Value, SH = 0; 416193323Sed TargetMask = ~TargetMask; 417193323Sed InsertMask = ~InsertMask; 418193323Sed 419193323Sed // If the LHS has a foldable shift and the RHS does not, then swap it to the 420193323Sed // RHS so that we can fold the shift into the insert. 421193323Sed if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 422193323Sed if (Op0.getOperand(0).getOpcode() == ISD::SHL || 423193323Sed Op0.getOperand(0).getOpcode() == ISD::SRL) { 424193323Sed if (Op1.getOperand(0).getOpcode() != ISD::SHL && 425193323Sed Op1.getOperand(0).getOpcode() != ISD::SRL) { 426193323Sed std::swap(Op0, Op1); 427193323Sed std::swap(Op0Opc, Op1Opc); 428193323Sed std::swap(TargetMask, InsertMask); 429193323Sed } 430193323Sed } 431193323Sed } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 432193323Sed if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 433193323Sed Op1.getOperand(0).getOpcode() != ISD::SRL) { 434193323Sed std::swap(Op0, Op1); 435193323Sed std::swap(Op0Opc, Op1Opc); 436193323Sed std::swap(TargetMask, InsertMask); 437193323Sed } 438193323Sed } 439218893Sdim 440193323Sed unsigned MB, ME; 441263508Sdim if (isRunOfOnes(InsertMask, MB, ME)) { 442199989Srdivacky SDValue Tmp1, Tmp2; 443193323Sed 444193323Sed if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 445193323Sed isInt32Immediate(Op1.getOperand(1), Value)) { 446193323Sed Op1 = Op1.getOperand(0); 447193323Sed SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 448193323Sed } 449193323Sed if (Op1Opc == ISD::AND) { 450193323Sed unsigned SHOpc = Op1.getOperand(0).getOpcode(); 451193323Sed if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 452193323Sed isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 453263508Sdim // Note that Value must be in range here (less than 32) because 454263508Sdim // otherwise there would not be any bits set in InsertMask. 455193323Sed Op1 = Op1.getOperand(0).getOperand(0); 456193323Sed SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 457193323Sed } 458193323Sed } 459199989Srdivacky 460193323Sed SH &= 31; 461199989Srdivacky SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), 462193323Sed getI32Imm(ME) }; 463251662Sdim return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 464193323Sed } 465193323Sed } 466193323Sed return 0; 467193323Sed} 468193323Sed 469193323Sed/// SelectCC - Select a comparison of the specified values with the specified 470193323Sed/// condition code, returning the CR# of the expression. 471193323SedSDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 472263508Sdim ISD::CondCode CC, SDLoc dl) { 473193323Sed // Always select the LHS. 474193323Sed unsigned Opc; 475218893Sdim 476193323Sed if (LHS.getValueType() == MVT::i32) { 477193323Sed unsigned Imm; 478193323Sed if (CC == ISD::SETEQ || CC == ISD::SETNE) { 479193323Sed if (isInt32Immediate(RHS, Imm)) { 480193323Sed // SETEQ/SETNE comparison with 16-bit immediate, fold it. 481206083Srdivacky if (isUInt<16>(Imm)) 482198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 483198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 484193323Sed // If this is a 16-bit signed immediate, fold it. 485206083Srdivacky if (isInt<16>((int)Imm)) 486198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 487198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 488218893Sdim 489193323Sed // For non-equality comparisons, the default code would materialize the 490193323Sed // constant, then compare against it, like this: 491193323Sed // lis r2, 4660 492218893Sdim // ori r2, r2, 22136 493193323Sed // cmpw cr0, r3, r2 494193323Sed // Since we are just comparing for equality, we can emit this instead: 495193323Sed // xoris r0,r3,0x1234 496193323Sed // cmplwi cr0,r0,0x5678 497193323Sed // beq cr0,L6 498198090Srdivacky SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, 499198090Srdivacky getI32Imm(Imm >> 16)), 0); 500198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, 501198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 502193323Sed } 503193323Sed Opc = PPC::CMPLW; 504193323Sed } else if (ISD::isUnsignedIntSetCC(CC)) { 505206083Srdivacky if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) 506198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 507198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 508193323Sed Opc = PPC::CMPLW; 509193323Sed } else { 510193323Sed short SImm; 511193323Sed if (isIntS16Immediate(RHS, SImm)) 512198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 513198090Srdivacky getI32Imm((int)SImm & 0xFFFF)), 514193323Sed 0); 515193323Sed Opc = PPC::CMPW; 516193323Sed } 517193323Sed } else if (LHS.getValueType() == MVT::i64) { 518193323Sed uint64_t Imm; 519193323Sed if (CC == ISD::SETEQ || CC == ISD::SETNE) { 520193323Sed if (isInt64Immediate(RHS.getNode(), Imm)) { 521193323Sed // SETEQ/SETNE comparison with 16-bit immediate, fold it. 522206083Srdivacky if (isUInt<16>(Imm)) 523198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 524198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 525193323Sed // If this is a 16-bit signed immediate, fold it. 526206083Srdivacky if (isInt<16>(Imm)) 527198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 528198090Srdivacky getI32Imm(Imm & 0xFFFF)), 0); 529218893Sdim 530193323Sed // For non-equality comparisons, the default code would materialize the 531193323Sed // constant, then compare against it, like this: 532193323Sed // lis r2, 4660 533218893Sdim // ori r2, r2, 22136 534193323Sed // cmpd cr0, r3, r2 535193323Sed // Since we are just comparing for equality, we can emit this instead: 536193323Sed // xoris r0,r3,0x1234 537193323Sed // cmpldi cr0,r0,0x5678 538193323Sed // beq cr0,L6 539206083Srdivacky if (isUInt<32>(Imm)) { 540198090Srdivacky SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 541198090Srdivacky getI64Imm(Imm >> 16)), 0); 542198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 543198090Srdivacky getI64Imm(Imm & 0xFFFF)), 0); 544193323Sed } 545193323Sed } 546193323Sed Opc = PPC::CMPLD; 547193323Sed } else if (ISD::isUnsignedIntSetCC(CC)) { 548206083Srdivacky if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) 549198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 550198090Srdivacky getI64Imm(Imm & 0xFFFF)), 0); 551193323Sed Opc = PPC::CMPLD; 552193323Sed } else { 553193323Sed short SImm; 554193323Sed if (isIntS16Immediate(RHS, SImm)) 555198090Srdivacky return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 556198090Srdivacky getI64Imm(SImm & 0xFFFF)), 557193323Sed 0); 558193323Sed Opc = PPC::CMPD; 559193323Sed } 560193323Sed } else if (LHS.getValueType() == MVT::f32) { 561193323Sed Opc = PPC::FCMPUS; 562193323Sed } else { 563193323Sed assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 564193323Sed Opc = PPC::FCMPUD; 565193323Sed } 566198090Srdivacky return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); 567193323Sed} 568193323Sed 569193323Sedstatic PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 570193323Sed switch (CC) { 571193323Sed case ISD::SETUEQ: 572193323Sed case ISD::SETONE: 573193323Sed case ISD::SETOLE: 574193323Sed case ISD::SETOGE: 575198090Srdivacky llvm_unreachable("Should be lowered by legalize!"); 576198090Srdivacky default: llvm_unreachable("Unknown condition!"); 577193323Sed case ISD::SETOEQ: 578193323Sed case ISD::SETEQ: return PPC::PRED_EQ; 579193323Sed case ISD::SETUNE: 580193323Sed case ISD::SETNE: return PPC::PRED_NE; 581193323Sed case ISD::SETOLT: 582193323Sed case ISD::SETLT: return PPC::PRED_LT; 583193323Sed case ISD::SETULE: 584193323Sed case ISD::SETLE: return PPC::PRED_LE; 585193323Sed case ISD::SETOGT: 586193323Sed case ISD::SETGT: return PPC::PRED_GT; 587193323Sed case ISD::SETUGE: 588193323Sed case ISD::SETGE: return PPC::PRED_GE; 589193323Sed case ISD::SETO: return PPC::PRED_NU; 590193323Sed case ISD::SETUO: return PPC::PRED_UN; 591193323Sed // These two are invalid for floating point. Assume we have int. 592193323Sed case ISD::SETULT: return PPC::PRED_LT; 593193323Sed case ISD::SETUGT: return PPC::PRED_GT; 594193323Sed } 595193323Sed} 596193323Sed 597193323Sed/// getCRIdxForSetCC - Return the index of the condition register field 598193323Sed/// associated with the SetCC condition, and whether or not the field is 599193323Sed/// treated as inverted. That is, lt = 0; ge = 0 inverted. 600263508Sdimstatic unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 601193323Sed Invert = false; 602193323Sed switch (CC) { 603198090Srdivacky default: llvm_unreachable("Unknown condition!"); 604193323Sed case ISD::SETOLT: 605193323Sed case ISD::SETLT: return 0; // Bit #0 = SETOLT 606193323Sed case ISD::SETOGT: 607193323Sed case ISD::SETGT: return 1; // Bit #1 = SETOGT 608193323Sed case ISD::SETOEQ: 609193323Sed case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 610193323Sed case ISD::SETUO: return 3; // Bit #3 = SETUO 611193323Sed case ISD::SETUGE: 612193323Sed case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 613193323Sed case ISD::SETULE: 614193323Sed case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 615193323Sed case ISD::SETUNE: 616193323Sed case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 617193323Sed case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 618218893Sdim case ISD::SETUEQ: 619218893Sdim case ISD::SETOGE: 620218893Sdim case ISD::SETOLE: 621193323Sed case ISD::SETONE: 622198090Srdivacky llvm_unreachable("Invalid branch code: should be expanded by legalize"); 623193323Sed // These are invalid for floating point. Assume integer. 624193323Sed case ISD::SETULT: return 0; 625193323Sed case ISD::SETUGT: return 1; 626193323Sed } 627193323Sed} 628193323Sed 629243830Sdim// getVCmpInst: return the vector compare instruction for the specified 630243830Sdim// vector type and condition code. Since this is for altivec specific code, 631243830Sdim// only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 632243830Sdimstatic unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { 633243830Sdim switch (CC) { 634243830Sdim case ISD::SETEQ: 635243830Sdim case ISD::SETUEQ: 636243830Sdim case ISD::SETNE: 637243830Sdim case ISD::SETUNE: 638243830Sdim if (VecVT == MVT::v16i8) 639243830Sdim return PPC::VCMPEQUB; 640243830Sdim else if (VecVT == MVT::v8i16) 641243830Sdim return PPC::VCMPEQUH; 642243830Sdim else if (VecVT == MVT::v4i32) 643243830Sdim return PPC::VCMPEQUW; 644243830Sdim // v4f32 != v4f32 could be translate to unordered not equal 645243830Sdim else if (VecVT == MVT::v4f32) 646243830Sdim return PPC::VCMPEQFP; 647243830Sdim break; 648243830Sdim case ISD::SETLT: 649243830Sdim case ISD::SETGT: 650243830Sdim case ISD::SETLE: 651243830Sdim case ISD::SETGE: 652243830Sdim if (VecVT == MVT::v16i8) 653243830Sdim return PPC::VCMPGTSB; 654243830Sdim else if (VecVT == MVT::v8i16) 655243830Sdim return PPC::VCMPGTSH; 656243830Sdim else if (VecVT == MVT::v4i32) 657243830Sdim return PPC::VCMPGTSW; 658243830Sdim else if (VecVT == MVT::v4f32) 659243830Sdim return PPC::VCMPGTFP; 660243830Sdim break; 661243830Sdim case ISD::SETULT: 662243830Sdim case ISD::SETUGT: 663243830Sdim case ISD::SETUGE: 664243830Sdim case ISD::SETULE: 665243830Sdim if (VecVT == MVT::v16i8) 666243830Sdim return PPC::VCMPGTUB; 667243830Sdim else if (VecVT == MVT::v8i16) 668243830Sdim return PPC::VCMPGTUH; 669243830Sdim else if (VecVT == MVT::v4i32) 670243830Sdim return PPC::VCMPGTUW; 671243830Sdim break; 672243830Sdim case ISD::SETOEQ: 673243830Sdim if (VecVT == MVT::v4f32) 674243830Sdim return PPC::VCMPEQFP; 675243830Sdim break; 676243830Sdim case ISD::SETOLT: 677243830Sdim case ISD::SETOGT: 678243830Sdim case ISD::SETOLE: 679243830Sdim if (VecVT == MVT::v4f32) 680243830Sdim return PPC::VCMPGTFP; 681243830Sdim break; 682243830Sdim case ISD::SETOGE: 683243830Sdim if (VecVT == MVT::v4f32) 684243830Sdim return PPC::VCMPGEFP; 685243830Sdim break; 686243830Sdim default: 687243830Sdim break; 688243830Sdim } 689243830Sdim llvm_unreachable("Invalid integer vector compare condition"); 690243830Sdim} 691243830Sdim 692243830Sdim// getVCmpEQInst: return the equal compare instruction for the specified vector 693243830Sdim// type. Since this is for altivec specific code, only support the altivec 694243830Sdim// types (v16i8, v8i16, v4i32, and v4f32). 695243830Sdimstatic unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { 696243830Sdim switch (VecVT) { 697243830Sdim case MVT::v16i8: 698243830Sdim return PPC::VCMPEQUB; 699243830Sdim case MVT::v8i16: 700243830Sdim return PPC::VCMPEQUH; 701243830Sdim case MVT::v4i32: 702243830Sdim return PPC::VCMPEQUW; 703243830Sdim case MVT::v4f32: 704243830Sdim return PPC::VCMPEQFP; 705243830Sdim default: 706243830Sdim llvm_unreachable("Invalid integer vector compare condition"); 707243830Sdim } 708243830Sdim} 709243830Sdim 710243830Sdim 711202375SrdivackySDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { 712263508Sdim SDLoc dl(N); 713193323Sed unsigned Imm; 714193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 715224145Sdim EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 716224145Sdim bool isPPC64 = (PtrVT == MVT::i64); 717224145Sdim 718193323Sed if (isInt32Immediate(N->getOperand(1), Imm)) { 719193323Sed // We can codegen setcc op, imm very efficiently compared to a brcond. 720193323Sed // Check for those cases here. 721193323Sed // setcc op, 0 722193323Sed if (Imm == 0) { 723193323Sed SDValue Op = N->getOperand(0); 724193323Sed switch (CC) { 725193323Sed default: break; 726193323Sed case ISD::SETEQ: { 727198090Srdivacky Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 728193323Sed SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 729193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 730193323Sed } 731193323Sed case ISD::SETNE: { 732224145Sdim if (isPPC64) break; 733193323Sed SDValue AD = 734218893Sdim SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 735198090Srdivacky Op, getI32Imm(~0U)), 0); 736218893Sdim return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 737193323Sed AD.getValue(1)); 738193323Sed } 739193323Sed case ISD::SETLT: { 740193323Sed SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 741193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 742193323Sed } 743193323Sed case ISD::SETGT: { 744193323Sed SDValue T = 745198090Srdivacky SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); 746198090Srdivacky T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 747193323Sed SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 748193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 749193323Sed } 750193323Sed } 751193323Sed } else if (Imm == ~0U) { // setcc op, -1 752193323Sed SDValue Op = N->getOperand(0); 753193323Sed switch (CC) { 754193323Sed default: break; 755193323Sed case ISD::SETEQ: 756224145Sdim if (isPPC64) break; 757218893Sdim Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 758198090Srdivacky Op, getI32Imm(1)), 0); 759218893Sdim return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 760218893Sdim SDValue(CurDAG->getMachineNode(PPC::LI, dl, 761198090Srdivacky MVT::i32, 762198090Srdivacky getI32Imm(0)), 0), 763193323Sed Op.getValue(1)); 764193323Sed case ISD::SETNE: { 765224145Sdim if (isPPC64) break; 766198090Srdivacky Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 767218893Sdim SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 768198090Srdivacky Op, getI32Imm(~0U)); 769193323Sed return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 770193323Sed Op, SDValue(AD, 1)); 771193323Sed } 772193323Sed case ISD::SETLT: { 773198090Srdivacky SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 774198090Srdivacky getI32Imm(1)), 0); 775198090Srdivacky SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, 776198090Srdivacky Op), 0); 777193323Sed SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 778193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 779193323Sed } 780193323Sed case ISD::SETGT: { 781193323Sed SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 782251662Sdim Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 783193323Sed 0); 784218893Sdim return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 785193323Sed getI32Imm(1)); 786193323Sed } 787193323Sed } 788193323Sed } 789193323Sed } 790218893Sdim 791243830Sdim SDValue LHS = N->getOperand(0); 792243830Sdim SDValue RHS = N->getOperand(1); 793243830Sdim 794243830Sdim // Altivec Vector compare instructions do not set any CR register by default and 795243830Sdim // vector compare operations return the same type as the operands. 796243830Sdim if (LHS.getValueType().isVector()) { 797243830Sdim EVT VecVT = LHS.getValueType(); 798243830Sdim MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; 799243830Sdim unsigned int VCmpInst = getVCmpInst(VT, CC); 800243830Sdim 801243830Sdim switch (CC) { 802243830Sdim case ISD::SETEQ: 803243830Sdim case ISD::SETOEQ: 804243830Sdim case ISD::SETUEQ: 805243830Sdim return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 806243830Sdim case ISD::SETNE: 807243830Sdim case ISD::SETONE: 808243830Sdim case ISD::SETUNE: { 809243830Sdim SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 810243830Sdim return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); 811243830Sdim } 812243830Sdim case ISD::SETLT: 813243830Sdim case ISD::SETOLT: 814243830Sdim case ISD::SETULT: 815243830Sdim return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); 816243830Sdim case ISD::SETGT: 817243830Sdim case ISD::SETOGT: 818243830Sdim case ISD::SETUGT: 819243830Sdim return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 820243830Sdim case ISD::SETGE: 821243830Sdim case ISD::SETOGE: 822243830Sdim case ISD::SETUGE: { 823243830Sdim // Small optimization: Altivec provides a 'Vector Compare Greater Than 824243830Sdim // or Equal To' instruction (vcmpgefp), so in this case there is no 825243830Sdim // need for extra logic for the equal compare. 826243830Sdim if (VecVT.getSimpleVT().isFloatingPoint()) { 827243830Sdim return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 828243830Sdim } else { 829243830Sdim SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 830243830Sdim unsigned int VCmpEQInst = getVCmpEQInst(VT); 831243830Sdim SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 832243830Sdim return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); 833243830Sdim } 834243830Sdim } 835243830Sdim case ISD::SETLE: 836243830Sdim case ISD::SETOLE: 837243830Sdim case ISD::SETULE: { 838243830Sdim SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); 839243830Sdim unsigned int VCmpEQInst = getVCmpEQInst(VT); 840243830Sdim SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 841243830Sdim return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); 842243830Sdim } 843243830Sdim default: 844243830Sdim llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); 845243830Sdim } 846243830Sdim } 847243830Sdim 848193323Sed bool Inv; 849263508Sdim unsigned Idx = getCRIdxForSetCC(CC, Inv); 850243830Sdim SDValue CCReg = SelectCC(LHS, RHS, CC, dl); 851193323Sed SDValue IntCR; 852218893Sdim 853193323Sed // Force the ccreg into CR7. 854193323Sed SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 855218893Sdim 856193323Sed SDValue InFlag(0, 0); // Null incoming flag value. 857218893Sdim CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 858193323Sed InFlag).getValue(1); 859218893Sdim 860263508Sdim IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 861263508Sdim CCReg), 0); 862218893Sdim 863193323Sed SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 864193323Sed getI32Imm(31), getI32Imm(31) }; 865263508Sdim if (!Inv) 866193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 867193323Sed 868193323Sed // Get the specified bit. 869193323Sed SDValue Tmp = 870251662Sdim SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 871263508Sdim return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 872193323Sed} 873193323Sed 874193323Sed 875193323Sed// Select - Convert the specified operand from a target-independent to a 876193323Sed// target-specific node if it hasn't already been changed. 877202375SrdivackySDNode *PPCDAGToDAGISel::Select(SDNode *N) { 878263508Sdim SDLoc dl(N); 879255804Sdim if (N->isMachineOpcode()) { 880255804Sdim N->setNodeId(-1); 881193323Sed return NULL; // Already selected. 882255804Sdim } 883193323Sed 884193323Sed switch (N->getOpcode()) { 885193323Sed default: break; 886218893Sdim 887193323Sed case ISD::Constant: { 888193323Sed if (N->getValueType(0) == MVT::i64) { 889193323Sed // Get 64 bit value. 890193323Sed int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 891193323Sed // Assume no remaining bits. 892193323Sed unsigned Remainder = 0; 893193323Sed // Assume no shift required. 894193323Sed unsigned Shift = 0; 895218893Sdim 896193323Sed // If it can't be represented as a 32 bit value. 897206083Srdivacky if (!isInt<32>(Imm)) { 898263508Sdim Shift = countTrailingZeros<uint64_t>(Imm); 899193323Sed int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 900218893Sdim 901193323Sed // If the shifted value fits 32 bits. 902206083Srdivacky if (isInt<32>(ImmSh)) { 903193323Sed // Go with the shifted value. 904193323Sed Imm = ImmSh; 905193323Sed } else { 906193323Sed // Still stuck with a 64 bit value. 907193323Sed Remainder = Imm; 908193323Sed Shift = 32; 909193323Sed Imm >>= 32; 910193323Sed } 911193323Sed } 912218893Sdim 913193323Sed // Intermediate operand. 914193323Sed SDNode *Result; 915193323Sed 916193323Sed // Handle first 32 bits. 917193323Sed unsigned Lo = Imm & 0xFFFF; 918193323Sed unsigned Hi = (Imm >> 16) & 0xFFFF; 919218893Sdim 920193323Sed // Simple value. 921206083Srdivacky if (isInt<16>(Imm)) { 922193323Sed // Just the Lo bits. 923198090Srdivacky Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 924193323Sed } else if (Lo) { 925193323Sed // Handle the Hi bits. 926193323Sed unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 927198090Srdivacky Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 928193323Sed // And Lo bits. 929198090Srdivacky Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 930198090Srdivacky SDValue(Result, 0), getI32Imm(Lo)); 931193323Sed } else { 932193323Sed // Just the Hi bits. 933198090Srdivacky Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 934193323Sed } 935218893Sdim 936193323Sed // If no shift, we're done. 937193323Sed if (!Shift) return Result; 938193323Sed 939193323Sed // Shift for next step if the upper 32-bits were not zero. 940193323Sed if (Imm) { 941198090Srdivacky Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, 942198090Srdivacky SDValue(Result, 0), 943198090Srdivacky getI32Imm(Shift), 944198090Srdivacky getI32Imm(63 - Shift)); 945193323Sed } 946193323Sed 947193323Sed // Add in the last bits as required. 948193323Sed if ((Hi = (Remainder >> 16) & 0xFFFF)) { 949198090Srdivacky Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, 950198090Srdivacky SDValue(Result, 0), getI32Imm(Hi)); 951218893Sdim } 952193323Sed if ((Lo = Remainder & 0xFFFF)) { 953198090Srdivacky Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 954198090Srdivacky SDValue(Result, 0), getI32Imm(Lo)); 955193323Sed } 956218893Sdim 957193323Sed return Result; 958193323Sed } 959193323Sed break; 960193323Sed } 961218893Sdim 962193323Sed case ISD::SETCC: 963202375Srdivacky return SelectSETCC(N); 964193323Sed case PPCISD::GlobalBaseReg: 965193323Sed return getGlobalBaseReg(); 966218893Sdim 967193323Sed case ISD::FrameIndex: { 968193323Sed int FI = cast<FrameIndexSDNode>(N)->getIndex(); 969202375Srdivacky SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); 970202375Srdivacky unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 971193323Sed if (N->hasOneUse()) 972202375Srdivacky return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, 973193323Sed getSmallIPtrImm(0)); 974202375Srdivacky return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, 975198090Srdivacky getSmallIPtrImm(0)); 976193323Sed } 977193323Sed 978263508Sdim case PPCISD::MFOCRF: { 979193323Sed SDValue InFlag = N->getOperand(1); 980263508Sdim return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, 981263508Sdim N->getOperand(0), InFlag); 982193323Sed } 983218893Sdim 984193323Sed case ISD::SDIV: { 985193323Sed // FIXME: since this depends on the setting of the carry flag from the srawi 986193323Sed // we should really be making notes about that for the scheduler. 987218893Sdim // FIXME: It sure would be nice if we could cheaply recognize the 988193323Sed // srl/add/sra pattern the dag combiner will generate for this as 989193323Sed // sra/addze rather than having to handle sdiv ourselves. oh well. 990193323Sed unsigned Imm; 991193323Sed if (isInt32Immediate(N->getOperand(1), Imm)) { 992193323Sed SDValue N0 = N->getOperand(0); 993193323Sed if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 994193323Sed SDNode *Op = 995218893Sdim CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 996198090Srdivacky N0, getI32Imm(Log2_32(Imm))); 997218893Sdim return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 998193323Sed SDValue(Op, 0), SDValue(Op, 1)); 999193323Sed } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 1000193323Sed SDNode *Op = 1001218893Sdim CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 1002198090Srdivacky N0, getI32Imm(Log2_32(-Imm))); 1003193323Sed SDValue PT = 1004198090Srdivacky SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, 1005198090Srdivacky SDValue(Op, 0), SDValue(Op, 1)), 1006193323Sed 0); 1007193323Sed return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 1008193323Sed } 1009193323Sed } 1010218893Sdim 1011193323Sed // Other cases are autogenerated. 1012193323Sed break; 1013193323Sed } 1014218893Sdim 1015193323Sed case ISD::LOAD: { 1016193323Sed // Handle preincrement loads. 1017202375Srdivacky LoadSDNode *LD = cast<LoadSDNode>(N); 1018198090Srdivacky EVT LoadedVT = LD->getMemoryVT(); 1019218893Sdim 1020193323Sed // Normal loads are handled by code generated from the .td file. 1021193323Sed if (LD->getAddressingMode() != ISD::PRE_INC) 1022193323Sed break; 1023218893Sdim 1024193323Sed SDValue Offset = LD->getOffset(); 1025249423Sdim if (Offset.getOpcode() == ISD::TargetConstant || 1026193323Sed Offset.getOpcode() == ISD::TargetGlobalAddress) { 1027218893Sdim 1028193323Sed unsigned Opcode; 1029193323Sed bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1030193323Sed if (LD->getValueType(0) != MVT::i64) { 1031193323Sed // Handle PPC32 integer and normal FP loads. 1032193323Sed assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1033198090Srdivacky switch (LoadedVT.getSimpleVT().SimpleTy) { 1034198090Srdivacky default: llvm_unreachable("Invalid PPC load type!"); 1035193323Sed case MVT::f64: Opcode = PPC::LFDU; break; 1036193323Sed case MVT::f32: Opcode = PPC::LFSU; break; 1037193323Sed case MVT::i32: Opcode = PPC::LWZU; break; 1038193323Sed case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 1039193323Sed case MVT::i1: 1040193323Sed case MVT::i8: Opcode = PPC::LBZU; break; 1041193323Sed } 1042193323Sed } else { 1043193323Sed assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1044193323Sed assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1045198090Srdivacky switch (LoadedVT.getSimpleVT().SimpleTy) { 1046198090Srdivacky default: llvm_unreachable("Invalid PPC load type!"); 1047193323Sed case MVT::i64: Opcode = PPC::LDU; break; 1048193323Sed case MVT::i32: Opcode = PPC::LWZU8; break; 1049193323Sed case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 1050193323Sed case MVT::i1: 1051193323Sed case MVT::i8: Opcode = PPC::LBZU8; break; 1052193323Sed } 1053193323Sed } 1054218893Sdim 1055193323Sed SDValue Chain = LD->getChain(); 1056193323Sed SDValue Base = LD->getBasePtr(); 1057193323Sed SDValue Ops[] = { Offset, Base, Chain }; 1058198090Srdivacky return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1059198090Srdivacky PPCLowering.getPointerTy(), 1060251662Sdim MVT::Other, Ops); 1061193323Sed } else { 1062239462Sdim unsigned Opcode; 1063239462Sdim bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1064239462Sdim if (LD->getValueType(0) != MVT::i64) { 1065239462Sdim // Handle PPC32 integer and normal FP loads. 1066239462Sdim assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1067239462Sdim switch (LoadedVT.getSimpleVT().SimpleTy) { 1068239462Sdim default: llvm_unreachable("Invalid PPC load type!"); 1069239462Sdim case MVT::f64: Opcode = PPC::LFDUX; break; 1070239462Sdim case MVT::f32: Opcode = PPC::LFSUX; break; 1071239462Sdim case MVT::i32: Opcode = PPC::LWZUX; break; 1072239462Sdim case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 1073239462Sdim case MVT::i1: 1074239462Sdim case MVT::i8: Opcode = PPC::LBZUX; break; 1075239462Sdim } 1076239462Sdim } else { 1077239462Sdim assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1078239462Sdim assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && 1079239462Sdim "Invalid sext update load"); 1080239462Sdim switch (LoadedVT.getSimpleVT().SimpleTy) { 1081239462Sdim default: llvm_unreachable("Invalid PPC load type!"); 1082239462Sdim case MVT::i64: Opcode = PPC::LDUX; break; 1083239462Sdim case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; 1084239462Sdim case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; 1085239462Sdim case MVT::i1: 1086239462Sdim case MVT::i8: Opcode = PPC::LBZUX8; break; 1087239462Sdim } 1088239462Sdim } 1089239462Sdim 1090239462Sdim SDValue Chain = LD->getChain(); 1091239462Sdim SDValue Base = LD->getBasePtr(); 1092249423Sdim SDValue Ops[] = { Base, Offset, Chain }; 1093239462Sdim return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1094239462Sdim PPCLowering.getPointerTy(), 1095251662Sdim MVT::Other, Ops); 1096193323Sed } 1097193323Sed } 1098218893Sdim 1099193323Sed case ISD::AND: { 1100193323Sed unsigned Imm, Imm2, SH, MB, ME; 1101243830Sdim uint64_t Imm64; 1102193323Sed 1103193323Sed // If this is an and of a value rotated between 0 and 31 bits and then and'd 1104193323Sed // with a mask, emit rlwinm 1105193323Sed if (isInt32Immediate(N->getOperand(1), Imm) && 1106193323Sed isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 1107193323Sed SDValue Val = N->getOperand(0).getOperand(0); 1108193323Sed SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1109193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1110193323Sed } 1111193323Sed // If this is just a masked value where the input is not handled above, and 1112193323Sed // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 1113193323Sed if (isInt32Immediate(N->getOperand(1), Imm) && 1114218893Sdim isRunOfOnes(Imm, MB, ME) && 1115193323Sed N->getOperand(0).getOpcode() != ISD::ROTL) { 1116193323Sed SDValue Val = N->getOperand(0); 1117193323Sed SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 1118193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1119193323Sed } 1120243830Sdim // If this is a 64-bit zero-extension mask, emit rldicl. 1121243830Sdim if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && 1122243830Sdim isMask_64(Imm64)) { 1123243830Sdim SDValue Val = N->getOperand(0); 1124243830Sdim MB = 64 - CountTrailingOnes_64(Imm64); 1125243830Sdim SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; 1126243830Sdim return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); 1127243830Sdim } 1128193323Sed // AND X, 0 -> 0, not "rlwinm 32". 1129193323Sed if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 1130193323Sed ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1131193323Sed return NULL; 1132193323Sed } 1133193323Sed // ISD::OR doesn't get all the bitfield insertion fun. 1134193323Sed // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1135218893Sdim if (isInt32Immediate(N->getOperand(1), Imm) && 1136193323Sed N->getOperand(0).getOpcode() == ISD::OR && 1137193323Sed isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1138193323Sed unsigned MB, ME; 1139193323Sed Imm = ~(Imm^Imm2); 1140193323Sed if (isRunOfOnes(Imm, MB, ME)) { 1141193323Sed SDValue Ops[] = { N->getOperand(0).getOperand(0), 1142193323Sed N->getOperand(0).getOperand(1), 1143193323Sed getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1144251662Sdim return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 1145193323Sed } 1146193323Sed } 1147218893Sdim 1148193323Sed // Other cases are autogenerated. 1149193323Sed break; 1150193323Sed } 1151193323Sed case ISD::OR: 1152193323Sed if (N->getValueType(0) == MVT::i32) 1153193323Sed if (SDNode *I = SelectBitfieldInsert(N)) 1154193323Sed return I; 1155218893Sdim 1156193323Sed // Other cases are autogenerated. 1157193323Sed break; 1158193323Sed case ISD::SHL: { 1159193323Sed unsigned Imm, SH, MB, ME; 1160193323Sed if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1161193323Sed isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1162193323Sed SDValue Ops[] = { N->getOperand(0).getOperand(0), 1163193323Sed getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1164193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1165193323Sed } 1166218893Sdim 1167193323Sed // Other cases are autogenerated. 1168193323Sed break; 1169193323Sed } 1170193323Sed case ISD::SRL: { 1171193323Sed unsigned Imm, SH, MB, ME; 1172193323Sed if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1173218893Sdim isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1174193323Sed SDValue Ops[] = { N->getOperand(0).getOperand(0), 1175193323Sed getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1176193323Sed return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1177193323Sed } 1178218893Sdim 1179193323Sed // Other cases are autogenerated. 1180193323Sed break; 1181193323Sed } 1182193323Sed case ISD::SELECT_CC: { 1183193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1184224145Sdim EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 1185224145Sdim bool isPPC64 = (PtrVT == MVT::i64); 1186218893Sdim 1187193323Sed // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1188224145Sdim if (!isPPC64) 1189224145Sdim if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1190224145Sdim if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1191224145Sdim if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1192224145Sdim if (N1C->isNullValue() && N3C->isNullValue() && 1193224145Sdim N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1194224145Sdim // FIXME: Implement this optzn for PPC64. 1195224145Sdim N->getValueType(0) == MVT::i32) { 1196224145Sdim SDNode *Tmp = 1197224145Sdim CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 1198224145Sdim N->getOperand(0), getI32Imm(~0U)); 1199224145Sdim return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1200224145Sdim SDValue(Tmp, 0), N->getOperand(0), 1201224145Sdim SDValue(Tmp, 1)); 1202224145Sdim } 1203193323Sed 1204193323Sed SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1205193323Sed unsigned BROpc = getPredicateForSetCC(CC); 1206193323Sed 1207193323Sed unsigned SelectCCOp; 1208193323Sed if (N->getValueType(0) == MVT::i32) 1209193323Sed SelectCCOp = PPC::SELECT_CC_I4; 1210193323Sed else if (N->getValueType(0) == MVT::i64) 1211193323Sed SelectCCOp = PPC::SELECT_CC_I8; 1212193323Sed else if (N->getValueType(0) == MVT::f32) 1213193323Sed SelectCCOp = PPC::SELECT_CC_F4; 1214193323Sed else if (N->getValueType(0) == MVT::f64) 1215193323Sed SelectCCOp = PPC::SELECT_CC_F8; 1216193323Sed else 1217193323Sed SelectCCOp = PPC::SELECT_CC_VRRC; 1218193323Sed 1219193323Sed SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1220193323Sed getI32Imm(BROpc) }; 1221193323Sed return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1222193323Sed } 1223263508Sdim case PPCISD::BDNZ: 1224263508Sdim case PPCISD::BDZ: { 1225263508Sdim bool IsPPC64 = PPCSubTarget.isPPC64(); 1226263508Sdim SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; 1227263508Sdim return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ? 1228263508Sdim (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 1229263508Sdim (IsPPC64 ? PPC::BDZ8 : PPC::BDZ), 1230263508Sdim MVT::Other, Ops, 2); 1231263508Sdim } 1232193323Sed case PPCISD::COND_BRANCH: { 1233193323Sed // Op #0 is the Chain. 1234193323Sed // Op #1 is the PPC::PRED_* number. 1235193323Sed // Op #2 is the CR# 1236193323Sed // Op #3 is the Dest MBB 1237193323Sed // Op #4 is the Flag. 1238193323Sed // Prevent PPC::PRED_* from being selected into LI. 1239193323Sed SDValue Pred = 1240193323Sed getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1241193323Sed SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1242193323Sed N->getOperand(0), N->getOperand(4) }; 1243193323Sed return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1244193323Sed } 1245193323Sed case ISD::BR_CC: { 1246193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1247193323Sed SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1248218893Sdim SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1249193323Sed N->getOperand(4), N->getOperand(0) }; 1250193323Sed return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1251193323Sed } 1252193323Sed case ISD::BRIND: { 1253193323Sed // FIXME: Should custom lower this. 1254193323Sed SDValue Chain = N->getOperand(0); 1255193323Sed SDValue Target = N->getOperand(1); 1256193323Sed unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1257223017Sdim unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; 1258234353Sdim Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, 1259198090Srdivacky Chain), 0); 1260223017Sdim return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); 1261193323Sed } 1262249423Sdim case PPCISD::TOC_ENTRY: { 1263249423Sdim assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); 1264249423Sdim 1265249423Sdim // For medium and large code model, we generate two instructions as 1266249423Sdim // described below. Otherwise we allow SelectCodeCommon to handle this, 1267249423Sdim // selecting one of LDtoc, LDtocJTI, and LDtocCPT. 1268249423Sdim CodeModel::Model CModel = TM.getCodeModel(); 1269249423Sdim if (CModel != CodeModel::Medium && CModel != CodeModel::Large) 1270249423Sdim break; 1271249423Sdim 1272249423Sdim // The first source operand is a TargetGlobalAddress or a 1273249423Sdim // TargetJumpTable. If it is an externally defined symbol, a symbol 1274249423Sdim // with common linkage, a function address, or a jump table address, 1275249423Sdim // or if we are generating code for large code model, we generate: 1276249423Sdim // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>)) 1277249423Sdim // Otherwise we generate: 1278249423Sdim // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>) 1279249423Sdim SDValue GA = N->getOperand(0); 1280249423Sdim SDValue TOCbase = N->getOperand(1); 1281249423Sdim SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, 1282249423Sdim TOCbase, GA); 1283249423Sdim 1284249423Sdim if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large) 1285249423Sdim return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1286249423Sdim SDValue(Tmp, 0)); 1287249423Sdim 1288249423Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) { 1289249423Sdim const GlobalValue *GValue = G->getGlobal(); 1290249423Sdim const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue); 1291249423Sdim const GlobalValue *RealGValue = GAlias ? 1292249423Sdim GAlias->resolveAliasedGlobal(false) : GValue; 1293249423Sdim const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue); 1294249423Sdim assert((GVar || isa<Function>(RealGValue)) && 1295249423Sdim "Unexpected global value subclass!"); 1296249423Sdim 1297249423Sdim // An external variable is one without an initializer. For these, 1298249423Sdim // for variables with common linkage, and for Functions, generate 1299249423Sdim // the LDtocL form. 1300249423Sdim if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() || 1301249423Sdim RealGValue->hasAvailableExternallyLinkage()) 1302249423Sdim return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1303249423Sdim SDValue(Tmp, 0)); 1304249423Sdim } 1305249423Sdim 1306249423Sdim return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, 1307249423Sdim SDValue(Tmp, 0), GA); 1308193323Sed } 1309249423Sdim case PPCISD::VADD_SPLAT: { 1310249423Sdim // This expands into one of three sequences, depending on whether 1311249423Sdim // the first operand is odd or even, positive or negative. 1312249423Sdim assert(isa<ConstantSDNode>(N->getOperand(0)) && 1313249423Sdim isa<ConstantSDNode>(N->getOperand(1)) && 1314249423Sdim "Invalid operand on VADD_SPLAT!"); 1315218893Sdim 1316249423Sdim int Elt = N->getConstantOperandVal(0); 1317249423Sdim int EltSize = N->getConstantOperandVal(1); 1318249423Sdim unsigned Opc1, Opc2, Opc3; 1319249423Sdim EVT VT; 1320249423Sdim 1321249423Sdim if (EltSize == 1) { 1322249423Sdim Opc1 = PPC::VSPLTISB; 1323249423Sdim Opc2 = PPC::VADDUBM; 1324249423Sdim Opc3 = PPC::VSUBUBM; 1325249423Sdim VT = MVT::v16i8; 1326249423Sdim } else if (EltSize == 2) { 1327249423Sdim Opc1 = PPC::VSPLTISH; 1328249423Sdim Opc2 = PPC::VADDUHM; 1329249423Sdim Opc3 = PPC::VSUBUHM; 1330249423Sdim VT = MVT::v8i16; 1331249423Sdim } else { 1332249423Sdim assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); 1333249423Sdim Opc1 = PPC::VSPLTISW; 1334249423Sdim Opc2 = PPC::VADDUWM; 1335249423Sdim Opc3 = PPC::VSUBUWM; 1336249423Sdim VT = MVT::v4i32; 1337249423Sdim } 1338249423Sdim 1339249423Sdim if ((Elt & 1) == 0) { 1340249423Sdim // Elt is even, in the range [-32,-18] + [16,30]. 1341249423Sdim // 1342249423Sdim // Convert: VADD_SPLAT elt, size 1343249423Sdim // Into: tmp = VSPLTIS[BHW] elt 1344249423Sdim // VADDU[BHW]M tmp, tmp 1345249423Sdim // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 1346249423Sdim SDValue EltVal = getI32Imm(Elt >> 1); 1347249423Sdim SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1348249423Sdim SDValue TmpVal = SDValue(Tmp, 0); 1349249423Sdim return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); 1350249423Sdim 1351249423Sdim } else if (Elt > 0) { 1352249423Sdim // Elt is odd and positive, in the range [17,31]. 1353249423Sdim // 1354249423Sdim // Convert: VADD_SPLAT elt, size 1355249423Sdim // Into: tmp1 = VSPLTIS[BHW] elt-16 1356249423Sdim // tmp2 = VSPLTIS[BHW] -16 1357249423Sdim // VSUBU[BHW]M tmp1, tmp2 1358249423Sdim SDValue EltVal = getI32Imm(Elt - 16); 1359249423Sdim SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1360249423Sdim EltVal = getI32Imm(-16); 1361249423Sdim SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1362249423Sdim return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), 1363249423Sdim SDValue(Tmp2, 0)); 1364249423Sdim 1365249423Sdim } else { 1366249423Sdim // Elt is odd and negative, in the range [-31,-17]. 1367249423Sdim // 1368249423Sdim // Convert: VADD_SPLAT elt, size 1369249423Sdim // Into: tmp1 = VSPLTIS[BHW] elt+16 1370249423Sdim // tmp2 = VSPLTIS[BHW] -16 1371249423Sdim // VADDU[BHW]M tmp1, tmp2 1372249423Sdim SDValue EltVal = getI32Imm(Elt + 16); 1373249423Sdim SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1374249423Sdim EltVal = getI32Imm(-16); 1375249423Sdim SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1376249423Sdim return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), 1377249423Sdim SDValue(Tmp2, 0)); 1378249423Sdim } 1379249423Sdim } 1380249423Sdim } 1381249423Sdim 1382202375Srdivacky return SelectCode(N); 1383193323Sed} 1384193323Sed 1385249423Sdim/// PostProcessISelDAG - Perform some late peephole optimizations 1386249423Sdim/// on the DAG representation. 1387249423Sdimvoid PPCDAGToDAGISel::PostprocessISelDAG() { 1388193323Sed 1389249423Sdim // Skip peepholes at -O0. 1390249423Sdim if (TM.getOptLevel() == CodeGenOpt::None) 1391249423Sdim return; 1392193323Sed 1393249423Sdim // These optimizations are currently supported only for 64-bit SVR4. 1394249423Sdim if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64()) 1395249423Sdim return; 1396249423Sdim 1397249423Sdim SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); 1398249423Sdim ++Position; 1399249423Sdim 1400249423Sdim while (Position != CurDAG->allnodes_begin()) { 1401249423Sdim SDNode *N = --Position; 1402249423Sdim // Skip dead nodes and any non-machine opcodes. 1403249423Sdim if (N->use_empty() || !N->isMachineOpcode()) 1404249423Sdim continue; 1405249423Sdim 1406249423Sdim unsigned FirstOp; 1407249423Sdim unsigned StorageOpcode = N->getMachineOpcode(); 1408249423Sdim 1409249423Sdim switch (StorageOpcode) { 1410249423Sdim default: continue; 1411249423Sdim 1412249423Sdim case PPC::LBZ: 1413249423Sdim case PPC::LBZ8: 1414249423Sdim case PPC::LD: 1415249423Sdim case PPC::LFD: 1416249423Sdim case PPC::LFS: 1417249423Sdim case PPC::LHA: 1418249423Sdim case PPC::LHA8: 1419249423Sdim case PPC::LHZ: 1420249423Sdim case PPC::LHZ8: 1421249423Sdim case PPC::LWA: 1422249423Sdim case PPC::LWZ: 1423249423Sdim case PPC::LWZ8: 1424249423Sdim FirstOp = 0; 1425249423Sdim break; 1426249423Sdim 1427249423Sdim case PPC::STB: 1428249423Sdim case PPC::STB8: 1429249423Sdim case PPC::STD: 1430249423Sdim case PPC::STFD: 1431249423Sdim case PPC::STFS: 1432249423Sdim case PPC::STH: 1433249423Sdim case PPC::STH8: 1434249423Sdim case PPC::STW: 1435249423Sdim case PPC::STW8: 1436249423Sdim FirstOp = 1; 1437249423Sdim break; 1438249423Sdim } 1439249423Sdim 1440249423Sdim // If this is a load or store with a zero offset, we may be able to 1441249423Sdim // fold an add-immediate into the memory operation. 1442249423Sdim if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) || 1443249423Sdim N->getConstantOperandVal(FirstOp) != 0) 1444249423Sdim continue; 1445249423Sdim 1446249423Sdim SDValue Base = N->getOperand(FirstOp + 1); 1447249423Sdim if (!Base.isMachineOpcode()) 1448249423Sdim continue; 1449249423Sdim 1450249423Sdim unsigned Flags = 0; 1451249423Sdim bool ReplaceFlags = true; 1452249423Sdim 1453249423Sdim // When the feeding operation is an add-immediate of some sort, 1454249423Sdim // determine whether we need to add relocation information to the 1455249423Sdim // target flags on the immediate operand when we fold it into the 1456249423Sdim // load instruction. 1457249423Sdim // 1458249423Sdim // For something like ADDItocL, the relocation information is 1459249423Sdim // inferred from the opcode; when we process it in the AsmPrinter, 1460249423Sdim // we add the necessary relocation there. A load, though, can receive 1461249423Sdim // relocation from various flavors of ADDIxxx, so we need to carry 1462249423Sdim // the relocation information in the target flags. 1463249423Sdim switch (Base.getMachineOpcode()) { 1464249423Sdim default: continue; 1465249423Sdim 1466249423Sdim case PPC::ADDI8: 1467249423Sdim case PPC::ADDI: 1468249423Sdim // In some cases (such as TLS) the relocation information 1469249423Sdim // is already in place on the operand, so copying the operand 1470249423Sdim // is sufficient. 1471249423Sdim ReplaceFlags = false; 1472249423Sdim // For these cases, the immediate may not be divisible by 4, in 1473249423Sdim // which case the fold is illegal for DS-form instructions. (The 1474249423Sdim // other cases provide aligned addresses and are always safe.) 1475249423Sdim if ((StorageOpcode == PPC::LWA || 1476249423Sdim StorageOpcode == PPC::LD || 1477249423Sdim StorageOpcode == PPC::STD) && 1478249423Sdim (!isa<ConstantSDNode>(Base.getOperand(1)) || 1479249423Sdim Base.getConstantOperandVal(1) % 4 != 0)) 1480249423Sdim continue; 1481249423Sdim break; 1482249423Sdim case PPC::ADDIdtprelL: 1483263508Sdim Flags = PPCII::MO_DTPREL_LO; 1484249423Sdim break; 1485249423Sdim case PPC::ADDItlsldL: 1486263508Sdim Flags = PPCII::MO_TLSLD_LO; 1487249423Sdim break; 1488249423Sdim case PPC::ADDItocL: 1489263508Sdim Flags = PPCII::MO_TOC_LO; 1490249423Sdim break; 1491249423Sdim } 1492249423Sdim 1493249423Sdim // We found an opportunity. Reverse the operands from the add 1494249423Sdim // immediate and substitute them into the load or store. If 1495249423Sdim // needed, update the target flags for the immediate operand to 1496249423Sdim // reflect the necessary relocation information. 1497249423Sdim DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); 1498249423Sdim DEBUG(Base->dump(CurDAG)); 1499249423Sdim DEBUG(dbgs() << "\nN: "); 1500249423Sdim DEBUG(N->dump(CurDAG)); 1501249423Sdim DEBUG(dbgs() << "\n"); 1502249423Sdim 1503249423Sdim SDValue ImmOpnd = Base.getOperand(1); 1504249423Sdim 1505249423Sdim // If the relocation information isn't already present on the 1506249423Sdim // immediate operand, add it now. 1507249423Sdim if (ReplaceFlags) { 1508249423Sdim if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { 1509263508Sdim SDLoc dl(GA); 1510249423Sdim const GlobalValue *GV = GA->getGlobal(); 1511263508Sdim // We can't perform this optimization for data whose alignment 1512263508Sdim // is insufficient for the instruction encoding. 1513263508Sdim if (GV->getAlignment() < 4 && 1514263508Sdim (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || 1515263508Sdim StorageOpcode == PPC::LWA)) { 1516263508Sdim DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); 1517263508Sdim continue; 1518263508Sdim } 1519249423Sdim ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); 1520249423Sdim } else if (ConstantPoolSDNode *CP = 1521249423Sdim dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { 1522249423Sdim const Constant *C = CP->getConstVal(); 1523249423Sdim ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, 1524249423Sdim CP->getAlignment(), 1525249423Sdim 0, Flags); 1526249423Sdim } 1527249423Sdim } 1528249423Sdim 1529249423Sdim if (FirstOp == 1) // Store 1530249423Sdim (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, 1531249423Sdim Base.getOperand(0), N->getOperand(3)); 1532249423Sdim else // Load 1533249423Sdim (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0), 1534249423Sdim N->getOperand(2)); 1535249423Sdim 1536249423Sdim // The add-immediate may now be dead, in which case remove it. 1537249423Sdim if (Base.getNode()->use_empty()) 1538249423Sdim CurDAG->RemoveDeadNode(Base.getNode()); 1539249423Sdim } 1540249423Sdim} 1541249423Sdim 1542249423Sdim 1543218893Sdim/// createPPCISelDag - This pass converts a legalized DAG into a 1544193323Sed/// PowerPC-specific DAG, ready for instruction scheduling. 1545193323Sed/// 1546193323SedFunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { 1547193323Sed return new PPCDAGToDAGISel(TM); 1548193323Sed} 1549193323Sed 1550249423Sdimstatic void initializePassOnce(PassRegistry &Registry) { 1551249423Sdim const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection"; 1552249423Sdim PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0, 1553249423Sdim false, false); 1554249423Sdim Registry.registerPass(*PI, true); 1555249423Sdim} 1556249423Sdim 1557249423Sdimvoid llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) { 1558249423Sdim CALL_ONCE_INITIALIZATION(initializePassOnce); 1559249423Sdim} 1560249423Sdim 1561