PPCFrameLowering.h revision 256281 
1//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef POWERPC_FRAMEINFO_H
14#define POWERPC_FRAMEINFO_H
15
16#include "PPC.h"
17#include "PPCSubtarget.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/Target/TargetFrameLowering.h"
20#include "llvm/Target/TargetMachine.h"
21
22namespace llvm {
23  class PPCSubtarget;
24
25class PPCFrameLowering: public TargetFrameLowering {
26  const PPCSubtarget &Subtarget;
27
28public:
29  PPCFrameLowering(const PPCSubtarget &sti)
30    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
31        (sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0),
32      Subtarget(sti) {
33  }
34
35  unsigned determineFrameLayout(MachineFunction &MF,
36                                bool UpdateMF = true,
37                                bool UseEstimate = false) const;
38
39  /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
40  /// the function.
41  void emitPrologue(MachineFunction &MF) const;
42  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
43
44  bool hasFP(const MachineFunction &MF) const;
45  bool needsFP(const MachineFunction &MF) const;
46  void replaceFPWithRealFP(MachineFunction &MF) const;
47
48  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
49                                            RegScavenger *RS = NULL) const;
50  void processFunctionBeforeFrameFinalized(MachineFunction &MF,
51                                       RegScavenger *RS = NULL) const;
52  void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
53
54  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
55                                 MachineBasicBlock::iterator MI,
56                                 const std::vector<CalleeSavedInfo> &CSI,
57                                 const TargetRegisterInfo *TRI) const;
58
59  void eliminateCallFramePseudoInstr(MachineFunction &MF,
60                                     MachineBasicBlock &MBB,
61                                     MachineBasicBlock::iterator I) const;
62
63  bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
64                                   MachineBasicBlock::iterator MI,
65                                   const std::vector<CalleeSavedInfo> &CSI,
66                                   const TargetRegisterInfo *TRI) const;
67
68  /// targetHandlesStackFrameRounding - Returns true if the target is
69  /// responsible for rounding up the stack frame (probably at emitPrologue
70  /// time).
71  bool targetHandlesStackFrameRounding() const { return true; }
72
73  /// getReturnSaveOffset - Return the previous frame offset to save the
74  /// return address.
75  static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
76    if (isDarwinABI)
77      return isPPC64 ? 16 : 8;
78    // SVR4 ABI:
79    return isPPC64 ? 16 : 4;
80  }
81
82  /// getFramePointerSaveOffset - Return the previous frame offset to save the
83  /// frame pointer.
84  static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
85    // For the Darwin ABI:
86    // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
87    // for saving the frame pointer (if needed.)  While the published ABI has
88    // not used this slot since at least MacOSX 10.2, there is older code
89    // around that does use it, and that needs to continue to work.
90    if (isDarwinABI)
91      return isPPC64 ? -8U : -4U;
92
93    // SVR4 ABI: First slot in the general register save area.
94    return isPPC64 ? -8U : -4U;
95  }
96
97  /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
98  ///
99  static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
100    if (isDarwinABI || isPPC64)
101      return 6 * (isPPC64 ? 8 : 4);
102
103    // SVR4 ABI:
104    return 8;
105  }
106
107  /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
108  /// argument area.
109  static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
110    // For the Darwin ABI / 64-bit SVR4 ABI:
111    // The prolog code of the callee may store up to 8 GPR argument registers to
112    // the stack, allowing va_start to index over them in memory if its varargs.
113    // Because we cannot tell if this is needed on the caller side, we have to
114    // conservatively assume that it is needed.  As such, make sure we have at
115    // least enough stack space for the caller to store the 8 GPRs.
116    if (isDarwinABI || isPPC64)
117      return 8 * (isPPC64 ? 8 : 4);
118
119    // 32-bit SVR4 ABI:
120    // There is no default stack allocated for the 8 first GPR arguments.
121    return 0;
122  }
123
124  /// getMinCallFrameSize - Return the minimum size a call frame can be using
125  /// the PowerPC ABI.
126  static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
127    // The call frame needs to be at least big enough for linkage and 8 args.
128    return getLinkageSize(isPPC64, isDarwinABI) +
129           getMinCallArgumentsSize(isPPC64, isDarwinABI);
130  }
131
132  // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
133  const SpillSlot *
134  getCalleeSavedSpillSlots(unsigned &NumEntries) const {
135    if (Subtarget.isDarwinABI()) {
136      NumEntries = 1;
137      if (Subtarget.isPPC64()) {
138        static const SpillSlot darwin64Offsets = {PPC::X31, -8};
139        return &darwin64Offsets;
140      } else {
141        static const SpillSlot darwinOffsets = {PPC::R31, -4};
142        return &darwinOffsets;
143      }
144    }
145
146    // Early exit if not using the SVR4 ABI.
147    if (!Subtarget.isSVR4ABI()) {
148      NumEntries = 0;
149      return 0;
150    }
151
152    // Note that the offsets here overlap, but this is fixed up in
153    // processFunctionBeforeFrameFinalized.
154
155    static const SpillSlot Offsets[] = {
156      // Floating-point register save area offsets.
157      {PPC::F31, -8},
158      {PPC::F30, -16},
159      {PPC::F29, -24},
160      {PPC::F28, -32},
161      {PPC::F27, -40},
162      {PPC::F26, -48},
163      {PPC::F25, -56},
164      {PPC::F24, -64},
165      {PPC::F23, -72},
166      {PPC::F22, -80},
167      {PPC::F21, -88},
168      {PPC::F20, -96},
169      {PPC::F19, -104},
170      {PPC::F18, -112},
171      {PPC::F17, -120},
172      {PPC::F16, -128},
173      {PPC::F15, -136},
174      {PPC::F14, -144},
175
176      // General register save area offsets.
177      {PPC::R31, -4},
178      {PPC::R30, -8},
179      {PPC::R29, -12},
180      {PPC::R28, -16},
181      {PPC::R27, -20},
182      {PPC::R26, -24},
183      {PPC::R25, -28},
184      {PPC::R24, -32},
185      {PPC::R23, -36},
186      {PPC::R22, -40},
187      {PPC::R21, -44},
188      {PPC::R20, -48},
189      {PPC::R19, -52},
190      {PPC::R18, -56},
191      {PPC::R17, -60},
192      {PPC::R16, -64},
193      {PPC::R15, -68},
194      {PPC::R14, -72},
195
196      // CR save area offset.  We map each of the nonvolatile CR fields
197      // to the slot for CR2, which is the first of the nonvolatile CR
198      // fields to be assigned, so that we only allocate one save slot.
199      // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
200      {PPC::CR2, -4},
201
202      // VRSAVE save area offset.
203      {PPC::VRSAVE, -4},
204
205      // Vector register save area
206      {PPC::V31, -16},
207      {PPC::V30, -32},
208      {PPC::V29, -48},
209      {PPC::V28, -64},
210      {PPC::V27, -80},
211      {PPC::V26, -96},
212      {PPC::V25, -112},
213      {PPC::V24, -128},
214      {PPC::V23, -144},
215      {PPC::V22, -160},
216      {PPC::V21, -176},
217      {PPC::V20, -192}
218    };
219
220    static const SpillSlot Offsets64[] = {
221      // Floating-point register save area offsets.
222      {PPC::F31, -8},
223      {PPC::F30, -16},
224      {PPC::F29, -24},
225      {PPC::F28, -32},
226      {PPC::F27, -40},
227      {PPC::F26, -48},
228      {PPC::F25, -56},
229      {PPC::F24, -64},
230      {PPC::F23, -72},
231      {PPC::F22, -80},
232      {PPC::F21, -88},
233      {PPC::F20, -96},
234      {PPC::F19, -104},
235      {PPC::F18, -112},
236      {PPC::F17, -120},
237      {PPC::F16, -128},
238      {PPC::F15, -136},
239      {PPC::F14, -144},
240
241      // General register save area offsets.
242      {PPC::X31, -8},
243      {PPC::X30, -16},
244      {PPC::X29, -24},
245      {PPC::X28, -32},
246      {PPC::X27, -40},
247      {PPC::X26, -48},
248      {PPC::X25, -56},
249      {PPC::X24, -64},
250      {PPC::X23, -72},
251      {PPC::X22, -80},
252      {PPC::X21, -88},
253      {PPC::X20, -96},
254      {PPC::X19, -104},
255      {PPC::X18, -112},
256      {PPC::X17, -120},
257      {PPC::X16, -128},
258      {PPC::X15, -136},
259      {PPC::X14, -144},
260
261      // VRSAVE save area offset.
262      {PPC::VRSAVE, -4},
263
264      // Vector register save area
265      {PPC::V31, -16},
266      {PPC::V30, -32},
267      {PPC::V29, -48},
268      {PPC::V28, -64},
269      {PPC::V27, -80},
270      {PPC::V26, -96},
271      {PPC::V25, -112},
272      {PPC::V24, -128},
273      {PPC::V23, -144},
274      {PPC::V22, -160},
275      {PPC::V21, -176},
276      {PPC::V20, -192}
277    };
278
279    if (Subtarget.isPPC64()) {
280      NumEntries = array_lengthof(Offsets64);
281
282      return Offsets64;
283    } else {
284      NumEntries = array_lengthof(Offsets);
285
286      return Offsets;
287    }
288  }
289};
290
291} // End llvm namespace
292
293#endif
294