MSP430RegisterInfo.cpp revision 195340 
1//===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-reg-info"
15
16#include "MSP430.h"
17#include "MSP430MachineFunctionInfo.h"
18#include "MSP430RegisterInfo.h"
19#include "MSP430TargetMachine.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/Target/TargetMachine.h"
24#include "llvm/Target/TargetOptions.h"
25#include "llvm/ADT/BitVector.h"
26
27using namespace llvm;
28
29// FIXME: Provide proper call frame setup / destroy opcodes.
30MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
31                                       const TargetInstrInfo &tii)
32  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
33    TM(tm), TII(tii) {
34  StackAlign = TM.getFrameInfo()->getStackAlignment();
35}
36
37const unsigned*
38MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
39  static const unsigned CalleeSavedRegs[] = {
40    MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
41    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
42    0
43  };
44
45  return CalleeSavedRegs;
46}
47
48const TargetRegisterClass* const*
49MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
50  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
51    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
52    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
53    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
54    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
55    0
56  };
57
58  return CalleeSavedRegClasses;
59}
60
61BitVector
62MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63  BitVector Reserved(getNumRegs());
64
65  // Mark 4 special registers as reserved.
66  Reserved.set(MSP430::PCW);
67  Reserved.set(MSP430::SPW);
68  Reserved.set(MSP430::SRW);
69  Reserved.set(MSP430::CGW);
70
71  // Mark frame pointer as reserved if needed.
72  if (hasFP(MF))
73    Reserved.set(MSP430::FPW);
74
75  return Reserved;
76}
77
78const TargetRegisterClass* MSP430RegisterInfo::getPointerRegClass() const {
79  return &MSP430::GR16RegClass;
80}
81
82
83bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
84  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
85}
86
87bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
88  return !MF.getFrameInfo()->hasVarSizedObjects();
89}
90
91void MSP430RegisterInfo::
92eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
93                              MachineBasicBlock::iterator I) const {
94  if (!hasReservedCallFrame(MF)) {
95    // If the stack pointer can be changed after prologue, turn the
96    // adjcallstackup instruction into a 'sub SPW, <amt>' and the
97    // adjcallstackdown instruction into 'add SPW, <amt>'
98    // TODO: consider using push / pop instead of sub + store / add
99    MachineInstr *Old = I;
100    uint64_t Amount = Old->getOperand(0).getImm();
101    if (Amount != 0) {
102      // We need to keep the stack aligned properly.  To do this, we round the
103      // amount of space needed for the outgoing arguments up to the next
104      // alignment boundary.
105      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
106
107      MachineInstr *New = 0;
108      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
109        New = BuildMI(MF, Old->getDebugLoc(),
110                      TII.get(MSP430::SUB16ri), MSP430::SPW)
111          .addReg(MSP430::SPW).addImm(Amount);
112      } else {
113        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
114        // factor out the amount the callee already popped.
115        uint64_t CalleeAmt = Old->getOperand(1).getImm();
116        Amount -= CalleeAmt;
117        if (Amount)
118          New = BuildMI(MF, Old->getDebugLoc(),
119                        TII.get(MSP430::ADD16ri), MSP430::SPW)
120            .addReg(MSP430::SPW).addImm(Amount);
121      }
122
123      if (New) {
124        // The SRW implicit def is dead.
125        New->getOperand(3).setIsDead();
126
127        // Replace the pseudo instruction with a new instruction...
128        MBB.insert(I, New);
129      }
130    }
131  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
132    // If we are performing frame pointer elimination and if the callee pops
133    // something off the stack pointer, add it back.
134    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
135      MachineInstr *Old = I;
136      MachineInstr *New =
137        BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
138                MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
139      // The SRW implicit def is dead.
140      New->getOperand(3).setIsDead();
141
142      MBB.insert(I, New);
143    }
144  }
145
146  MBB.erase(I);
147}
148
149void
150MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
151                                        int SPAdj, RegScavenger *RS) const {
152  assert(SPAdj == 0 && "Unexpected");
153
154  unsigned i = 0;
155  MachineInstr &MI = *II;
156  MachineBasicBlock &MBB = *MI.getParent();
157  MachineFunction &MF = *MBB.getParent();
158  DebugLoc dl = MI.getDebugLoc();
159  while (!MI.getOperand(i).isFI()) {
160    ++i;
161    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
162  }
163
164  int FrameIndex = MI.getOperand(i).getIndex();
165
166  unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
167  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
168
169  // Skip the saved PC
170  Offset += 2;
171
172  if (!hasFP(MF))
173    Offset += MF.getFrameInfo()->getStackSize();
174  else
175    Offset += 2; // Skip the saved FPW
176
177  // Fold imm into offset
178  Offset += MI.getOperand(i+1).getImm();
179
180  if (MI.getOpcode() == MSP430::ADD16ri) {
181    // This is actually "load effective address" of the stack slot
182    // instruction. We have only two-address instructions, thus we need to
183    // expand it into mov + add
184
185    MI.setDesc(TII.get(MSP430::MOV16rr));
186    MI.getOperand(i).ChangeToRegister(BasePtr, false);
187
188    if (Offset == 0)
189      return;
190
191    // We need to materialize the offset via add instruction.
192    unsigned DstReg = MI.getOperand(0).getReg();
193    if (Offset < 0)
194      BuildMI(MBB, next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
195        .addReg(DstReg).addImm(-Offset);
196    else
197      BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
198        .addReg(DstReg).addImm(Offset);
199
200    return;
201  }
202
203  MI.getOperand(i).ChangeToRegister(BasePtr, false);
204  MI.getOperand(i+1).ChangeToImmediate(Offset);
205}
206
207void
208MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
209                                                                         const {
210  // Create a frame entry for the FPW register that must be saved.
211  if (hasFP(MF)) {
212    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4);
213    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
214           "Slot for FPW register must be last in order to be found!");
215    FrameIdx = 0;
216  }
217}
218
219
220void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
221  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
222  MachineFrameInfo *MFI = MF.getFrameInfo();
223  MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
224  MachineBasicBlock::iterator MBBI = MBB.begin();
225  DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
226                 DebugLoc::getUnknownLoc());
227
228  // Get the number of bytes to allocate from the FrameInfo.
229  uint64_t StackSize = MFI->getStackSize();
230
231  uint64_t NumBytes = 0;
232  if (hasFP(MF)) {
233    // Calculate required stack adjustment
234    uint64_t FrameSize = StackSize - 2;
235    NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
236
237    // Get the offset of the stack slot for the EBP register... which is
238    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
239    // Update the frame offset adjustment.
240    MFI->setOffsetAdjustment(-NumBytes);
241
242    // Save FPW into the appropriate stack slot...
243    BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
244      .addReg(MSP430::FPW, RegState::Kill);
245
246    // Update FPW with the new base value...
247    BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
248      .addReg(MSP430::SPW);
249
250    // Mark the FramePtr as live-in in every block except the entry.
251    for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
252         I != E; ++I)
253      I->addLiveIn(MSP430::FPW);
254
255  } else
256    NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
257
258  // Skip the callee-saved push instructions.
259  while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
260    ++MBBI;
261
262  if (MBBI != MBB.end())
263    DL = MBBI->getDebugLoc();
264
265  if (NumBytes) { // adjust stack pointer: SPW -= numbytes
266    // If there is an SUB16ri of SPW immediately before this instruction, merge
267    // the two.
268    //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
269    // If there is an ADD16ri or SUB16ri of SPW immediately after this
270    // instruction, merge the two instructions.
271    // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
272
273    if (NumBytes) {
274      MachineInstr *MI =
275        BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
276        .addReg(MSP430::SPW).addImm(NumBytes);
277      // The SRW implicit def is dead.
278      MI->getOperand(3).setIsDead();
279    }
280  }
281}
282
283void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
284                                      MachineBasicBlock &MBB) const {
285  const MachineFrameInfo *MFI = MF.getFrameInfo();
286  MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
287  MachineBasicBlock::iterator MBBI = prior(MBB.end());
288  unsigned RetOpcode = MBBI->getOpcode();
289  DebugLoc DL = MBBI->getDebugLoc();
290
291  switch (RetOpcode) {
292  case MSP430::RET: break;  // These are ok
293  default:
294    assert(0 && "Can only insert epilog into returning blocks");
295  }
296
297  // Get the number of bytes to allocate from the FrameInfo
298  uint64_t StackSize = MFI->getStackSize();
299  unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
300  uint64_t NumBytes = 0;
301
302  if (hasFP(MF)) {
303    // Calculate required stack adjustment
304    uint64_t FrameSize = StackSize - 2;
305    NumBytes = FrameSize - CSSize;
306
307    // pop FPW.
308    BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
309  } else
310    NumBytes = StackSize - CSSize;
311
312  // Skip the callee-saved pop instructions.
313  MachineBasicBlock::iterator LastCSPop = MBBI;
314  while (MBBI != MBB.begin()) {
315    MachineBasicBlock::iterator PI = prior(MBBI);
316    unsigned Opc = PI->getOpcode();
317    if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
318      break;
319    --MBBI;
320  }
321
322  DL = MBBI->getDebugLoc();
323
324  // If there is an ADD16ri or SUB16ri of SPW immediately before this
325  // instruction, merge the two instructions.
326  //if (NumBytes || MFI->hasVarSizedObjects())
327  //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
328
329  if (MFI->hasVarSizedObjects()) {
330    assert(0 && "Not implemented yet!");
331  } else {
332    // adjust stack pointer back: SPW += numbytes
333    if (NumBytes) {
334      MachineInstr *MI =
335        BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
336        .addReg(MSP430::SPW).addImm(NumBytes);
337      // The SRW implicit def is dead.
338      MI->getOperand(3).setIsDead();
339    }
340  }
341}
342
343unsigned MSP430RegisterInfo::getRARegister() const {
344  return MSP430::PCW;
345}
346
347unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const {
348  return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
349}
350
351int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
352  assert(0 && "Not implemented yet!");
353  return 0;
354}
355
356#include "MSP430GenRegisterInfo.inc"
357