1234353Sdim//===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the MSP430 instructions in TableGen format. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sedinclude "MSP430InstrFormats.td" 15193323Sed 16193323Sed//===----------------------------------------------------------------------===// 17193323Sed// Type Constraints. 18193323Sed//===----------------------------------------------------------------------===// 19193323Sedclass SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 20193323Sedclass SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 21193323Sed 22193323Sed//===----------------------------------------------------------------------===// 23193323Sed// Type Profiles. 24193323Sed//===----------------------------------------------------------------------===// 25193323Seddef SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 26193323Seddef SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>; 27193323Seddef SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 28210299Seddef SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29210299Sed SDTCisPtrTy<0>]>; 30193323Seddef SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 31193323Seddef SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, 32193323Sed SDTCisVT<1, i8>]>; 33210299Seddef SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 34210299Sed SDTCisSameAs<1, 2>, 35193323Sed SDTCisVT<3, i8>]>; 36210299Seddef SDT_MSP430Shift : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 37210299Sed SDTCisI8<2>]>; 38193323Sed 39193323Sed//===----------------------------------------------------------------------===// 40193323Sed// MSP430 Specific Node Definitions. 41193323Sed//===----------------------------------------------------------------------===// 42200581Srdivackydef MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone, 43249423Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 44200581Srdivackydef MSP430retiflag : SDNode<"MSP430ISD::RETI_FLAG", SDTNone, 45249423Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 46193323Sed 47193323Seddef MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; 48193323Seddef MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>; 49193323Seddef MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>; 50193323Sed 51193323Seddef MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, 52218893Sdim [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 53193323Seddef MSP430callseq_start : 54193323Sed SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart, 55218893Sdim [SDNPHasChain, SDNPOutGlue]>; 56193323Seddef MSP430callseq_end : 57193323Sed SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd, 58218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 59193323Seddef MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; 60218893Sdimdef MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutGlue]>; 61210299Seddef MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, 62218893Sdim [SDNPHasChain, SDNPInGlue]>; 63210299Seddef MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, 64218893Sdim [SDNPInGlue]>; 65200581Srdivackydef MSP430shl : SDNode<"MSP430ISD::SHL", SDT_MSP430Shift, []>; 66200581Srdivackydef MSP430sra : SDNode<"MSP430ISD::SRA", SDT_MSP430Shift, []>; 67200581Srdivackydef MSP430srl : SDNode<"MSP430ISD::SRL", SDT_MSP430Shift, []>; 68193323Sed 69193323Sed//===----------------------------------------------------------------------===// 70193323Sed// MSP430 Operand Definitions. 71193323Sed//===----------------------------------------------------------------------===// 72193323Sed 73193323Sed// Address operands 74193323Seddef memsrc : Operand<i16> { 75193323Sed let PrintMethod = "printSrcMemOperand"; 76193323Sed let MIOperandInfo = (ops GR16, i16imm); 77193323Sed} 78193323Sed 79193323Seddef memdst : Operand<i16> { 80193323Sed let PrintMethod = "printSrcMemOperand"; 81193323Sed let MIOperandInfo = (ops GR16, i16imm); 82193323Sed} 83193323Sed 84207618Srdivacky// Short jump targets have OtherVT type and are printed as pcrel imm values. 85207618Srdivackydef jmptarget : Operand<OtherVT> { 86198396Srdivacky let PrintMethod = "printPCRelImmOperand"; 87198396Srdivacky} 88193323Sed 89193323Sed// Operand for printing out a condition code. 90193323Seddef cc : Operand<i8> { 91193323Sed let PrintMethod = "printCCOperand"; 92193323Sed} 93193323Sed 94193323Sed//===----------------------------------------------------------------------===// 95193323Sed// MSP430 Complex Pattern Definitions. 96193323Sed//===----------------------------------------------------------------------===// 97193323Sed 98193323Seddef addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>; 99193323Sed 100193323Sed//===----------------------------------------------------------------------===// 101193323Sed// Pattern Fragments 102193323Seddef zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 103193323Seddef extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>; 104200581Srdivackydef and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 105200581Srdivacky return N->hasOneUse(); 106200581Srdivacky}]>; 107193323Sed//===----------------------------------------------------------------------===// 108193323Sed// Instruction list.. 109193323Sed 110193323Sed// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 111193323Sed// a stack adjustment and the codegen must know that they may modify the stack 112193323Sed// pointer before prolog-epilog rewriting occurs. 113193323Sed// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 114193323Sed// sub / add which can clobber SRW. 115193323Sedlet Defs = [SPW, SRW], Uses = [SPW] in { 116193323Seddef ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt), 117193323Sed "#ADJCALLSTACKDOWN", 118193323Sed [(MSP430callseq_start timm:$amt)]>; 119193323Seddef ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), 120193323Sed "#ADJCALLSTACKUP", 121193323Sed [(MSP430callseq_end timm:$amt1, timm:$amt2)]>; 122193323Sed} 123193323Sed 124198892Srdivackylet usesCustomInserter = 1 in { 125210299Sed def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc), 126193323Sed "# Select8 PSEUDO", 127193323Sed [(set GR8:$dst, 128210299Sed (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>; 129210299Sed def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc), 130193323Sed "# Select16 PSEUDO", 131193323Sed [(set GR16:$dst, 132210299Sed (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>; 133200581Srdivacky let Defs = [SRW] in { 134200581Srdivacky def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 135200581Srdivacky "# Shl8 PSEUDO", 136200581Srdivacky [(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>; 137200581Srdivacky def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 138200581Srdivacky "# Shl16 PSEUDO", 139200581Srdivacky [(set GR16:$dst, (MSP430shl GR16:$src, GR8:$cnt))]>; 140200581Srdivacky def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 141200581Srdivacky "# Sra8 PSEUDO", 142200581Srdivacky [(set GR8:$dst, (MSP430sra GR8:$src, GR8:$cnt))]>; 143200581Srdivacky def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 144200581Srdivacky "# Sra16 PSEUDO", 145200581Srdivacky [(set GR16:$dst, (MSP430sra GR16:$src, GR8:$cnt))]>; 146200581Srdivacky def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 147200581Srdivacky "# Srl8 PSEUDO", 148200581Srdivacky [(set GR8:$dst, (MSP430srl GR8:$src, GR8:$cnt))]>; 149200581Srdivacky def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 150200581Srdivacky "# Srl16 PSEUDO", 151200581Srdivacky [(set GR16:$dst, (MSP430srl GR16:$src, GR8:$cnt))]>; 152200581Srdivacky 153200581Srdivacky } 154193323Sed} 155193323Sed 156193323Sedlet neverHasSideEffects = 1 in 157193323Seddef NOP : Pseudo<(outs), (ins), "nop", []>; 158193323Sed 159193323Sed//===----------------------------------------------------------------------===// 160193323Sed// Control Flow Instructions... 161193323Sed// 162193323Sed 163193323Sed// FIXME: Provide proper encoding! 164199481Srdivackylet isReturn = 1, isTerminator = 1, isBarrier = 1 in { 165202878Srdivacky def RET : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 166202878Srdivacky (outs), (ins), "ret", [(MSP430retflag)]>; 167202878Srdivacky def RETI : II16r<0x0, (outs), (ins), "reti", [(MSP430retiflag)]>; 168193323Sed} 169193323Sed 170193323Sedlet isBranch = 1, isTerminator = 1 in { 171193323Sed 172202878Srdivacky// FIXME: expand opcode & cond field for branches! 173202878Srdivacky 174193323Sed// Direct branch 175202878Srdivackylet isBarrier = 1 in { 176202878Srdivacky // Short branch 177207618Srdivacky def JMP : CJForm<0, 0, (outs), (ins jmptarget:$dst), 178193323Sed "jmp\t$dst", 179193323Sed [(br bb:$dst)]>; 180207618Srdivacky let isIndirectBranch = 1 in { 181207618Srdivacky // Long branches 182207618Srdivacky def Bi : I16ri<0, (outs), (ins i16imm:$brdst), 183207618Srdivacky "br\t$brdst", 184207618Srdivacky [(brind tblockaddress:$brdst)]>; 185207618Srdivacky def Br : I16rr<0, (outs), (ins GR16:$brdst), 186263508Sdim "br\t$brdst", 187207618Srdivacky [(brind GR16:$brdst)]>; 188207618Srdivacky def Bm : I16rm<0, (outs), (ins memsrc:$brdst), 189263508Sdim "br\t$brdst", 190207618Srdivacky [(brind (load addr:$brdst))]>; 191207618Srdivacky } 192202878Srdivacky} 193193323Sed 194193323Sed// Conditional branches 195193323Sedlet Uses = [SRW] in 196202878Srdivacky def JCC : CJForm<0, 0, 197207618Srdivacky (outs), (ins jmptarget:$dst, cc:$cc), 198202878Srdivacky "j$cc\t$dst", 199202878Srdivacky [(MSP430brcc bb:$dst, imm:$cc)]>; 200193323Sed} // isBranch, isTerminator 201193323Sed 202193323Sed//===----------------------------------------------------------------------===// 203193323Sed// Call Instructions... 204193323Sed// 205193323Sedlet isCall = 1 in 206193323Sed // All calls clobber the non-callee saved registers. SPW is marked as 207193323Sed // a use to prevent stack-pointer assignments that appear immediately 208193323Sed // before calls from potentially appearing dead. Uses for argument 209193323Sed // registers are added manually. 210193323Sed let Defs = [R12W, R13W, R14W, R15W, SRW], 211193323Sed Uses = [SPW] in { 212202878Srdivacky def CALLi : II16i<0x0, 213239462Sdim (outs), (ins i16imm:$dst), 214202878Srdivacky "call\t$dst", [(MSP430call imm:$dst)]>; 215202878Srdivacky def CALLr : II16r<0x0, 216239462Sdim (outs), (ins GR16:$dst), 217202878Srdivacky "call\t$dst", [(MSP430call GR16:$dst)]>; 218202878Srdivacky def CALLm : II16m<0x0, 219239462Sdim (outs), (ins memsrc:$dst), 220202878Srdivacky "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>; 221193323Sed } 222193323Sed 223193323Sed 224193323Sed//===----------------------------------------------------------------------===// 225193323Sed// Miscellaneous Instructions... 226193323Sed// 227193323Sedlet Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in { 228193323Sedlet mayLoad = 1 in 229202878Srdivackydef POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 230202878Srdivacky (outs GR16:$reg), (ins), "pop.w\t$reg", []>; 231193323Sed 232193323Sedlet mayStore = 1 in 233202878Srdivackydef PUSH16r : II16r<0x0, 234202878Srdivacky (outs), (ins GR16:$reg), "push.w\t$reg",[]>; 235193323Sed} 236193323Sed 237193323Sed//===----------------------------------------------------------------------===// 238193323Sed// Move Instructions 239193323Sed 240193323Sed// FIXME: Provide proper encoding! 241193323Sedlet neverHasSideEffects = 1 in { 242202878Srdivackydef MOV8rr : I8rr<0x0, 243202878Srdivacky (outs GR8:$dst), (ins GR8:$src), 244202878Srdivacky "mov.b\t{$src, $dst}", 245202878Srdivacky []>; 246202878Srdivackydef MOV16rr : I16rr<0x0, 247202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 248202878Srdivacky "mov.w\t{$src, $dst}", 249202878Srdivacky []>; 250193323Sed} 251193323Sed 252193323Sed// FIXME: Provide proper encoding! 253193323Sedlet isReMaterializable = 1, isAsCheapAsAMove = 1 in { 254202878Srdivackydef MOV8ri : I8ri<0x0, 255202878Srdivacky (outs GR8:$dst), (ins i8imm:$src), 256202878Srdivacky "mov.b\t{$src, $dst}", 257202878Srdivacky [(set GR8:$dst, imm:$src)]>; 258202878Srdivackydef MOV16ri : I16ri<0x0, 259202878Srdivacky (outs GR16:$dst), (ins i16imm:$src), 260202878Srdivacky "mov.w\t{$src, $dst}", 261202878Srdivacky [(set GR16:$dst, imm:$src)]>; 262193323Sed} 263193323Sed 264204642Srdivackylet canFoldAsLoad = 1, isReMaterializable = 1 in { 265202878Srdivackydef MOV8rm : I8rm<0x0, 266202878Srdivacky (outs GR8:$dst), (ins memsrc:$src), 267202878Srdivacky "mov.b\t{$src, $dst}", 268202878Srdivacky [(set GR8:$dst, (load addr:$src))]>; 269202878Srdivackydef MOV16rm : I16rm<0x0, 270202878Srdivacky (outs GR16:$dst), (ins memsrc:$src), 271202878Srdivacky "mov.w\t{$src, $dst}", 272202878Srdivacky [(set GR16:$dst, (load addr:$src))]>; 273193323Sed} 274193323Sed 275202878Srdivackydef MOVZX16rr8 : I8rr<0x0, 276202878Srdivacky (outs GR16:$dst), (ins GR8:$src), 277202878Srdivacky "mov.b\t{$src, $dst}", 278202878Srdivacky [(set GR16:$dst, (zext GR8:$src))]>; 279202878Srdivackydef MOVZX16rm8 : I8rm<0x0, 280202878Srdivacky (outs GR16:$dst), (ins memsrc:$src), 281202878Srdivacky "mov.b\t{$src, $dst}", 282202878Srdivacky [(set GR16:$dst, (zextloadi16i8 addr:$src))]>; 283193323Sed 284199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in { 285202878Srdivackydef MOV8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 286202878Srdivacky (outs GR8:$dst, GR16:$base_wb), (ins GR16:$base), 287202878Srdivacky "mov.b\t{@$base+, $dst}", []>; 288202878Srdivackydef MOV16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 289202878Srdivacky (outs GR16:$dst, GR16:$base_wb), (ins GR16:$base), 290202878Srdivacky "mov.w\t{@$base+, $dst}", []>; 291199481Srdivacky} 292199481Srdivacky 293193323Sed// Any instruction that defines a 8-bit result leaves the high half of the 294193323Sed// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may 295193323Sed// be copying from a truncate, but any other 8-bit operation will zero-extend 296193323Sed// up to 16 bits. 297193323Seddef def8 : PatLeaf<(i8 GR8:$src), [{ 298193323Sed return N->getOpcode() != ISD::TRUNCATE && 299203954Srdivacky N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 300193323Sed N->getOpcode() != ISD::CopyFromReg; 301193323Sed}]>; 302193323Sed 303193323Sed// In the case of a 8-bit def that is known to implicitly zero-extend, 304193323Sed// we can use a SUBREG_TO_REG. 305193323Seddef : Pat<(i16 (zext def8:$src)), 306193323Sed (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 307193323Sed 308202878Srdivackydef MOV8mi : I8mi<0x0, 309202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 310202878Srdivacky "mov.b\t{$src, $dst}", 311202878Srdivacky [(store (i8 imm:$src), addr:$dst)]>; 312202878Srdivackydef MOV16mi : I16mi<0x0, 313202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 314202878Srdivacky "mov.w\t{$src, $dst}", 315202878Srdivacky [(store (i16 imm:$src), addr:$dst)]>; 316193323Sed 317202878Srdivackydef MOV8mr : I8mr<0x0, 318202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 319202878Srdivacky "mov.b\t{$src, $dst}", 320202878Srdivacky [(store GR8:$src, addr:$dst)]>; 321202878Srdivackydef MOV16mr : I16mr<0x0, 322202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 323202878Srdivacky "mov.w\t{$src, $dst}", 324202878Srdivacky [(store GR16:$src, addr:$dst)]>; 325193323Sed 326202878Srdivackydef MOV8mm : I8mm<0x0, 327202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 328202878Srdivacky "mov.b\t{$src, $dst}", 329202878Srdivacky [(store (i8 (load addr:$src)), addr:$dst)]>; 330202878Srdivackydef MOV16mm : I16mm<0x0, 331202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 332202878Srdivacky "mov.w\t{$src, $dst}", 333202878Srdivacky [(store (i16 (load addr:$src)), addr:$dst)]>; 334193323Sed 335193323Sed//===----------------------------------------------------------------------===// 336193323Sed// Arithmetic Instructions 337193323Sed 338210299Sedlet Constraints = "$src = $dst" in { 339193323Sed 340193323Sedlet Defs = [SRW] in { 341193323Sed 342193323Sedlet isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 343202878Srdivacky 344202878Srdivackydef ADD8rr : I8rr<0x0, 345210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 346202878Srdivacky "add.b\t{$src2, $dst}", 347210299Sed [(set GR8:$dst, (add GR8:$src, GR8:$src2)), 348202878Srdivacky (implicit SRW)]>; 349202878Srdivackydef ADD16rr : I16rr<0x0, 350210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 351202878Srdivacky "add.w\t{$src2, $dst}", 352210299Sed [(set GR16:$dst, (add GR16:$src, GR16:$src2)), 353202878Srdivacky (implicit SRW)]>; 354193323Sed} 355193323Sed 356202878Srdivackydef ADD8rm : I8rm<0x0, 357210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 358202878Srdivacky "add.b\t{$src2, $dst}", 359210299Sed [(set GR8:$dst, (add GR8:$src, (load addr:$src2))), 360202878Srdivacky (implicit SRW)]>; 361202878Srdivackydef ADD16rm : I16rm<0x0, 362210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 363202878Srdivacky "add.w\t{$src2, $dst}", 364210299Sed [(set GR16:$dst, (add GR16:$src, (load addr:$src2))), 365202878Srdivacky (implicit SRW)]>; 366193323Sed 367199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, 368210299SedConstraints = "$base = $base_wb, $src = $dst" in { 369202878Srdivackydef ADD8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 370202878Srdivacky (outs GR8:$dst, GR16:$base_wb), 371210299Sed (ins GR8:$src, GR16:$base), 372202878Srdivacky "add.b\t{@$base+, $dst}", []>; 373202878Srdivackydef ADD16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 374202878Srdivacky (outs GR16:$dst, GR16:$base_wb), 375210299Sed (ins GR16:$src, GR16:$base), 376199481Srdivacky "add.w\t{@$base+, $dst}", []>; 377199481Srdivacky} 378199481Srdivacky 379199481Srdivacky 380202878Srdivackydef ADD8ri : I8ri<0x0, 381210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 382202878Srdivacky "add.b\t{$src2, $dst}", 383210299Sed [(set GR8:$dst, (add GR8:$src, imm:$src2)), 384202878Srdivacky (implicit SRW)]>; 385202878Srdivackydef ADD16ri : I16ri<0x0, 386210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 387202878Srdivacky "add.w\t{$src2, $dst}", 388210299Sed [(set GR16:$dst, (add GR16:$src, imm:$src2)), 389202878Srdivacky (implicit SRW)]>; 390193323Sed 391210299Sedlet Constraints = "" in { 392202878Srdivackydef ADD8mr : I8mr<0x0, 393202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 394202878Srdivacky "add.b\t{$src, $dst}", 395202878Srdivacky [(store (add (load addr:$dst), GR8:$src), addr:$dst), 396202878Srdivacky (implicit SRW)]>; 397202878Srdivackydef ADD16mr : I16mr<0x0, 398202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 399202878Srdivacky "add.w\t{$src, $dst}", 400202878Srdivacky [(store (add (load addr:$dst), GR16:$src), addr:$dst), 401202878Srdivacky (implicit SRW)]>; 402193323Sed 403202878Srdivackydef ADD8mi : I8mi<0x0, 404202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 405202878Srdivacky "add.b\t{$src, $dst}", 406202878Srdivacky [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst), 407202878Srdivacky (implicit SRW)]>; 408202878Srdivackydef ADD16mi : I16mi<0x0, 409202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 410202878Srdivacky "add.w\t{$src, $dst}", 411202878Srdivacky [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst), 412202878Srdivacky (implicit SRW)]>; 413193323Sed 414202878Srdivackydef ADD8mm : I8mm<0x0, 415202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 416202878Srdivacky "add.b\t{$src, $dst}", 417202878Srdivacky [(store (add (load addr:$dst), 418202878Srdivacky (i8 (load addr:$src))), addr:$dst), 419202878Srdivacky (implicit SRW)]>; 420202878Srdivackydef ADD16mm : I16mm<0x0, 421202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 422202878Srdivacky "add.w\t{$src, $dst}", 423202878Srdivacky [(store (add (load addr:$dst), 424202878Srdivacky (i16 (load addr:$src))), addr:$dst), 425202878Srdivacky (implicit SRW)]>; 426193323Sed} 427193323Sed 428193323Sedlet Uses = [SRW] in { 429193323Sed 430193323Sedlet isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y 431202878Srdivackydef ADC8rr : I8rr<0x0, 432210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 433202878Srdivacky "addc.b\t{$src2, $dst}", 434210299Sed [(set GR8:$dst, (adde GR8:$src, GR8:$src2)), 435202878Srdivacky (implicit SRW)]>; 436202878Srdivackydef ADC16rr : I16rr<0x0, 437210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 438202878Srdivacky "addc.w\t{$src2, $dst}", 439210299Sed [(set GR16:$dst, (adde GR16:$src, GR16:$src2)), 440202878Srdivacky (implicit SRW)]>; 441193323Sed} // isCommutable 442193323Sed 443202878Srdivackydef ADC8ri : I8ri<0x0, 444210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 445202878Srdivacky "addc.b\t{$src2, $dst}", 446210299Sed [(set GR8:$dst, (adde GR8:$src, imm:$src2)), 447202878Srdivacky (implicit SRW)]>; 448202878Srdivackydef ADC16ri : I16ri<0x0, 449210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 450202878Srdivacky "addc.w\t{$src2, $dst}", 451210299Sed [(set GR16:$dst, (adde GR16:$src, imm:$src2)), 452202878Srdivacky (implicit SRW)]>; 453193323Sed 454202878Srdivackydef ADC8rm : I8rm<0x0, 455210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 456202878Srdivacky "addc.b\t{$src2, $dst}", 457210299Sed [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))), 458202878Srdivacky (implicit SRW)]>; 459202878Srdivackydef ADC16rm : I16rm<0x0, 460210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 461202878Srdivacky "addc.w\t{$src2, $dst}", 462210299Sed [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))), 463202878Srdivacky (implicit SRW)]>; 464193323Sed 465210299Sedlet Constraints = "" in { 466202878Srdivackydef ADC8mr : I8mr<0x0, 467202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 468202878Srdivacky "addc.b\t{$src, $dst}", 469202878Srdivacky [(store (adde (load addr:$dst), GR8:$src), addr:$dst), 470202878Srdivacky (implicit SRW)]>; 471202878Srdivackydef ADC16mr : I16mr<0x0, 472202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 473202878Srdivacky "addc.w\t{$src, $dst}", 474202878Srdivacky [(store (adde (load addr:$dst), GR16:$src), addr:$dst), 475202878Srdivacky (implicit SRW)]>; 476193323Sed 477202878Srdivackydef ADC8mi : I8mi<0x0, 478202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 479202878Srdivacky "addc.b\t{$src, $dst}", 480202878Srdivacky [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst), 481202878Srdivacky (implicit SRW)]>; 482202878Srdivackydef ADC16mi : I16mi<0x0, 483202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 484202878Srdivacky "addc.w\t{$src, $dst}", 485202878Srdivacky [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst), 486202878Srdivacky (implicit SRW)]>; 487193323Sed 488202878Srdivackydef ADC8mm : I8mm<0x0, 489202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 490202878Srdivacky "addc.b\t{$src, $dst}", 491202878Srdivacky [(store (adde (load addr:$dst), 492202878Srdivacky (i8 (load addr:$src))), addr:$dst), 493202878Srdivacky (implicit SRW)]>; 494202878Srdivackydef ADC16mm : I8mm<0x0, 495202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 496202878Srdivacky "addc.w\t{$src, $dst}", 497202878Srdivacky [(store (adde (load addr:$dst), 498202878Srdivacky (i16 (load addr:$src))), addr:$dst), 499202878Srdivacky (implicit SRW)]>; 500193323Sed} 501193323Sed 502193323Sed} // Uses = [SRW] 503193323Sed 504193323Sedlet isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y 505202878Srdivackydef AND8rr : I8rr<0x0, 506210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 507202878Srdivacky "and.b\t{$src2, $dst}", 508210299Sed [(set GR8:$dst, (and GR8:$src, GR8:$src2)), 509202878Srdivacky (implicit SRW)]>; 510202878Srdivackydef AND16rr : I16rr<0x0, 511210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 512202878Srdivacky "and.w\t{$src2, $dst}", 513210299Sed [(set GR16:$dst, (and GR16:$src, GR16:$src2)), 514202878Srdivacky (implicit SRW)]>; 515193323Sed} 516193323Sed 517202878Srdivackydef AND8ri : I8ri<0x0, 518210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 519202878Srdivacky "and.b\t{$src2, $dst}", 520210299Sed [(set GR8:$dst, (and GR8:$src, imm:$src2)), 521202878Srdivacky (implicit SRW)]>; 522202878Srdivackydef AND16ri : I16ri<0x0, 523210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 524202878Srdivacky "and.w\t{$src2, $dst}", 525210299Sed [(set GR16:$dst, (and GR16:$src, imm:$src2)), 526202878Srdivacky (implicit SRW)]>; 527193323Sed 528202878Srdivackydef AND8rm : I8rm<0x0, 529210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 530202878Srdivacky "and.b\t{$src2, $dst}", 531210299Sed [(set GR8:$dst, (and GR8:$src, (load addr:$src2))), 532202878Srdivacky (implicit SRW)]>; 533202878Srdivackydef AND16rm : I16rm<0x0, 534210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 535202878Srdivacky "and.w\t{$src2, $dst}", 536210299Sed [(set GR16:$dst, (and GR16:$src, (load addr:$src2))), 537202878Srdivacky (implicit SRW)]>; 538193323Sed 539199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, 540210299SedConstraints = "$base = $base_wb, $src = $dst" in { 541202878Srdivackydef AND8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 542202878Srdivacky (outs GR8:$dst, GR16:$base_wb), 543210299Sed (ins GR8:$src, GR16:$base), 544202878Srdivacky "and.b\t{@$base+, $dst}", []>; 545202878Srdivackydef AND16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 546202878Srdivacky (outs GR16:$dst, GR16:$base_wb), 547210299Sed (ins GR16:$src, GR16:$base), 548202878Srdivacky "and.w\t{@$base+, $dst}", []>; 549199481Srdivacky} 550199481Srdivacky 551210299Sedlet Constraints = "" in { 552202878Srdivackydef AND8mr : I8mr<0x0, 553202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 554202878Srdivacky "and.b\t{$src, $dst}", 555202878Srdivacky [(store (and (load addr:$dst), GR8:$src), addr:$dst), 556202878Srdivacky (implicit SRW)]>; 557202878Srdivackydef AND16mr : I16mr<0x0, 558202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 559202878Srdivacky "and.w\t{$src, $dst}", 560202878Srdivacky [(store (and (load addr:$dst), GR16:$src), addr:$dst), 561202878Srdivacky (implicit SRW)]>; 562193323Sed 563202878Srdivackydef AND8mi : I8mi<0x0, 564202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 565202878Srdivacky "and.b\t{$src, $dst}", 566202878Srdivacky [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst), 567202878Srdivacky (implicit SRW)]>; 568202878Srdivackydef AND16mi : I16mi<0x0, 569202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 570202878Srdivacky "and.w\t{$src, $dst}", 571202878Srdivacky [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst), 572202878Srdivacky (implicit SRW)]>; 573193323Sed 574202878Srdivackydef AND8mm : I8mm<0x0, 575202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 576202878Srdivacky "and.b\t{$src, $dst}", 577202878Srdivacky [(store (and (load addr:$dst), 578202878Srdivacky (i8 (load addr:$src))), addr:$dst), 579202878Srdivacky (implicit SRW)]>; 580202878Srdivackydef AND16mm : I16mm<0x0, 581202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 582202878Srdivacky "and.w\t{$src, $dst}", 583202878Srdivacky [(store (and (load addr:$dst), 584202878Srdivacky (i16 (load addr:$src))), addr:$dst), 585202878Srdivacky (implicit SRW)]>; 586193323Sed} 587193323Sed 588199481Srdivackylet isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y 589202878Srdivackydef OR8rr : I8rr<0x0, 590210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 591202878Srdivacky "bis.b\t{$src2, $dst}", 592210299Sed [(set GR8:$dst, (or GR8:$src, GR8:$src2))]>; 593202878Srdivackydef OR16rr : I16rr<0x0, 594210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 595202878Srdivacky "bis.w\t{$src2, $dst}", 596210299Sed [(set GR16:$dst, (or GR16:$src, GR16:$src2))]>; 597199481Srdivacky} 598193323Sed 599202878Srdivackydef OR8ri : I8ri<0x0, 600210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 601202878Srdivacky "bis.b\t{$src2, $dst}", 602210299Sed [(set GR8:$dst, (or GR8:$src, imm:$src2))]>; 603202878Srdivackydef OR16ri : I16ri<0x0, 604210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 605202878Srdivacky "bis.w\t{$src2, $dst}", 606210299Sed [(set GR16:$dst, (or GR16:$src, imm:$src2))]>; 607199481Srdivacky 608202878Srdivackydef OR8rm : I8rm<0x0, 609210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 610202878Srdivacky "bis.b\t{$src2, $dst}", 611210299Sed [(set GR8:$dst, (or GR8:$src, (load addr:$src2)))]>; 612202878Srdivackydef OR16rm : I16rm<0x0, 613210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 614202878Srdivacky "bis.w\t{$src2, $dst}", 615210299Sed [(set GR16:$dst, (or GR16:$src, (load addr:$src2)))]>; 616199481Srdivacky 617199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, 618210299SedConstraints = "$base = $base_wb, $src = $dst" in { 619202878Srdivackydef OR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 620202878Srdivacky (outs GR8:$dst, GR16:$base_wb), 621210299Sed (ins GR8:$src, GR16:$base), 622199481Srdivacky "bis.b\t{@$base+, $dst}", []>; 623202878Srdivackydef OR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 624202878Srdivacky (outs GR16:$dst, GR16:$base_wb), 625210299Sed (ins GR16:$src, GR16:$base), 626202878Srdivacky "bis.w\t{@$base+, $dst}", []>; 627199481Srdivacky} 628199481Srdivacky 629210299Sedlet Constraints = "" in { 630202878Srdivackydef OR8mr : I8mr<0x0, 631202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 632202878Srdivacky "bis.b\t{$src, $dst}", 633202878Srdivacky [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; 634202878Srdivackydef OR16mr : I16mr<0x0, 635202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 636202878Srdivacky "bis.w\t{$src, $dst}", 637202878Srdivacky [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>; 638199481Srdivacky 639202878Srdivackydef OR8mi : I8mi<0x0, 640202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 641202878Srdivacky "bis.b\t{$src, $dst}", 642202878Srdivacky [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>; 643202878Srdivackydef OR16mi : I16mi<0x0, 644202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 645202878Srdivacky "bis.w\t{$src, $dst}", 646202878Srdivacky [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>; 647199481Srdivacky 648202878Srdivackydef OR8mm : I8mm<0x0, 649202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 650202878Srdivacky "bis.b\t{$src, $dst}", 651202878Srdivacky [(store (or (i8 (load addr:$dst)), 652202878Srdivacky (i8 (load addr:$src))), addr:$dst)]>; 653202878Srdivackydef OR16mm : I16mm<0x0, 654202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 655202878Srdivacky "bis.w\t{$src, $dst}", 656202878Srdivacky [(store (or (i16 (load addr:$dst)), 657202878Srdivacky (i16 (load addr:$src))), addr:$dst)]>; 658199481Srdivacky} 659199481Srdivacky 660199481Srdivacky// bic does not modify condition codes 661202878Srdivackydef BIC8rr : I8rr<0x0, 662210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 663202878Srdivacky "bic.b\t{$src2, $dst}", 664210299Sed [(set GR8:$dst, (and GR8:$src, (not GR8:$src2)))]>; 665202878Srdivackydef BIC16rr : I16rr<0x0, 666210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 667202878Srdivacky "bic.w\t{$src2, $dst}", 668210299Sed [(set GR16:$dst, (and GR16:$src, (not GR16:$src2)))]>; 669199481Srdivacky 670202878Srdivackydef BIC8rm : I8rm<0x0, 671210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 672202878Srdivacky "bic.b\t{$src2, $dst}", 673210299Sed [(set GR8:$dst, (and GR8:$src, (not (i8 (load addr:$src2)))))]>; 674202878Srdivackydef BIC16rm : I16rm<0x0, 675210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 676202878Srdivacky "bic.w\t{$src2, $dst}", 677210299Sed [(set GR16:$dst, (and GR16:$src, (not (i16 (load addr:$src2)))))]>; 678199481Srdivacky 679210299Sedlet Constraints = "" in { 680202878Srdivackydef BIC8mr : I8mr<0x0, 681202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 682202878Srdivacky "bic.b\t{$src, $dst}", 683202878Srdivacky [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>; 684202878Srdivackydef BIC16mr : I16mr<0x0, 685202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 686202878Srdivacky "bic.w\t{$src, $dst}", 687202878Srdivacky [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>; 688199481Srdivacky 689202878Srdivackydef BIC8mm : I8mm<0x0, 690202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 691202878Srdivacky "bic.b\t{$src, $dst}", 692202878Srdivacky [(store (and (load addr:$dst), 693202878Srdivacky (not (i8 (load addr:$src)))), addr:$dst)]>; 694202878Srdivackydef BIC16mm : I16mm<0x0, 695202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 696202878Srdivacky "bic.w\t{$src, $dst}", 697202878Srdivacky [(store (and (load addr:$dst), 698202878Srdivacky (not (i16 (load addr:$src)))), addr:$dst)]>; 699199481Srdivacky} 700199481Srdivacky 701193323Sedlet isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y 702202878Srdivackydef XOR8rr : I8rr<0x0, 703210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 704202878Srdivacky "xor.b\t{$src2, $dst}", 705210299Sed [(set GR8:$dst, (xor GR8:$src, GR8:$src2)), 706202878Srdivacky (implicit SRW)]>; 707202878Srdivackydef XOR16rr : I16rr<0x0, 708210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 709202878Srdivacky "xor.w\t{$src2, $dst}", 710210299Sed [(set GR16:$dst, (xor GR16:$src, GR16:$src2)), 711202878Srdivacky (implicit SRW)]>; 712193323Sed} 713193323Sed 714202878Srdivackydef XOR8ri : I8ri<0x0, 715210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 716202878Srdivacky "xor.b\t{$src2, $dst}", 717210299Sed [(set GR8:$dst, (xor GR8:$src, imm:$src2)), 718202878Srdivacky (implicit SRW)]>; 719202878Srdivackydef XOR16ri : I16ri<0x0, 720210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 721202878Srdivacky "xor.w\t{$src2, $dst}", 722210299Sed [(set GR16:$dst, (xor GR16:$src, imm:$src2)), 723202878Srdivacky (implicit SRW)]>; 724193323Sed 725202878Srdivackydef XOR8rm : I8rm<0x0, 726210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 727202878Srdivacky "xor.b\t{$src2, $dst}", 728210299Sed [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))), 729202878Srdivacky (implicit SRW)]>; 730202878Srdivackydef XOR16rm : I16rm<0x0, 731210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 732202878Srdivacky "xor.w\t{$src2, $dst}", 733210299Sed [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))), 734202878Srdivacky (implicit SRW)]>; 735193323Sed 736199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, 737210299SedConstraints = "$base = $base_wb, $src = $dst" in { 738202878Srdivackydef XOR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 739202878Srdivacky (outs GR8:$dst, GR16:$base_wb), 740210299Sed (ins GR8:$src, GR16:$base), 741202878Srdivacky "xor.b\t{@$base+, $dst}", []>; 742202878Srdivackydef XOR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 743202878Srdivacky (outs GR16:$dst, GR16:$base_wb), 744210299Sed (ins GR16:$src, GR16:$base), 745202878Srdivacky "xor.w\t{@$base+, $dst}", []>; 746199481Srdivacky} 747199481Srdivacky 748210299Sedlet Constraints = "" in { 749202878Srdivackydef XOR8mr : I8mr<0x0, 750202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 751202878Srdivacky "xor.b\t{$src, $dst}", 752202878Srdivacky [(store (xor (load addr:$dst), GR8:$src), addr:$dst), 753202878Srdivacky (implicit SRW)]>; 754202878Srdivackydef XOR16mr : I16mr<0x0, 755202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 756202878Srdivacky "xor.w\t{$src, $dst}", 757202878Srdivacky [(store (xor (load addr:$dst), GR16:$src), addr:$dst), 758202878Srdivacky (implicit SRW)]>; 759193323Sed 760202878Srdivackydef XOR8mi : I8mi<0x0, 761202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 762202878Srdivacky "xor.b\t{$src, $dst}", 763202878Srdivacky [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst), 764202878Srdivacky (implicit SRW)]>; 765202878Srdivackydef XOR16mi : I16mi<0x0, 766202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 767202878Srdivacky "xor.w\t{$src, $dst}", 768202878Srdivacky [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst), 769202878Srdivacky (implicit SRW)]>; 770193323Sed 771202878Srdivackydef XOR8mm : I8mm<0x0, 772202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 773202878Srdivacky "xor.b\t{$src, $dst}", 774202878Srdivacky [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 775202878Srdivacky (implicit SRW)]>; 776202878Srdivackydef XOR16mm : I16mm<0x0, 777202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 778202878Srdivacky "xor.w\t{$src, $dst}", 779202878Srdivacky [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 780202878Srdivacky (implicit SRW)]>; 781193323Sed} 782193323Sed 783193323Sed 784202878Srdivackydef SUB8rr : I8rr<0x0, 785210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 786202878Srdivacky "sub.b\t{$src2, $dst}", 787210299Sed [(set GR8:$dst, (sub GR8:$src, GR8:$src2)), 788202878Srdivacky (implicit SRW)]>; 789202878Srdivackydef SUB16rr : I16rr<0x0, 790210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 791202878Srdivacky "sub.w\t{$src2, $dst}", 792210299Sed [(set GR16:$dst, (sub GR16:$src, GR16:$src2)), 793202878Srdivacky (implicit SRW)]>; 794193323Sed 795202878Srdivackydef SUB8ri : I8ri<0x0, 796210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 797202878Srdivacky "sub.b\t{$src2, $dst}", 798210299Sed [(set GR8:$dst, (sub GR8:$src, imm:$src2)), 799202878Srdivacky (implicit SRW)]>; 800202878Srdivackydef SUB16ri : I16ri<0x0, 801210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 802202878Srdivacky "sub.w\t{$src2, $dst}", 803210299Sed [(set GR16:$dst, (sub GR16:$src, imm:$src2)), 804202878Srdivacky (implicit SRW)]>; 805193323Sed 806202878Srdivackydef SUB8rm : I8rm<0x0, 807210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 808202878Srdivacky "sub.b\t{$src2, $dst}", 809210299Sed [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))), 810202878Srdivacky (implicit SRW)]>; 811202878Srdivackydef SUB16rm : I16rm<0x0, 812210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 813202878Srdivacky "sub.w\t{$src2, $dst}", 814210299Sed [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))), 815202878Srdivacky (implicit SRW)]>; 816193323Sed 817199481Srdivackylet mayLoad = 1, hasExtraDefRegAllocReq = 1, 818210299SedConstraints = "$base = $base_wb, $src = $dst" in { 819202878Srdivackydef SUB8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, 820202878Srdivacky (outs GR8:$dst, GR16:$base_wb), 821210299Sed (ins GR8:$src, GR16:$base), 822202878Srdivacky "sub.b\t{@$base+, $dst}", []>; 823202878Srdivackydef SUB16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, 824202878Srdivacky (outs GR16:$dst, GR16:$base_wb), 825210299Sed (ins GR16:$src, GR16:$base), 826199481Srdivacky "sub.w\t{@$base+, $dst}", []>; 827199481Srdivacky} 828199481Srdivacky 829210299Sedlet Constraints = "" in { 830202878Srdivackydef SUB8mr : I8mr<0x0, 831202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 832202878Srdivacky "sub.b\t{$src, $dst}", 833202878Srdivacky [(store (sub (load addr:$dst), GR8:$src), addr:$dst), 834202878Srdivacky (implicit SRW)]>; 835202878Srdivackydef SUB16mr : I16mr<0x0, 836202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 837202878Srdivacky "sub.w\t{$src, $dst}", 838202878Srdivacky [(store (sub (load addr:$dst), GR16:$src), addr:$dst), 839202878Srdivacky (implicit SRW)]>; 840193323Sed 841202878Srdivackydef SUB8mi : I8mi<0x0, 842202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 843202878Srdivacky "sub.b\t{$src, $dst}", 844202878Srdivacky [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst), 845202878Srdivacky (implicit SRW)]>; 846202878Srdivackydef SUB16mi : I16mi<0x0, 847202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 848202878Srdivacky "sub.w\t{$src, $dst}", 849202878Srdivacky [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst), 850202878Srdivacky (implicit SRW)]>; 851193323Sed 852202878Srdivackydef SUB8mm : I8mm<0x0, 853202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 854202878Srdivacky "sub.b\t{$src, $dst}", 855202878Srdivacky [(store (sub (load addr:$dst), 856202878Srdivacky (i8 (load addr:$src))), addr:$dst), 857202878Srdivacky (implicit SRW)]>; 858202878Srdivackydef SUB16mm : I16mm<0x0, 859202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 860202878Srdivacky "sub.w\t{$src, $dst}", 861202878Srdivacky [(store (sub (load addr:$dst), 862202878Srdivacky (i16 (load addr:$src))), addr:$dst), 863202878Srdivacky (implicit SRW)]>; 864193323Sed} 865193323Sed 866193323Sedlet Uses = [SRW] in { 867202878Srdivackydef SBC8rr : I8rr<0x0, 868210299Sed (outs GR8:$dst), (ins GR8:$src, GR8:$src2), 869202878Srdivacky "subc.b\t{$src2, $dst}", 870210299Sed [(set GR8:$dst, (sube GR8:$src, GR8:$src2)), 871202878Srdivacky (implicit SRW)]>; 872202878Srdivackydef SBC16rr : I16rr<0x0, 873210299Sed (outs GR16:$dst), (ins GR16:$src, GR16:$src2), 874202878Srdivacky "subc.w\t{$src2, $dst}", 875210299Sed [(set GR16:$dst, (sube GR16:$src, GR16:$src2)), 876202878Srdivacky (implicit SRW)]>; 877193323Sed 878202878Srdivackydef SBC8ri : I8ri<0x0, 879210299Sed (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), 880202878Srdivacky "subc.b\t{$src2, $dst}", 881210299Sed [(set GR8:$dst, (sube GR8:$src, imm:$src2)), 882202878Srdivacky (implicit SRW)]>; 883202878Srdivackydef SBC16ri : I16ri<0x0, 884210299Sed (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), 885202878Srdivacky "subc.w\t{$src2, $dst}", 886210299Sed [(set GR16:$dst, (sube GR16:$src, imm:$src2)), 887202878Srdivacky (implicit SRW)]>; 888193323Sed 889202878Srdivackydef SBC8rm : I8rm<0x0, 890210299Sed (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), 891202878Srdivacky "subc.b\t{$src2, $dst}", 892210299Sed [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))), 893202878Srdivacky (implicit SRW)]>; 894202878Srdivackydef SBC16rm : I16rm<0x0, 895210299Sed (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), 896202878Srdivacky "subc.w\t{$src2, $dst}", 897210299Sed [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))), 898202878Srdivacky (implicit SRW)]>; 899193323Sed 900210299Sedlet Constraints = "" in { 901202878Srdivackydef SBC8mr : I8mr<0x0, 902202878Srdivacky (outs), (ins memdst:$dst, GR8:$src), 903202878Srdivacky "subc.b\t{$src, $dst}", 904202878Srdivacky [(store (sube (load addr:$dst), GR8:$src), addr:$dst), 905202878Srdivacky (implicit SRW)]>; 906202878Srdivackydef SBC16mr : I16mr<0x0, 907202878Srdivacky (outs), (ins memdst:$dst, GR16:$src), 908202878Srdivacky "subc.w\t{$src, $dst}", 909202878Srdivacky [(store (sube (load addr:$dst), GR16:$src), addr:$dst), 910202878Srdivacky (implicit SRW)]>; 911193323Sed 912202878Srdivackydef SBC8mi : I8mi<0x0, 913202878Srdivacky (outs), (ins memdst:$dst, i8imm:$src), 914202878Srdivacky "subc.b\t{$src, $dst}", 915202878Srdivacky [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst), 916202878Srdivacky (implicit SRW)]>; 917202878Srdivackydef SBC16mi : I16mi<0x0, 918202878Srdivacky (outs), (ins memdst:$dst, i16imm:$src), 919202878Srdivacky "subc.w\t{$src, $dst}", 920202878Srdivacky [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst), 921202878Srdivacky (implicit SRW)]>; 922193323Sed 923202878Srdivackydef SBC8mm : I8mm<0x0, 924202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 925202878Srdivacky "subc.b\t{$src, $dst}", 926202878Srdivacky [(store (sube (load addr:$dst), 927202878Srdivacky (i8 (load addr:$src))), addr:$dst), 928202878Srdivacky (implicit SRW)]>; 929202878Srdivackydef SBC16mm : I16mm<0x0, 930202878Srdivacky (outs), (ins memdst:$dst, memsrc:$src), 931202878Srdivacky "subc.w\t{$src, $dst}", 932202878Srdivacky [(store (sube (load addr:$dst), 933202878Srdivacky (i16 (load addr:$src))), addr:$dst), 934202878Srdivacky (implicit SRW)]>; 935193323Sed} 936193323Sed 937193323Sed} // Uses = [SRW] 938193323Sed 939202878Srdivacky// FIXME: memory variant! 940202878Srdivackydef SAR8r1 : II8r<0x0, 941202878Srdivacky (outs GR8:$dst), (ins GR8:$src), 942202878Srdivacky "rra.b\t$dst", 943202878Srdivacky [(set GR8:$dst, (MSP430rra GR8:$src)), 944202878Srdivacky (implicit SRW)]>; 945202878Srdivackydef SAR16r1 : II16r<0x0, 946202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 947202878Srdivacky "rra.w\t$dst", 948202878Srdivacky [(set GR16:$dst, (MSP430rra GR16:$src)), 949202878Srdivacky (implicit SRW)]>; 950193323Sed 951202878Srdivackydef SHL8r1 : I8rr<0x0, 952202878Srdivacky (outs GR8:$dst), (ins GR8:$src), 953202878Srdivacky "rla.b\t$dst", 954202878Srdivacky [(set GR8:$dst, (MSP430rla GR8:$src)), 955202878Srdivacky (implicit SRW)]>; 956202878Srdivackydef SHL16r1 : I16rr<0x0, 957202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 958202878Srdivacky "rla.w\t$dst", 959202878Srdivacky [(set GR16:$dst, (MSP430rla GR16:$src)), 960202878Srdivacky (implicit SRW)]>; 961193323Sed 962193323Seddef SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src), 963193323Sed "clrc\n\t" 964193323Sed "rrc.b\t$dst", 965193323Sed [(set GR8:$dst, (MSP430rrc GR8:$src)), 966193323Sed (implicit SRW)]>; 967193323Seddef SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src), 968193323Sed "clrc\n\t" 969193323Sed "rrc.w\t$dst", 970193323Sed [(set GR16:$dst, (MSP430rrc GR16:$src)), 971193323Sed (implicit SRW)]>; 972193323Sed 973202878Srdivacky// FIXME: Memory sext's ? 974202878Srdivackydef SEXT16r : II16r<0x0, 975202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 976202878Srdivacky "sxt\t$dst", 977202878Srdivacky [(set GR16:$dst, (sext_inreg GR16:$src, i8)), 978202878Srdivacky (implicit SRW)]>; 979193323Sed 980193323Sed} // Defs = [SRW] 981193323Sed 982202878Srdivackydef ZEXT16r : I8rr<0x0, 983202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 984202878Srdivacky "mov.b\t{$src, $dst}", 985202878Srdivacky [(set GR16:$dst, (zext (trunc GR16:$src)))]>; 986199481Srdivacky 987202878Srdivacky// FIXME: Memory bitswaps? 988202878Srdivackydef SWPB16r : II16r<0x0, 989202878Srdivacky (outs GR16:$dst), (ins GR16:$src), 990202878Srdivacky "swpb\t$dst", 991202878Srdivacky [(set GR16:$dst, (bswap GR16:$src))]>; 992193323Sed 993210299Sed} // Constraints = "$src = $dst" 994193323Sed 995193323Sed// Integer comparisons 996193323Sedlet Defs = [SRW] in { 997202878Srdivackydef CMP8rr : I8rr<0x0, 998210299Sed (outs), (ins GR8:$src, GR8:$src2), 999210299Sed "cmp.b\t{$src2, $src}", 1000210299Sed [(MSP430cmp GR8:$src, GR8:$src2), (implicit SRW)]>; 1001202878Srdivackydef CMP16rr : I16rr<0x0, 1002210299Sed (outs), (ins GR16:$src, GR16:$src2), 1003210299Sed "cmp.w\t{$src2, $src}", 1004210299Sed [(MSP430cmp GR16:$src, GR16:$src2), (implicit SRW)]>; 1005193323Sed 1006202878Srdivackydef CMP8ri : I8ri<0x0, 1007210299Sed (outs), (ins GR8:$src, i8imm:$src2), 1008210299Sed "cmp.b\t{$src2, $src}", 1009210299Sed [(MSP430cmp GR8:$src, imm:$src2), (implicit SRW)]>; 1010202878Srdivackydef CMP16ri : I16ri<0x0, 1011210299Sed (outs), (ins GR16:$src, i16imm:$src2), 1012210299Sed "cmp.w\t{$src2, $src}", 1013210299Sed [(MSP430cmp GR16:$src, imm:$src2), (implicit SRW)]>; 1014193323Sed 1015202878Srdivackydef CMP8mi : I8mi<0x0, 1016210299Sed (outs), (ins memsrc:$src, i8imm:$src2), 1017210299Sed "cmp.b\t{$src2, $src}", 1018210299Sed [(MSP430cmp (load addr:$src), 1019202878Srdivacky (i8 imm:$src2)), (implicit SRW)]>; 1020202878Srdivackydef CMP16mi : I16mi<0x0, 1021210299Sed (outs), (ins memsrc:$src, i16imm:$src2), 1022210299Sed "cmp.w\t{$src2, $src}", 1023210299Sed [(MSP430cmp (load addr:$src), 1024202878Srdivacky (i16 imm:$src2)), (implicit SRW)]>; 1025193323Sed 1026202878Srdivackydef CMP8rm : I8rm<0x0, 1027210299Sed (outs), (ins GR8:$src, memsrc:$src2), 1028210299Sed "cmp.b\t{$src2, $src}", 1029210299Sed [(MSP430cmp GR8:$src, (load addr:$src2)), 1030202878Srdivacky (implicit SRW)]>; 1031202878Srdivackydef CMP16rm : I16rm<0x0, 1032210299Sed (outs), (ins GR16:$src, memsrc:$src2), 1033210299Sed "cmp.w\t{$src2, $src}", 1034210299Sed [(MSP430cmp GR16:$src, (load addr:$src2)), 1035202878Srdivacky (implicit SRW)]>; 1036193323Sed 1037202878Srdivackydef CMP8mr : I8mr<0x0, 1038210299Sed (outs), (ins memsrc:$src, GR8:$src2), 1039210299Sed "cmp.b\t{$src2, $src}", 1040210299Sed [(MSP430cmp (load addr:$src), GR8:$src2), 1041202878Srdivacky (implicit SRW)]>; 1042202878Srdivackydef CMP16mr : I16mr<0x0, 1043210299Sed (outs), (ins memsrc:$src, GR16:$src2), 1044210299Sed "cmp.w\t{$src2, $src}", 1045210299Sed [(MSP430cmp (load addr:$src), GR16:$src2), 1046202878Srdivacky (implicit SRW)]>; 1047193323Sed 1048200581Srdivacky 1049200581Srdivacky// BIT TESTS, just sets condition codes 1050200581Srdivacky// Note that the C condition is set differently than when using CMP. 1051200581Srdivackylet isCommutable = 1 in { 1052202878Srdivackydef BIT8rr : I8rr<0x0, 1053210299Sed (outs), (ins GR8:$src, GR8:$src2), 1054210299Sed "bit.b\t{$src2, $src}", 1055210299Sed [(MSP430cmp (and_su GR8:$src, GR8:$src2), 0), 1056202878Srdivacky (implicit SRW)]>; 1057202878Srdivackydef BIT16rr : I16rr<0x0, 1058210299Sed (outs), (ins GR16:$src, GR16:$src2), 1059210299Sed "bit.w\t{$src2, $src}", 1060210299Sed [(MSP430cmp (and_su GR16:$src, GR16:$src2), 0), 1061202878Srdivacky (implicit SRW)]>; 1062200581Srdivacky} 1063202878Srdivackydef BIT8ri : I8ri<0x0, 1064210299Sed (outs), (ins GR8:$src, i8imm:$src2), 1065210299Sed "bit.b\t{$src2, $src}", 1066210299Sed [(MSP430cmp (and_su GR8:$src, imm:$src2), 0), 1067202878Srdivacky (implicit SRW)]>; 1068202878Srdivackydef BIT16ri : I16ri<0x0, 1069210299Sed (outs), (ins GR16:$src, i16imm:$src2), 1070210299Sed "bit.w\t{$src2, $src}", 1071210299Sed [(MSP430cmp (and_su GR16:$src, imm:$src2), 0), 1072202878Srdivacky (implicit SRW)]>; 1073200581Srdivacky 1074202878Srdivackydef BIT8rm : I8rm<0x0, 1075210299Sed (outs), (ins GR8:$src, memdst:$src2), 1076210299Sed "bit.b\t{$src2, $src}", 1077210299Sed [(MSP430cmp (and_su GR8:$src, (load addr:$src2)), 0), 1078202878Srdivacky (implicit SRW)]>; 1079202878Srdivackydef BIT16rm : I16rm<0x0, 1080210299Sed (outs), (ins GR16:$src, memdst:$src2), 1081210299Sed "bit.w\t{$src2, $src}", 1082210299Sed [(MSP430cmp (and_su GR16:$src, (load addr:$src2)), 0), 1083202878Srdivacky (implicit SRW)]>; 1084200581Srdivacky 1085202878Srdivackydef BIT8mr : I8mr<0x0, 1086210299Sed (outs), (ins memsrc:$src, GR8:$src2), 1087210299Sed "bit.b\t{$src2, $src}", 1088210299Sed [(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0), 1089202878Srdivacky (implicit SRW)]>; 1090202878Srdivackydef BIT16mr : I16mr<0x0, 1091210299Sed (outs), (ins memsrc:$src, GR16:$src2), 1092210299Sed "bit.w\t{$src2, $src}", 1093210299Sed [(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0), 1094202878Srdivacky (implicit SRW)]>; 1095200581Srdivacky 1096202878Srdivackydef BIT8mi : I8mi<0x0, 1097210299Sed (outs), (ins memsrc:$src, i8imm:$src2), 1098210299Sed "bit.b\t{$src2, $src}", 1099210299Sed [(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0), 1100202878Srdivacky (implicit SRW)]>; 1101202878Srdivackydef BIT16mi : I16mi<0x0, 1102210299Sed (outs), (ins memsrc:$src, i16imm:$src2), 1103210299Sed "bit.w\t{$src2, $src}", 1104210299Sed [(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0), 1105202878Srdivacky (implicit SRW)]>; 1106200581Srdivacky 1107202878Srdivackydef BIT8mm : I8mm<0x0, 1108210299Sed (outs), (ins memsrc:$src, memsrc:$src2), 1109210299Sed "bit.b\t{$src2, $src}", 1110210299Sed [(MSP430cmp (and_su (i8 (load addr:$src)), 1111202878Srdivacky (load addr:$src2)), 1112202878Srdivacky 0), 1113200581Srdivacky (implicit SRW)]>; 1114202878Srdivackydef BIT16mm : I16mm<0x0, 1115210299Sed (outs), (ins memsrc:$src, memsrc:$src2), 1116210299Sed "bit.w\t{$src2, $src}", 1117210299Sed [(MSP430cmp (and_su (i16 (load addr:$src)), 1118202878Srdivacky (load addr:$src2)), 1119202878Srdivacky 0), 1120202878Srdivacky (implicit SRW)]>; 1121193323Sed} // Defs = [SRW] 1122193323Sed 1123193323Sed//===----------------------------------------------------------------------===// 1124193323Sed// Non-Instruction Patterns 1125193323Sed 1126193323Sed// extload 1127193323Seddef : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1128193323Sed 1129193323Sed// anyext 1130202878Srdivackydef : Pat<(i16 (anyext GR8:$src)), 1131202878Srdivacky (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 1132193323Sed 1133193323Sed// truncs 1134193323Seddef : Pat<(i8 (trunc GR16:$src)), 1135193323Sed (EXTRACT_SUBREG GR16:$src, subreg_8bit)>; 1136193323Sed 1137193323Sed// GlobalAddress, ExternalSymbol 1138193323Seddef : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>; 1139193323Seddef : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>; 1140207618Srdivackydef : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>; 1141193323Sed 1142210299Seddef : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)), 1143210299Sed (ADD16ri GR16:$src, tglobaladdr:$src2)>; 1144210299Seddef : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)), 1145210299Sed (ADD16ri GR16:$src, texternalsym:$src2)>; 1146210299Seddef : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)), 1147210299Sed (ADD16ri GR16:$src, tblockaddress:$src2)>; 1148193323Sed 1149193323Seddef : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst), 1150193323Sed (MOV16mi addr:$dst, tglobaladdr:$src)>; 1151193323Seddef : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst), 1152193323Sed (MOV16mi addr:$dst, texternalsym:$src)>; 1153207618Srdivackydef : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst), 1154207618Srdivacky (MOV16mi addr:$dst, tblockaddress:$src)>; 1155193323Sed 1156193323Sed// calls 1157193323Seddef : Pat<(MSP430call (i16 tglobaladdr:$dst)), 1158193323Sed (CALLi tglobaladdr:$dst)>; 1159193323Seddef : Pat<(MSP430call (i16 texternalsym:$dst)), 1160193323Sed (CALLi texternalsym:$dst)>; 1161193323Sed 1162193323Sed// add and sub always produce carry 1163210299Seddef : Pat<(addc GR16:$src, GR16:$src2), 1164210299Sed (ADD16rr GR16:$src, GR16:$src2)>; 1165210299Seddef : Pat<(addc GR16:$src, (load addr:$src2)), 1166210299Sed (ADD16rm GR16:$src, addr:$src2)>; 1167210299Seddef : Pat<(addc GR16:$src, imm:$src2), 1168210299Sed (ADD16ri GR16:$src, imm:$src2)>; 1169193323Seddef : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst), 1170193323Sed (ADD16mr addr:$dst, GR16:$src)>; 1171193323Seddef : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 1172193323Sed (ADD16mm addr:$dst, addr:$src)>; 1173193323Sed 1174210299Seddef : Pat<(addc GR8:$src, GR8:$src2), 1175210299Sed (ADD8rr GR8:$src, GR8:$src2)>; 1176210299Seddef : Pat<(addc GR8:$src, (load addr:$src2)), 1177210299Sed (ADD8rm GR8:$src, addr:$src2)>; 1178210299Seddef : Pat<(addc GR8:$src, imm:$src2), 1179210299Sed (ADD8ri GR8:$src, imm:$src2)>; 1180193323Seddef : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst), 1181193323Sed (ADD8mr addr:$dst, GR8:$src)>; 1182193323Seddef : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 1183193323Sed (ADD8mm addr:$dst, addr:$src)>; 1184193323Sed 1185210299Seddef : Pat<(subc GR16:$src, GR16:$src2), 1186210299Sed (SUB16rr GR16:$src, GR16:$src2)>; 1187210299Seddef : Pat<(subc GR16:$src, (load addr:$src2)), 1188210299Sed (SUB16rm GR16:$src, addr:$src2)>; 1189210299Seddef : Pat<(subc GR16:$src, imm:$src2), 1190210299Sed (SUB16ri GR16:$src, imm:$src2)>; 1191193323Seddef : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst), 1192193323Sed (SUB16mr addr:$dst, GR16:$src)>; 1193193323Seddef : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 1194193323Sed (SUB16mm addr:$dst, addr:$src)>; 1195193323Sed 1196210299Seddef : Pat<(subc GR8:$src, GR8:$src2), 1197210299Sed (SUB8rr GR8:$src, GR8:$src2)>; 1198210299Seddef : Pat<(subc GR8:$src, (load addr:$src2)), 1199210299Sed (SUB8rm GR8:$src, addr:$src2)>; 1200210299Seddef : Pat<(subc GR8:$src, imm:$src2), 1201210299Sed (SUB8ri GR8:$src, imm:$src2)>; 1202193323Seddef : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst), 1203193323Sed (SUB8mr addr:$dst, GR8:$src)>; 1204193323Seddef : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 1205193323Sed (SUB8mm addr:$dst, addr:$src)>; 1206199481Srdivacky 1207199481Srdivacky// peephole patterns 1208199481Srdivackydef : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; 1209210299Seddef : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0), 1210210299Sed (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit), 1211200581Srdivacky (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>; 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