HexagonSchedule.td revision 249423 
1//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Functional Units
11def LSUNIT    : FuncUnit; // SLOT0
12def LUNIT     : FuncUnit; // SLOT1
13def MUNIT     : FuncUnit; // SLOT2
14def SUNIT     : FuncUnit; // SLOT3
15def LOOPUNIT  : FuncUnit;
16
17// Itinerary classes
18def ALU32     : InstrItinClass;
19def ALU64     : InstrItinClass;
20def CR        : InstrItinClass;
21def J         : InstrItinClass;
22def JR        : InstrItinClass;
23def LD        : InstrItinClass;
24def LD0       : InstrItinClass;
25def M         : InstrItinClass;
26def ST        : InstrItinClass;
27def ST0       : InstrItinClass;
28def S         : InstrItinClass;
29def SYS       : InstrItinClass;
30def ENDLOOP   : InstrItinClass;
31def PSEUDO    : InstrItinClass;
32def PSEUDOM   : InstrItinClass;
33
34def HexagonItineraries :
35      ProcessorItineraries<[LSUNIT, LUNIT, MUNIT, SUNIT, LOOPUNIT], [], [
36        InstrItinData<ALU32  , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
37        InstrItinData<ALU64  , [InstrStage<1, [MUNIT, SUNIT]>]>,
38        InstrItinData<CR     , [InstrStage<1, [SUNIT]>]>,
39        InstrItinData<J      , [InstrStage<1, [SUNIT, MUNIT]>]>,
40        InstrItinData<JR     , [InstrStage<1, [MUNIT]>]>,
41        InstrItinData<LD     , [InstrStage<1, [LUNIT, LSUNIT]>]>,
42        InstrItinData<LD0    , [InstrStage<1, [LSUNIT]>]>,
43        InstrItinData<M      , [InstrStage<1, [MUNIT, SUNIT]>]>,
44        InstrItinData<ST     , [InstrStage<1, [LSUNIT]>]>,
45        InstrItinData<ST0    , [InstrStage<1, [LSUNIT]>]>,
46        InstrItinData<S      , [InstrStage<1, [SUNIT, MUNIT]>]>,
47        InstrItinData<SYS    , [InstrStage<1, [LSUNIT]>]>,
48        InstrItinData<ENDLOOP, [InstrStage<1, [LOOPUNIT]>]>,
49        InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
50        InstrItinData<PSEUDOM, [InstrStage<1, [MUNIT, SUNIT], 0>,
51                                InstrStage<1, [MUNIT, SUNIT]>]>
52      ]>;
53
54def HexagonModel : SchedMachineModel {
55  // Max issue per cycle == bundle width.
56  let IssueWidth = 4;
57  let Itineraries = HexagonItineraries;
58  let LoadLatency = 1;
59}
60
61//===----------------------------------------------------------------------===//
62// V4 Machine Info +
63//===----------------------------------------------------------------------===//
64
65include "HexagonScheduleV4.td"
66
67//===----------------------------------------------------------------------===//
68// V4 Machine Info -
69//===----------------------------------------------------------------------===//
70