ARMFixupKinds.h revision 226584
1226584Sdim//===-- ARM/ARMFixupKinds.h - ARM Specific Fixup Entries --------*- C++ -*-===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim 10226584Sdim#ifndef LLVM_ARM_ARMFIXUPKINDS_H 11226584Sdim#define LLVM_ARM_ARMFIXUPKINDS_H 12226584Sdim 13226584Sdim#include "llvm/MC/MCFixup.h" 14226584Sdim 15226584Sdimnamespace llvm { 16226584Sdimnamespace ARM { 17226584Sdimenum Fixups { 18226584Sdim // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol 19226584Sdim // addresses 20226584Sdim fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind, 21226584Sdim 22226584Sdim // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with 23226584Sdim // the 16-bit halfwords reordered. 24226584Sdim fixup_t2_ldst_pcrel_12, 25226584Sdim 26226584Sdim // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses 27226584Sdim // used in VFP instructions where the lower 2 bits are not encoded 28226584Sdim // (so it's encoded as an 8-bit immediate). 29226584Sdim fixup_arm_pcrel_10, 30226584Sdim // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for 31226584Sdim // the short-swapped encoding of Thumb2 instructions. 32226584Sdim fixup_t2_pcrel_10, 33226584Sdim // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol 34226584Sdim // addresses where the lower 2 bits are not encoded (so it's encoded as an 35226584Sdim // 8-bit immediate). 36226584Sdim fixup_thumb_adr_pcrel_10, 37226584Sdim // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR 38226584Sdim // instruction. 39226584Sdim fixup_arm_adr_pcrel_12, 40226584Sdim // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR 41226584Sdim // instruction. 42226584Sdim fixup_t2_adr_pcrel_12, 43226584Sdim // fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch 44226584Sdim // instructions. 45226584Sdim fixup_arm_condbranch, 46226584Sdim // fixup_arm_uncondbranch - 24-bit PC relative relocation for 47226584Sdim // branch instructions. (unconditional) 48226584Sdim fixup_arm_uncondbranch, 49226584Sdim // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct 50226584Sdim // uconditional branch instructions. 51226584Sdim fixup_t2_condbranch, 52226584Sdim // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct 53226584Sdim // branch unconditional branch instructions. 54226584Sdim fixup_t2_uncondbranch, 55226584Sdim 56226584Sdim // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions. 57226584Sdim fixup_arm_thumb_br, 58226584Sdim 59226584Sdim // fixup_arm_thumb_bl - Fixup for Thumb BL instructions. 60226584Sdim fixup_arm_thumb_bl, 61226584Sdim 62226584Sdim // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions. 63226584Sdim fixup_arm_thumb_blx, 64226584Sdim 65226584Sdim // fixup_arm_thumb_cb - Fixup for Thumb branch instructions. 66226584Sdim fixup_arm_thumb_cb, 67226584Sdim 68226584Sdim // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs. 69226584Sdim fixup_arm_thumb_cp, 70226584Sdim 71226584Sdim // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions. 72226584Sdim fixup_arm_thumb_bcc, 73226584Sdim 74226584Sdim // The next two are for the movt/movw pair 75226584Sdim // the 16bit imm field are split into imm{15-12} and imm{11-0} 76226584Sdim fixup_arm_movt_hi16, // :upper16: 77226584Sdim fixup_arm_movw_lo16, // :lower16: 78226584Sdim fixup_t2_movt_hi16, // :upper16: 79226584Sdim fixup_t2_movw_lo16, // :lower16: 80226584Sdim 81226584Sdim // It is possible to create an "immediate" that happens to be pcrel. 82226584Sdim // movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8) 83226584Sdim // result in different reloc tags than the above two. 84226584Sdim // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC 85226584Sdim fixup_arm_movt_hi16_pcrel, // :upper16: 86226584Sdim fixup_arm_movw_lo16_pcrel, // :lower16: 87226584Sdim fixup_t2_movt_hi16_pcrel, // :upper16: 88226584Sdim fixup_t2_movw_lo16_pcrel, // :lower16: 89226584Sdim 90226584Sdim // Marker 91226584Sdim LastTargetFixupKind, 92226584Sdim NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind 93226584Sdim}; 94226584Sdim} 95226584Sdim} 96226584Sdim 97226584Sdim#endif 98