1234353Sdim//===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim 10226584Sdim#ifndef LLVM_ARM_ARMFIXUPKINDS_H 11226584Sdim#define LLVM_ARM_ARMFIXUPKINDS_H 12226584Sdim 13226584Sdim#include "llvm/MC/MCFixup.h" 14226584Sdim 15226584Sdimnamespace llvm { 16226584Sdimnamespace ARM { 17226584Sdimenum Fixups { 18226584Sdim // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol 19226584Sdim // addresses 20226584Sdim fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind, 21226584Sdim 22226584Sdim // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with 23226584Sdim // the 16-bit halfwords reordered. 24226584Sdim fixup_t2_ldst_pcrel_12, 25226584Sdim 26234353Sdim // fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol 27234353Sdim // addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded. 28234353Sdim fixup_arm_pcrel_10_unscaled, 29226584Sdim // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses 30226584Sdim // used in VFP instructions where the lower 2 bits are not encoded 31226584Sdim // (so it's encoded as an 8-bit immediate). 32226584Sdim fixup_arm_pcrel_10, 33226584Sdim // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for 34226584Sdim // the short-swapped encoding of Thumb2 instructions. 35226584Sdim fixup_t2_pcrel_10, 36226584Sdim // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol 37226584Sdim // addresses where the lower 2 bits are not encoded (so it's encoded as an 38226584Sdim // 8-bit immediate). 39226584Sdim fixup_thumb_adr_pcrel_10, 40226584Sdim // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR 41226584Sdim // instruction. 42226584Sdim fixup_arm_adr_pcrel_12, 43226584Sdim // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR 44226584Sdim // instruction. 45226584Sdim fixup_t2_adr_pcrel_12, 46226584Sdim // fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch 47226584Sdim // instructions. 48226584Sdim fixup_arm_condbranch, 49226584Sdim // fixup_arm_uncondbranch - 24-bit PC relative relocation for 50226584Sdim // branch instructions. (unconditional) 51226584Sdim fixup_arm_uncondbranch, 52226584Sdim // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct 53226584Sdim // uconditional branch instructions. 54226584Sdim fixup_t2_condbranch, 55226584Sdim // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct 56226584Sdim // branch unconditional branch instructions. 57226584Sdim fixup_t2_uncondbranch, 58226584Sdim 59226584Sdim // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions. 60226584Sdim fixup_arm_thumb_br, 61226584Sdim 62234353Sdim // The following fixups handle the ARM BL instructions. These can be 63234353Sdim // conditionalised; however, the ARM ELF ABI requires a different relocation 64234353Sdim // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that 65234353Sdim // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has 66234353Sdim // no conditional version; R_ARM_JUMP24 would have to insert a veneer. 67234353Sdim // 68234353Sdim // MachO does not draw a distinction between the two cases, so it will treat 69234353Sdim // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups. 70234353Sdim 71234353Sdim // fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions. 72234353Sdim fixup_arm_uncondbl, 73234353Sdim 74234353Sdim // fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial 75234353Sdim // conditionalisation. 76234353Sdim fixup_arm_condbl, 77234353Sdim 78234353Sdim // fixup_arm_blx - Fixup for ARM BLX instructions. 79234353Sdim fixup_arm_blx, 80234353Sdim 81226584Sdim // fixup_arm_thumb_bl - Fixup for Thumb BL instructions. 82226584Sdim fixup_arm_thumb_bl, 83226584Sdim 84226584Sdim // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions. 85226584Sdim fixup_arm_thumb_blx, 86226584Sdim 87226584Sdim // fixup_arm_thumb_cb - Fixup for Thumb branch instructions. 88226584Sdim fixup_arm_thumb_cb, 89226584Sdim 90226584Sdim // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs. 91226584Sdim fixup_arm_thumb_cp, 92226584Sdim 93226584Sdim // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions. 94226584Sdim fixup_arm_thumb_bcc, 95226584Sdim 96226584Sdim // The next two are for the movt/movw pair 97226584Sdim // the 16bit imm field are split into imm{15-12} and imm{11-0} 98226584Sdim fixup_arm_movt_hi16, // :upper16: 99226584Sdim fixup_arm_movw_lo16, // :lower16: 100226584Sdim fixup_t2_movt_hi16, // :upper16: 101226584Sdim fixup_t2_movw_lo16, // :lower16: 102226584Sdim 103226584Sdim // It is possible to create an "immediate" that happens to be pcrel. 104226584Sdim // movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8) 105226584Sdim // result in different reloc tags than the above two. 106226584Sdim // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC 107226584Sdim fixup_arm_movt_hi16_pcrel, // :upper16: 108226584Sdim fixup_arm_movw_lo16_pcrel, // :lower16: 109226584Sdim fixup_t2_movt_hi16_pcrel, // :upper16: 110226584Sdim fixup_t2_movw_lo16_pcrel, // :lower16: 111226584Sdim 112226584Sdim // Marker 113226584Sdim LastTargetFixupKind, 114226584Sdim NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind 115226584Sdim}; 116226584Sdim} 117226584Sdim} 118226584Sdim 119226584Sdim#endif 120