ARMCodeEmitter.cpp revision 234353
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMBaseInstrInfo.h" 19#include "ARMRelocations.h" 20#include "ARMSubtarget.h" 21#include "ARMTargetMachine.h" 22#include "MCTargetDesc/ARMAddressingModes.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMBaseInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMBaseInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const MCInstrDesc &MCID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 unsigned getAddrModeSBit(const MachineInstr &MI, 105 const MCInstrDesc &MCID) const; 106 107 void emitDataProcessingInstruction(const MachineInstr &MI, 108 unsigned ImplicitRd = 0, 109 unsigned ImplicitRn = 0); 110 111 void emitLoadStoreInstruction(const MachineInstr &MI, 112 unsigned ImplicitRd = 0, 113 unsigned ImplicitRn = 0); 114 115 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 116 unsigned ImplicitRn = 0); 117 118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 119 120 void emitMulFrmInstruction(const MachineInstr &MI); 121 122 void emitExtendInstruction(const MachineInstr &MI); 123 124 void emitMiscArithInstruction(const MachineInstr &MI); 125 126 void emitSaturateInstruction(const MachineInstr &MI); 127 128 void emitBranchInstruction(const MachineInstr &MI); 129 130 void emitInlineJumpTable(unsigned JTIndex); 131 132 void emitMiscBranchInstruction(const MachineInstr &MI); 133 134 void emitVFPArithInstruction(const MachineInstr &MI); 135 136 void emitVFPConversionInstruction(const MachineInstr &MI); 137 138 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 141 142 void emitNEONLaneInstruction(const MachineInstr &MI); 143 void emitNEONDupInstruction(const MachineInstr &MI); 144 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 145 void emitNEON2RegInstruction(const MachineInstr &MI); 146 void emitNEON3RegInstruction(const MachineInstr &MI); 147 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 149 /// operand requires relocation, record the relocation and return zero. 150 unsigned getMachineOpValue(const MachineInstr &MI, 151 const MachineOperand &MO) const; 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 154 } 155 156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 157 // TableGen'erated getBinaryCodeForInstr() function to encode any 158 // operand values, instead querying getMachineOpValue() directly for 159 // each operand it needs to encode. Thus, any of the new encoder 160 // helper functions can simply return 0 as the values the return 161 // are already handled elsewhere. They are placeholders to allow this 162 // encoder to continue to function until the MC encoder is sufficiently 163 // far along that this one can be eliminated entirely. 164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 165 const { return 0; } 166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 167 const { return 0; } 168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 169 const { return 0; } 170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 171 const { return 0; } 172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 179 const { return 0; } 180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 181 const { return 0; } 182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 189 unsigned Op) const { return 0; } 190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 199 const { return 0; } 200 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 211 const { return 0; } 212 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) 217 const { return 0; } 218 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 221 const { return 0; } 222 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 225 const { return 0; } 226 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 229 const { return 0; } 230 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 231 unsigned Op) 232 const { return 0; } 233 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 234 const { return 0; } 235 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 236 const { return 0; } 237 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 238 unsigned Op) const { return 0; } 239 unsigned getSsatBitPosValue(const MachineInstr &MI, 240 unsigned Op) const { return 0; } 241 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 242 const {return 0; } 243 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 244 const { return 0; } 245 246 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 247 const { 248 // {17-13} = reg 249 // {12} = (U)nsigned (add == '1', sub == '0') 250 // {11-0} = imm12 251 const MachineOperand &MO = MI.getOperand(Op); 252 const MachineOperand &MO1 = MI.getOperand(Op + 1); 253 if (!MO.isReg()) { 254 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 255 return 0; 256 } 257 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 258 int32_t Imm12 = MO1.getImm(); 259 uint32_t Binary; 260 Binary = Imm12 & 0xfff; 261 if (Imm12 >= 0) 262 Binary |= (1 << 12); 263 Binary |= (Reg << 13); 264 return Binary; 265 } 266 267 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { 268 return 0; 269 } 270 271 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 272 const { return 0;} 273 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 274 const { return 0;} 275 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 276 const { return 0;} 277 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 278 const { return 0;} 279 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 280 const { return 0; } 281 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 282 const { return 0; } 283 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 284 const { return 0; } 285 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 286 const { return 0; } 287 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 288 const { return 0; } 289 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 290 // {17-13} = reg 291 // {12} = (U)nsigned (add == '1', sub == '0') 292 // {11-0} = imm12 293 const MachineOperand &MO = MI.getOperand(Op); 294 const MachineOperand &MO1 = MI.getOperand(Op + 1); 295 if (!MO.isReg()) { 296 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 297 return 0; 298 } 299 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 300 int32_t Imm12 = MO1.getImm(); 301 302 // Special value for #-0 303 if (Imm12 == INT32_MIN) 304 Imm12 = 0; 305 306 // Immediate is always encoded as positive. The 'U' bit controls add vs 307 // sub. 308 bool isAdd = true; 309 if (Imm12 < 0) { 310 Imm12 = -Imm12; 311 isAdd = false; 312 } 313 314 uint32_t Binary = Imm12 & 0xfff; 315 if (isAdd) 316 Binary |= (1 << 12); 317 Binary |= (Reg << 13); 318 return Binary; 319 } 320 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 321 const { return 0; } 322 323 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 324 const { return 0; } 325 326 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 327 const { return 0; } 328 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 329 const { return 0; } 330 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 331 const { return 0; } 332 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 333 const { return 0; } 334 335 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 336 /// machine operand requires relocation, record the relocation and return 337 /// zero. 338 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 339 unsigned Reloc); 340 341 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 342 /// 343 unsigned getShiftOp(unsigned Imm) const ; 344 345 /// Routines that handle operands which add machine relocations which are 346 /// fixed up by the relocation stage. 347 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 348 bool MayNeedFarStub, bool Indirect, 349 intptr_t ACPV = 0) const; 350 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 351 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 352 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 353 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 354 intptr_t JTBase = 0) const; 355 }; 356} 357 358char ARMCodeEmitter::ID = 0; 359 360/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 361/// code to the specified MCE object. 362FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 363 JITCodeEmitter &JCE) { 364 return new ARMCodeEmitter(TM, JCE); 365} 366 367bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 368 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 369 MF.getTarget().getRelocationModel() != Reloc::Static) && 370 "JIT relocation model must be set to static or default!"); 371 JTI = ((ARMBaseTargetMachine &)MF.getTarget()).getJITInfo(); 372 II = (const ARMBaseInstrInfo *)MF.getTarget().getInstrInfo(); 373 TD = MF.getTarget().getTargetData(); 374 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 375 MCPEs = &MF.getConstantPool()->getConstants(); 376 MJTEs = 0; 377 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 378 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 379 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 380 JTI->Initialize(MF, IsPIC); 381 MMI = &getAnalysis<MachineModuleInfo>(); 382 MCE.setModuleInfo(MMI); 383 384 do { 385 DEBUG(errs() << "JITTing function '" 386 << MF.getFunction()->getName() << "'\n"); 387 MCE.startFunction(MF); 388 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 389 MBB != E; ++MBB) { 390 MCE.StartMachineBasicBlock(MBB); 391 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 392 I != E; ++I) 393 emitInstruction(*I); 394 } 395 } while (MCE.finishFunction(MF)); 396 397 return false; 398} 399 400/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 401/// 402unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 403 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 404 default: llvm_unreachable("Unknown shift opc!"); 405 case ARM_AM::asr: return 2; 406 case ARM_AM::lsl: return 0; 407 case ARM_AM::lsr: return 1; 408 case ARM_AM::ror: 409 case ARM_AM::rrx: return 3; 410 } 411} 412 413/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 414/// machine operand requires relocation, record the relocation and return zero. 415unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 416 const MachineOperand &MO, 417 unsigned Reloc) { 418 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 419 && "Relocation to this function should be for movt or movw"); 420 421 if (MO.isImm()) 422 return static_cast<unsigned>(MO.getImm()); 423 else if (MO.isGlobal()) 424 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 425 else if (MO.isSymbol()) 426 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 427 else if (MO.isMBB()) 428 emitMachineBasicBlock(MO.getMBB(), Reloc); 429 else { 430#ifndef NDEBUG 431 errs() << MO; 432#endif 433 llvm_unreachable("Unsupported operand type for movw/movt"); 434 } 435 return 0; 436} 437 438/// getMachineOpValue - Return binary encoding of operand. If the machine 439/// operand requires relocation, record the relocation and return zero. 440unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 441 const MachineOperand &MO) const { 442 if (MO.isReg()) 443 return getARMRegisterNumbering(MO.getReg()); 444 else if (MO.isImm()) 445 return static_cast<unsigned>(MO.getImm()); 446 else if (MO.isGlobal()) 447 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 448 else if (MO.isSymbol()) 449 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 450 else if (MO.isCPI()) { 451 const MCInstrDesc &MCID = MI.getDesc(); 452 // For VFP load, the immediate offset is multiplied by 4. 453 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 454 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 455 emitConstPoolAddress(MO.getIndex(), Reloc); 456 } else if (MO.isJTI()) 457 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 458 else if (MO.isMBB()) 459 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 460 else 461 llvm_unreachable("Unable to encode MachineOperand!"); 462 return 0; 463} 464 465/// emitGlobalAddress - Emit the specified address to the code stream. 466/// 467void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 468 bool MayNeedFarStub, bool Indirect, 469 intptr_t ACPV) const { 470 MachineRelocation MR = Indirect 471 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 472 const_cast<GlobalValue *>(GV), 473 ACPV, MayNeedFarStub) 474 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 475 const_cast<GlobalValue *>(GV), ACPV, 476 MayNeedFarStub); 477 MCE.addRelocation(MR); 478} 479 480/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 481/// be emitted to the current location in the function, and allow it to be PC 482/// relative. 483void ARMCodeEmitter:: 484emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 485 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 486 Reloc, ES)); 487} 488 489/// emitConstPoolAddress - Arrange for the address of an constant pool 490/// to be emitted to the current location in the function, and allow it to be PC 491/// relative. 492void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 493 // Tell JIT emitter we'll resolve the address. 494 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 495 Reloc, CPI, 0, true)); 496} 497 498/// emitJumpTableAddress - Arrange for the address of a jump table to 499/// be emitted to the current location in the function, and allow it to be PC 500/// relative. 501void ARMCodeEmitter:: 502emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 503 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 504 Reloc, JTIndex, 0, true)); 505} 506 507/// emitMachineBasicBlock - Emit the specified address basic block. 508void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 509 unsigned Reloc, 510 intptr_t JTBase) const { 511 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 512 Reloc, BB, JTBase)); 513} 514 515void ARMCodeEmitter::emitWordLE(unsigned Binary) { 516 DEBUG(errs() << " 0x"; 517 errs().write_hex(Binary) << "\n"); 518 MCE.emitWordLE(Binary); 519} 520 521void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 522 DEBUG(errs() << " 0x"; 523 errs().write_hex(Binary) << "\n"); 524 MCE.emitDWordLE(Binary); 525} 526 527void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 528 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 529 530 MCE.processDebugLoc(MI.getDebugLoc(), true); 531 532 ++NumEmitted; // Keep track of the # of mi's emitted 533 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 534 default: { 535 llvm_unreachable("Unhandled instruction encoding format!"); 536 } 537 case ARMII::MiscFrm: 538 if (MI.getOpcode() == ARM::LEApcrelJT) { 539 // Materialize jumptable address. 540 emitLEApcrelJTInstruction(MI); 541 break; 542 } 543 llvm_unreachable("Unhandled instruction encoding!"); 544 case ARMII::Pseudo: 545 emitPseudoInstruction(MI); 546 break; 547 case ARMII::DPFrm: 548 case ARMII::DPSoRegFrm: 549 emitDataProcessingInstruction(MI); 550 break; 551 case ARMII::LdFrm: 552 case ARMII::StFrm: 553 emitLoadStoreInstruction(MI); 554 break; 555 case ARMII::LdMiscFrm: 556 case ARMII::StMiscFrm: 557 emitMiscLoadStoreInstruction(MI); 558 break; 559 case ARMII::LdStMulFrm: 560 emitLoadStoreMultipleInstruction(MI); 561 break; 562 case ARMII::MulFrm: 563 emitMulFrmInstruction(MI); 564 break; 565 case ARMII::ExtFrm: 566 emitExtendInstruction(MI); 567 break; 568 case ARMII::ArithMiscFrm: 569 emitMiscArithInstruction(MI); 570 break; 571 case ARMII::SatFrm: 572 emitSaturateInstruction(MI); 573 break; 574 case ARMII::BrFrm: 575 emitBranchInstruction(MI); 576 break; 577 case ARMII::BrMiscFrm: 578 emitMiscBranchInstruction(MI); 579 break; 580 // VFP instructions. 581 case ARMII::VFPUnaryFrm: 582 case ARMII::VFPBinaryFrm: 583 emitVFPArithInstruction(MI); 584 break; 585 case ARMII::VFPConv1Frm: 586 case ARMII::VFPConv2Frm: 587 case ARMII::VFPConv3Frm: 588 case ARMII::VFPConv4Frm: 589 case ARMII::VFPConv5Frm: 590 emitVFPConversionInstruction(MI); 591 break; 592 case ARMII::VFPLdStFrm: 593 emitVFPLoadStoreInstruction(MI); 594 break; 595 case ARMII::VFPLdStMulFrm: 596 emitVFPLoadStoreMultipleInstruction(MI); 597 break; 598 599 // NEON instructions. 600 case ARMII::NGetLnFrm: 601 case ARMII::NSetLnFrm: 602 emitNEONLaneInstruction(MI); 603 break; 604 case ARMII::NDupFrm: 605 emitNEONDupInstruction(MI); 606 break; 607 case ARMII::N1RegModImmFrm: 608 emitNEON1RegModImmInstruction(MI); 609 break; 610 case ARMII::N2RegFrm: 611 emitNEON2RegInstruction(MI); 612 break; 613 case ARMII::N3RegFrm: 614 emitNEON3RegInstruction(MI); 615 break; 616 } 617 MCE.processDebugLoc(MI.getDebugLoc(), false); 618} 619 620void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 621 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 622 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 623 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 624 625 // Remember the CONSTPOOL_ENTRY address for later relocation. 626 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 627 628 // Emit constpool island entry. In most cases, the actual values will be 629 // resolved and relocated after code emission. 630 if (MCPE.isMachineConstantPoolEntry()) { 631 ARMConstantPoolValue *ACPV = 632 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 633 634 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 635 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 636 637 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 638 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 639 if (GV) { 640 Reloc::Model RelocM = TM.getRelocationModel(); 641 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 642 isa<Function>(GV), 643 Subtarget->GVIsIndirectSymbol(GV, RelocM), 644 (intptr_t)ACPV); 645 } else { 646 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 647 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute); 648 } 649 emitWordLE(0); 650 } else { 651 const Constant *CV = MCPE.Val.ConstVal; 652 653 DEBUG({ 654 errs() << " ** Constant pool #" << CPI << " @ " 655 << (void*)MCE.getCurrentPCValue() << " "; 656 if (const Function *F = dyn_cast<Function>(CV)) 657 errs() << F->getName(); 658 else 659 errs() << *CV; 660 errs() << '\n'; 661 }); 662 663 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 664 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 665 emitWordLE(0); 666 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 667 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 668 emitWordLE(Val); 669 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 670 if (CFP->getType()->isFloatTy()) 671 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 672 else if (CFP->getType()->isDoubleTy()) 673 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 674 else { 675 llvm_unreachable("Unable to handle this constantpool entry!"); 676 } 677 } else { 678 llvm_unreachable("Unable to handle this constantpool entry!"); 679 } 680 } 681} 682 683void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 684 const MachineOperand &MO0 = MI.getOperand(0); 685 const MachineOperand &MO1 = MI.getOperand(1); 686 687 // Emit the 'movw' instruction. 688 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 689 690 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 691 692 // Set the conditional execution predicate. 693 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 694 695 // Encode Rd. 696 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 697 698 // Encode imm16 as imm4:imm12 699 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 700 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 701 emitWordLE(Binary); 702 703 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 704 // Emit the 'movt' instruction. 705 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 706 707 // Set the conditional execution predicate. 708 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 709 710 // Encode Rd. 711 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 712 713 // Encode imm16 as imm4:imm1, same as movw above. 714 Binary |= Hi16 & 0xFFF; 715 Binary |= ((Hi16 >> 12) & 0xF) << 16; 716 emitWordLE(Binary); 717} 718 719void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 720 const MachineOperand &MO0 = MI.getOperand(0); 721 const MachineOperand &MO1 = MI.getOperand(1); 722 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 723 "Not a valid so_imm value!"); 724 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 725 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 726 727 // Emit the 'mov' instruction. 728 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 729 730 // Set the conditional execution predicate. 731 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 732 733 // Encode Rd. 734 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 735 736 // Encode so_imm. 737 // Set bit I(25) to identify this is the immediate form of <shifter_op> 738 Binary |= 1 << ARMII::I_BitShift; 739 Binary |= getMachineSoImmOpValue(V1); 740 emitWordLE(Binary); 741 742 // Now the 'orr' instruction. 743 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 744 745 // Set the conditional execution predicate. 746 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 747 748 // Encode Rd. 749 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 750 751 // Encode Rn. 752 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 753 754 // Encode so_imm. 755 // Set bit I(25) to identify this is the immediate form of <shifter_op> 756 Binary |= 1 << ARMII::I_BitShift; 757 Binary |= getMachineSoImmOpValue(V2); 758 emitWordLE(Binary); 759} 760 761void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 762 // It's basically add r, pc, (LJTI - $+8) 763 764 const MCInstrDesc &MCID = MI.getDesc(); 765 766 // Emit the 'add' instruction. 767 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 768 769 // Set the conditional execution predicate 770 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 771 772 // Encode S bit if MI modifies CPSR. 773 Binary |= getAddrModeSBit(MI, MCID); 774 775 // Encode Rd. 776 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 777 778 // Encode Rn which is PC. 779 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 780 781 // Encode the displacement. 782 Binary |= 1 << ARMII::I_BitShift; 783 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 784 785 emitWordLE(Binary); 786} 787 788void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 789 unsigned Opcode = MI.getDesc().Opcode; 790 791 // Part of binary is determined by TableGn. 792 unsigned Binary = getBinaryCodeForInstr(MI); 793 794 // Set the conditional execution predicate 795 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 796 797 // Encode S bit if MI modifies CPSR. 798 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 799 Binary |= 1 << ARMII::S_BitShift; 800 801 // Encode register def if there is one. 802 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 803 804 // Encode the shift operation. 805 switch (Opcode) { 806 default: break; 807 case ARM::RRX: 808 // rrx 809 Binary |= 0x6 << 4; 810 break; 811 case ARM::MOVsrl_flag: 812 // lsr #1 813 Binary |= (0x2 << 4) | (1 << 7); 814 break; 815 case ARM::MOVsra_flag: 816 // asr #1 817 Binary |= (0x4 << 4) | (1 << 7); 818 break; 819 } 820 821 // Encode register Rm. 822 Binary |= getMachineOpValue(MI, 1); 823 824 emitWordLE(Binary); 825} 826 827void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 828 DEBUG(errs() << " ** LPC" << LabelID << " @ " 829 << (void*)MCE.getCurrentPCValue() << '\n'); 830 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 831} 832 833void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 834 unsigned Opcode = MI.getDesc().Opcode; 835 switch (Opcode) { 836 default: 837 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 838 case ARM::BX_CALL: 839 case ARM::BMOVPCRX_CALL: { 840 // First emit mov lr, pc 841 unsigned Binary = 0x01a0e00f; 842 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 843 emitWordLE(Binary); 844 845 // and then emit the branch. 846 emitMiscBranchInstruction(MI); 847 break; 848 } 849 case TargetOpcode::INLINEASM: { 850 // We allow inline assembler nodes with empty bodies - they can 851 // implicitly define registers, which is ok for JIT. 852 if (MI.getOperand(0).getSymbolName()[0]) { 853 report_fatal_error("JIT does not support inline asm!"); 854 } 855 break; 856 } 857 case TargetOpcode::PROLOG_LABEL: 858 case TargetOpcode::EH_LABEL: 859 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 860 break; 861 case TargetOpcode::IMPLICIT_DEF: 862 case TargetOpcode::KILL: 863 // Do nothing. 864 break; 865 case ARM::CONSTPOOL_ENTRY: 866 emitConstPoolInstruction(MI); 867 break; 868 case ARM::PICADD: { 869 // Remember of the address of the PC label for relocation later. 870 addPCLabel(MI.getOperand(2).getImm()); 871 // PICADD is just an add instruction that implicitly read pc. 872 emitDataProcessingInstruction(MI, 0, ARM::PC); 873 break; 874 } 875 case ARM::PICLDR: 876 case ARM::PICLDRB: 877 case ARM::PICSTR: 878 case ARM::PICSTRB: { 879 // Remember of the address of the PC label for relocation later. 880 addPCLabel(MI.getOperand(2).getImm()); 881 // These are just load / store instructions that implicitly read pc. 882 emitLoadStoreInstruction(MI, 0, ARM::PC); 883 break; 884 } 885 case ARM::PICLDRH: 886 case ARM::PICLDRSH: 887 case ARM::PICLDRSB: 888 case ARM::PICSTRH: { 889 // Remember of the address of the PC label for relocation later. 890 addPCLabel(MI.getOperand(2).getImm()); 891 // These are just load / store instructions that implicitly read pc. 892 emitMiscLoadStoreInstruction(MI, ARM::PC); 893 break; 894 } 895 896 case ARM::MOVi32imm: 897 // Two instructions to materialize a constant. 898 if (Subtarget->hasV6T2Ops()) 899 emitMOVi32immInstruction(MI); 900 else 901 emitMOVi2piecesInstruction(MI); 902 break; 903 904 case ARM::LEApcrelJT: 905 // Materialize jumptable address. 906 emitLEApcrelJTInstruction(MI); 907 break; 908 case ARM::RRX: 909 case ARM::MOVsrl_flag: 910 case ARM::MOVsra_flag: 911 emitPseudoMoveInstruction(MI); 912 break; 913 } 914} 915 916unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 917 const MCInstrDesc &MCID, 918 const MachineOperand &MO, 919 unsigned OpIdx) { 920 unsigned Binary = getMachineOpValue(MI, MO); 921 922 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 923 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 924 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 925 926 // Encode the shift opcode. 927 unsigned SBits = 0; 928 unsigned Rs = MO1.getReg(); 929 if (Rs) { 930 // Set shift operand (bit[7:4]). 931 // LSL - 0001 932 // LSR - 0011 933 // ASR - 0101 934 // ROR - 0111 935 // RRX - 0110 and bit[11:8] clear. 936 switch (SOpc) { 937 default: llvm_unreachable("Unknown shift opc!"); 938 case ARM_AM::lsl: SBits = 0x1; break; 939 case ARM_AM::lsr: SBits = 0x3; break; 940 case ARM_AM::asr: SBits = 0x5; break; 941 case ARM_AM::ror: SBits = 0x7; break; 942 case ARM_AM::rrx: SBits = 0x6; break; 943 } 944 } else { 945 // Set shift operand (bit[6:4]). 946 // LSL - 000 947 // LSR - 010 948 // ASR - 100 949 // ROR - 110 950 switch (SOpc) { 951 default: llvm_unreachable("Unknown shift opc!"); 952 case ARM_AM::lsl: SBits = 0x0; break; 953 case ARM_AM::lsr: SBits = 0x2; break; 954 case ARM_AM::asr: SBits = 0x4; break; 955 case ARM_AM::ror: SBits = 0x6; break; 956 } 957 } 958 Binary |= SBits << 4; 959 if (SOpc == ARM_AM::rrx) 960 return Binary; 961 962 // Encode the shift operation Rs or shift_imm (except rrx). 963 if (Rs) { 964 // Encode Rs bit[11:8]. 965 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 966 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 967 } 968 969 // Encode shift_imm bit[11:7]. 970 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 971} 972 973unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 974 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 975 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 976 977 // Encode rotate_imm. 978 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 979 << ARMII::SoRotImmShift; 980 981 // Encode immed_8. 982 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 983 return Binary; 984} 985 986unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 987 const MCInstrDesc &MCID) const { 988 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ 989 const MachineOperand &MO = MI.getOperand(i-1); 990 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 991 return 1 << ARMII::S_BitShift; 992 } 993 return 0; 994} 995 996void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 997 unsigned ImplicitRd, 998 unsigned ImplicitRn) { 999 const MCInstrDesc &MCID = MI.getDesc(); 1000 1001 // Part of binary is determined by TableGn. 1002 unsigned Binary = getBinaryCodeForInstr(MI); 1003 1004 // Set the conditional execution predicate 1005 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1006 1007 // Encode S bit if MI modifies CPSR. 1008 Binary |= getAddrModeSBit(MI, MCID); 1009 1010 // Encode register def if there is one. 1011 unsigned NumDefs = MCID.getNumDefs(); 1012 unsigned OpIdx = 0; 1013 if (NumDefs) 1014 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1015 else if (ImplicitRd) 1016 // Special handling for implicit use (e.g. PC). 1017 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1018 1019 if (MCID.Opcode == ARM::MOVi16) { 1020 // Get immediate from MI. 1021 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1022 ARM::reloc_arm_movw); 1023 // Encode imm which is the same as in emitMOVi32immInstruction(). 1024 Binary |= Lo16 & 0xFFF; 1025 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1026 emitWordLE(Binary); 1027 return; 1028 } else if(MCID.Opcode == ARM::MOVTi16) { 1029 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1030 ARM::reloc_arm_movt) >> 16); 1031 Binary |= Hi16 & 0xFFF; 1032 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1033 emitWordLE(Binary); 1034 return; 1035 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1036 uint32_t v = ~MI.getOperand(2).getImm(); 1037 int32_t lsb = CountTrailingZeros_32(v); 1038 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1039 // Instr{20-16} = msb, Instr{11-7} = lsb 1040 Binary |= (msb & 0x1F) << 16; 1041 Binary |= (lsb & 0x1F) << 7; 1042 emitWordLE(Binary); 1043 return; 1044 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1045 // Encode Rn in Instr{0-3} 1046 Binary |= getMachineOpValue(MI, OpIdx++); 1047 1048 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1049 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1050 1051 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1052 Binary |= (widthm1 & 0x1F) << 16; 1053 Binary |= (lsb & 0x1F) << 7; 1054 emitWordLE(Binary); 1055 return; 1056 } 1057 1058 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1059 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1060 ++OpIdx; 1061 1062 // Encode first non-shifter register operand if there is one. 1063 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1064 if (!isUnary) { 1065 if (ImplicitRn) 1066 // Special handling for implicit use (e.g. PC). 1067 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1068 else { 1069 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1070 ++OpIdx; 1071 } 1072 } 1073 1074 // Encode shifter operand. 1075 const MachineOperand &MO = MI.getOperand(OpIdx); 1076 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1077 // Encode SoReg. 1078 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1079 return; 1080 } 1081 1082 if (MO.isReg()) { 1083 // Encode register Rm. 1084 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1085 return; 1086 } 1087 1088 // Encode so_imm. 1089 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1090 1091 emitWordLE(Binary); 1092} 1093 1094void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1095 unsigned ImplicitRd, 1096 unsigned ImplicitRn) { 1097 const MCInstrDesc &MCID = MI.getDesc(); 1098 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1099 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1100 1101 // Part of binary is determined by TableGn. 1102 unsigned Binary = getBinaryCodeForInstr(MI); 1103 1104 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1105 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1106 MI.getOpcode() == ARM::STRi12) { 1107 emitWordLE(Binary); 1108 return; 1109 } 1110 1111 // Set the conditional execution predicate 1112 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1113 1114 unsigned OpIdx = 0; 1115 1116 // Operand 0 of a pre- and post-indexed store is the address base 1117 // writeback. Skip it. 1118 bool Skipped = false; 1119 if (IsPrePost && Form == ARMII::StFrm) { 1120 ++OpIdx; 1121 Skipped = true; 1122 } 1123 1124 // Set first operand 1125 if (ImplicitRd) 1126 // Special handling for implicit use (e.g. PC). 1127 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1128 else 1129 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1130 1131 // Set second operand 1132 if (ImplicitRn) 1133 // Special handling for implicit use (e.g. PC). 1134 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1135 else 1136 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1137 1138 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1139 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1140 ++OpIdx; 1141 1142 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1143 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1144 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1145 1146 // Set bit U(23) according to sign of immed value (positive or negative). 1147 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1148 ARMII::U_BitShift); 1149 if (!MO2.getReg()) { // is immediate 1150 if (ARM_AM::getAM2Offset(AM2Opc)) 1151 // Set the value of offset_12 field 1152 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1153 emitWordLE(Binary); 1154 return; 1155 } 1156 1157 // Set bit I(25), because this is not in immediate encoding. 1158 Binary |= 1 << ARMII::I_BitShift; 1159 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1160 // Set bit[3:0] to the corresponding Rm register 1161 Binary |= getARMRegisterNumbering(MO2.getReg()); 1162 1163 // If this instr is in scaled register offset/index instruction, set 1164 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1165 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1166 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1167 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1168 } 1169 1170 emitWordLE(Binary); 1171} 1172 1173void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1174 unsigned ImplicitRn) { 1175 const MCInstrDesc &MCID = MI.getDesc(); 1176 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1177 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1178 1179 // Part of binary is determined by TableGn. 1180 unsigned Binary = getBinaryCodeForInstr(MI); 1181 1182 // Set the conditional execution predicate 1183 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1184 1185 unsigned OpIdx = 0; 1186 1187 // Operand 0 of a pre- and post-indexed store is the address base 1188 // writeback. Skip it. 1189 bool Skipped = false; 1190 if (IsPrePost && Form == ARMII::StMiscFrm) { 1191 ++OpIdx; 1192 Skipped = true; 1193 } 1194 1195 // Set first operand 1196 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1197 1198 // Skip LDRD and STRD's second operand. 1199 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1200 ++OpIdx; 1201 1202 // Set second operand 1203 if (ImplicitRn) 1204 // Special handling for implicit use (e.g. PC). 1205 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1206 else 1207 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1208 1209 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1210 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1211 ++OpIdx; 1212 1213 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1214 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1215 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1216 1217 // Set bit U(23) according to sign of immed value (positive or negative) 1218 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1219 ARMII::U_BitShift); 1220 1221 // If this instr is in register offset/index encoding, set bit[3:0] 1222 // to the corresponding Rm register. 1223 if (MO2.getReg()) { 1224 Binary |= getARMRegisterNumbering(MO2.getReg()); 1225 emitWordLE(Binary); 1226 return; 1227 } 1228 1229 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1230 Binary |= 1 << ARMII::AM3_I_BitShift; 1231 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1232 // Set operands 1233 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1234 Binary |= (ImmOffs & 0xF); // immedL 1235 } 1236 1237 emitWordLE(Binary); 1238} 1239 1240static unsigned getAddrModeUPBits(unsigned Mode) { 1241 unsigned Binary = 0; 1242 1243 // Set addressing mode by modifying bits U(23) and P(24) 1244 // IA - Increment after - bit U = 1 and bit P = 0 1245 // IB - Increment before - bit U = 1 and bit P = 1 1246 // DA - Decrement after - bit U = 0 and bit P = 0 1247 // DB - Decrement before - bit U = 0 and bit P = 1 1248 switch (Mode) { 1249 default: llvm_unreachable("Unknown addressing sub-mode!"); 1250 case ARM_AM::da: break; 1251 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1252 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1253 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1254 } 1255 1256 return Binary; 1257} 1258 1259void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1260 const MCInstrDesc &MCID = MI.getDesc(); 1261 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1262 1263 // Part of binary is determined by TableGn. 1264 unsigned Binary = getBinaryCodeForInstr(MI); 1265 1266 // Set the conditional execution predicate 1267 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1268 1269 // Skip operand 0 of an instruction with base register update. 1270 unsigned OpIdx = 0; 1271 if (IsUpdating) 1272 ++OpIdx; 1273 1274 // Set base address operand 1275 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1276 1277 // Set addressing mode by modifying bits U(23) and P(24) 1278 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1279 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1280 1281 // Set bit W(21) 1282 if (IsUpdating) 1283 Binary |= 0x1 << ARMII::W_BitShift; 1284 1285 // Set registers 1286 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1287 const MachineOperand &MO = MI.getOperand(i); 1288 if (!MO.isReg() || MO.isImplicit()) 1289 break; 1290 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1291 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1292 RegNum < 16); 1293 Binary |= 0x1 << RegNum; 1294 } 1295 1296 emitWordLE(Binary); 1297} 1298 1299void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1300 const MCInstrDesc &MCID = MI.getDesc(); 1301 1302 // Part of binary is determined by TableGn. 1303 unsigned Binary = getBinaryCodeForInstr(MI); 1304 1305 // Set the conditional execution predicate 1306 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1307 1308 // Encode S bit if MI modifies CPSR. 1309 Binary |= getAddrModeSBit(MI, MCID); 1310 1311 // 32x32->64bit operations have two destination registers. The number 1312 // of register definitions will tell us if that's what we're dealing with. 1313 unsigned OpIdx = 0; 1314 if (MCID.getNumDefs() == 2) 1315 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1316 1317 // Encode Rd 1318 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1319 1320 // Encode Rm 1321 Binary |= getMachineOpValue(MI, OpIdx++); 1322 1323 // Encode Rs 1324 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1325 1326 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1327 // it as Rn (for multiply, that's in the same offset as RdLo. 1328 if (MCID.getNumOperands() > OpIdx && 1329 !MCID.OpInfo[OpIdx].isPredicate() && 1330 !MCID.OpInfo[OpIdx].isOptionalDef()) 1331 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1332 1333 emitWordLE(Binary); 1334} 1335 1336void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1337 const MCInstrDesc &MCID = MI.getDesc(); 1338 1339 // Part of binary is determined by TableGn. 1340 unsigned Binary = getBinaryCodeForInstr(MI); 1341 1342 // Set the conditional execution predicate 1343 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1344 1345 unsigned OpIdx = 0; 1346 1347 // Encode Rd 1348 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1349 1350 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1351 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1352 if (MO2.isReg()) { 1353 // Two register operand form. 1354 // Encode Rn. 1355 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1356 1357 // Encode Rm. 1358 Binary |= getMachineOpValue(MI, MO2); 1359 ++OpIdx; 1360 } else { 1361 Binary |= getMachineOpValue(MI, MO1); 1362 } 1363 1364 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1365 if (MI.getOperand(OpIdx).isImm() && 1366 !MCID.OpInfo[OpIdx].isPredicate() && 1367 !MCID.OpInfo[OpIdx].isOptionalDef()) 1368 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1369 1370 emitWordLE(Binary); 1371} 1372 1373void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1374 const MCInstrDesc &MCID = MI.getDesc(); 1375 1376 // Part of binary is determined by TableGn. 1377 unsigned Binary = getBinaryCodeForInstr(MI); 1378 1379 // Set the conditional execution predicate 1380 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1381 1382 // PKH instructions are finished at this point 1383 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1384 emitWordLE(Binary); 1385 return; 1386 } 1387 1388 unsigned OpIdx = 0; 1389 1390 // Encode Rd 1391 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1392 1393 const MachineOperand &MO = MI.getOperand(OpIdx++); 1394 if (OpIdx == MCID.getNumOperands() || 1395 MCID.OpInfo[OpIdx].isPredicate() || 1396 MCID.OpInfo[OpIdx].isOptionalDef()) { 1397 // Encode Rm and it's done. 1398 Binary |= getMachineOpValue(MI, MO); 1399 emitWordLE(Binary); 1400 return; 1401 } 1402 1403 // Encode Rn. 1404 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1405 1406 // Encode Rm. 1407 Binary |= getMachineOpValue(MI, OpIdx++); 1408 1409 // Encode shift_imm. 1410 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1411 if (MCID.Opcode == ARM::PKHTB) { 1412 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1413 if (ShiftAmt == 32) 1414 ShiftAmt = 0; 1415 } 1416 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1417 Binary |= ShiftAmt << ARMII::ShiftShift; 1418 1419 emitWordLE(Binary); 1420} 1421 1422void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1423 const MCInstrDesc &MCID = MI.getDesc(); 1424 1425 // Part of binary is determined by TableGen. 1426 unsigned Binary = getBinaryCodeForInstr(MI); 1427 1428 // Set the conditional execution predicate 1429 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1430 1431 // Encode Rd 1432 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1433 1434 // Encode saturate bit position. 1435 unsigned Pos = MI.getOperand(1).getImm(); 1436 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1437 Pos -= 1; 1438 assert((Pos < 16 || (Pos < 32 && 1439 MCID.Opcode != ARM::SSAT16 && 1440 MCID.Opcode != ARM::USAT16)) && 1441 "saturate bit position out of range"); 1442 Binary |= Pos << 16; 1443 1444 // Encode Rm 1445 Binary |= getMachineOpValue(MI, 2); 1446 1447 // Encode shift_imm. 1448 if (MCID.getNumOperands() == 4) { 1449 unsigned ShiftOp = MI.getOperand(3).getImm(); 1450 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1451 if (Opc == ARM_AM::asr) 1452 Binary |= (1 << 6); 1453 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1454 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1455 ShiftAmt = 0; 1456 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1457 Binary |= ShiftAmt << ARMII::ShiftShift; 1458 } 1459 1460 emitWordLE(Binary); 1461} 1462 1463void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1464 const MCInstrDesc &MCID = MI.getDesc(); 1465 1466 if (MCID.Opcode == ARM::TPsoft) { 1467 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1468 } 1469 1470 // Part of binary is determined by TableGn. 1471 unsigned Binary = getBinaryCodeForInstr(MI); 1472 1473 // Set the conditional execution predicate 1474 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1475 1476 // Set signed_immed_24 field 1477 Binary |= getMachineOpValue(MI, 0); 1478 1479 emitWordLE(Binary); 1480} 1481 1482void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1483 // Remember the base address of the inline jump table. 1484 uintptr_t JTBase = MCE.getCurrentPCValue(); 1485 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1486 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1487 << '\n'); 1488 1489 // Now emit the jump table entries. 1490 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1491 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1492 if (IsPIC) 1493 // DestBB address - JT base. 1494 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1495 else 1496 // Absolute DestBB address. 1497 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1498 emitWordLE(0); 1499 } 1500} 1501 1502void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1503 const MCInstrDesc &MCID = MI.getDesc(); 1504 1505 // Handle jump tables. 1506 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1507 // First emit a ldr pc, [] instruction. 1508 emitDataProcessingInstruction(MI, ARM::PC); 1509 1510 // Then emit the inline jump table. 1511 unsigned JTIndex = 1512 (MCID.Opcode == ARM::BR_JTr) 1513 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1514 emitInlineJumpTable(JTIndex); 1515 return; 1516 } else if (MCID.Opcode == ARM::BR_JTm) { 1517 // First emit a ldr pc, [] instruction. 1518 emitLoadStoreInstruction(MI, ARM::PC); 1519 1520 // Then emit the inline jump table. 1521 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1522 return; 1523 } 1524 1525 // Part of binary is determined by TableGn. 1526 unsigned Binary = getBinaryCodeForInstr(MI); 1527 1528 // Set the conditional execution predicate 1529 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1530 1531 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1532 // The return register is LR. 1533 Binary |= getARMRegisterNumbering(ARM::LR); 1534 else 1535 // otherwise, set the return register 1536 Binary |= getMachineOpValue(MI, 0); 1537 1538 emitWordLE(Binary); 1539} 1540 1541static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1542 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1543 unsigned Binary = 0; 1544 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1545 RegD = getARMRegisterNumbering(RegD); 1546 if (!isSPVFP) 1547 Binary |= RegD << ARMII::RegRdShift; 1548 else { 1549 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1550 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1551 } 1552 return Binary; 1553} 1554 1555static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1556 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1557 unsigned Binary = 0; 1558 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1559 RegN = getARMRegisterNumbering(RegN); 1560 if (!isSPVFP) 1561 Binary |= RegN << ARMII::RegRnShift; 1562 else { 1563 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1564 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1565 } 1566 return Binary; 1567} 1568 1569static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1570 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1571 unsigned Binary = 0; 1572 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1573 RegM = getARMRegisterNumbering(RegM); 1574 if (!isSPVFP) 1575 Binary |= RegM; 1576 else { 1577 Binary |= ((RegM & 0x1E) >> 1); 1578 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1579 } 1580 return Binary; 1581} 1582 1583void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1584 const MCInstrDesc &MCID = MI.getDesc(); 1585 1586 // Part of binary is determined by TableGn. 1587 unsigned Binary = getBinaryCodeForInstr(MI); 1588 1589 // Set the conditional execution predicate 1590 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1591 1592 unsigned OpIdx = 0; 1593 assert((Binary & ARMII::D_BitShift) == 0 && 1594 (Binary & ARMII::N_BitShift) == 0 && 1595 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1596 1597 // Encode Dd / Sd. 1598 Binary |= encodeVFPRd(MI, OpIdx++); 1599 1600 // If this is a two-address operand, skip it, e.g. FMACD. 1601 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1602 ++OpIdx; 1603 1604 // Encode Dn / Sn. 1605 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1606 Binary |= encodeVFPRn(MI, OpIdx++); 1607 1608 if (OpIdx == MCID.getNumOperands() || 1609 MCID.OpInfo[OpIdx].isPredicate() || 1610 MCID.OpInfo[OpIdx].isOptionalDef()) { 1611 // FCMPEZD etc. has only one operand. 1612 emitWordLE(Binary); 1613 return; 1614 } 1615 1616 // Encode Dm / Sm. 1617 Binary |= encodeVFPRm(MI, OpIdx); 1618 1619 emitWordLE(Binary); 1620} 1621 1622void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1623 const MCInstrDesc &MCID = MI.getDesc(); 1624 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1625 1626 // Part of binary is determined by TableGn. 1627 unsigned Binary = getBinaryCodeForInstr(MI); 1628 1629 // Set the conditional execution predicate 1630 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1631 1632 switch (Form) { 1633 default: break; 1634 case ARMII::VFPConv1Frm: 1635 case ARMII::VFPConv2Frm: 1636 case ARMII::VFPConv3Frm: 1637 // Encode Dd / Sd. 1638 Binary |= encodeVFPRd(MI, 0); 1639 break; 1640 case ARMII::VFPConv4Frm: 1641 // Encode Dn / Sn. 1642 Binary |= encodeVFPRn(MI, 0); 1643 break; 1644 case ARMII::VFPConv5Frm: 1645 // Encode Dm / Sm. 1646 Binary |= encodeVFPRm(MI, 0); 1647 break; 1648 } 1649 1650 switch (Form) { 1651 default: break; 1652 case ARMII::VFPConv1Frm: 1653 // Encode Dm / Sm. 1654 Binary |= encodeVFPRm(MI, 1); 1655 break; 1656 case ARMII::VFPConv2Frm: 1657 case ARMII::VFPConv3Frm: 1658 // Encode Dn / Sn. 1659 Binary |= encodeVFPRn(MI, 1); 1660 break; 1661 case ARMII::VFPConv4Frm: 1662 case ARMII::VFPConv5Frm: 1663 // Encode Dd / Sd. 1664 Binary |= encodeVFPRd(MI, 1); 1665 break; 1666 } 1667 1668 if (Form == ARMII::VFPConv5Frm) 1669 // Encode Dn / Sn. 1670 Binary |= encodeVFPRn(MI, 2); 1671 else if (Form == ARMII::VFPConv3Frm) 1672 // Encode Dm / Sm. 1673 Binary |= encodeVFPRm(MI, 2); 1674 1675 emitWordLE(Binary); 1676} 1677 1678void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1679 // Part of binary is determined by TableGn. 1680 unsigned Binary = getBinaryCodeForInstr(MI); 1681 1682 // Set the conditional execution predicate 1683 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1684 1685 unsigned OpIdx = 0; 1686 1687 // Encode Dd / Sd. 1688 Binary |= encodeVFPRd(MI, OpIdx++); 1689 1690 // Encode address base. 1691 const MachineOperand &Base = MI.getOperand(OpIdx++); 1692 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1693 1694 // If there is a non-zero immediate offset, encode it. 1695 if (Base.isReg()) { 1696 const MachineOperand &Offset = MI.getOperand(OpIdx); 1697 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1698 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1699 Binary |= 1 << ARMII::U_BitShift; 1700 Binary |= ImmOffs; 1701 emitWordLE(Binary); 1702 return; 1703 } 1704 } 1705 1706 // If immediate offset is omitted, default to +0. 1707 Binary |= 1 << ARMII::U_BitShift; 1708 1709 emitWordLE(Binary); 1710} 1711 1712void 1713ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1714 const MCInstrDesc &MCID = MI.getDesc(); 1715 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1716 1717 // Part of binary is determined by TableGn. 1718 unsigned Binary = getBinaryCodeForInstr(MI); 1719 1720 // Set the conditional execution predicate 1721 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1722 1723 // Skip operand 0 of an instruction with base register update. 1724 unsigned OpIdx = 0; 1725 if (IsUpdating) 1726 ++OpIdx; 1727 1728 // Set base address operand 1729 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1730 1731 // Set addressing mode by modifying bits U(23) and P(24) 1732 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1733 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1734 1735 // Set bit W(21) 1736 if (IsUpdating) 1737 Binary |= 0x1 << ARMII::W_BitShift; 1738 1739 // First register is encoded in Dd. 1740 Binary |= encodeVFPRd(MI, OpIdx+2); 1741 1742 // Count the number of registers. 1743 unsigned NumRegs = 1; 1744 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1745 const MachineOperand &MO = MI.getOperand(i); 1746 if (!MO.isReg() || MO.isImplicit()) 1747 break; 1748 ++NumRegs; 1749 } 1750 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1751 // Otherwise, it will be 0, in the case of 32-bit registers. 1752 if(Binary & 0x100) 1753 Binary |= NumRegs * 2; 1754 else 1755 Binary |= NumRegs; 1756 1757 emitWordLE(Binary); 1758} 1759 1760static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1761 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1762 unsigned Binary = 0; 1763 RegD = getARMRegisterNumbering(RegD); 1764 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1765 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1766 return Binary; 1767} 1768 1769static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1770 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1771 unsigned Binary = 0; 1772 RegN = getARMRegisterNumbering(RegN); 1773 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1774 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1775 return Binary; 1776} 1777 1778static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1779 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1780 unsigned Binary = 0; 1781 RegM = getARMRegisterNumbering(RegM); 1782 Binary |= (RegM & 0xf); 1783 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1784 return Binary; 1785} 1786 1787/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1788/// data-processing instruction to the corresponding Thumb encoding. 1789static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1790 assert((Binary & 0xfe000000) == 0xf2000000 && 1791 "not an ARM NEON data-processing instruction"); 1792 unsigned UBit = (Binary >> 24) & 1; 1793 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1794} 1795 1796void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1797 unsigned Binary = getBinaryCodeForInstr(MI); 1798 1799 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1800 const MCInstrDesc &MCID = MI.getDesc(); 1801 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1802 RegTOpIdx = 0; 1803 RegNOpIdx = 1; 1804 LnOpIdx = 2; 1805 } else { // ARMII::NSetLnFrm 1806 RegTOpIdx = 2; 1807 RegNOpIdx = 0; 1808 LnOpIdx = 3; 1809 } 1810 1811 // Set the conditional execution predicate 1812 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1813 1814 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1815 RegT = getARMRegisterNumbering(RegT); 1816 Binary |= (RegT << ARMII::RegRdShift); 1817 Binary |= encodeNEONRn(MI, RegNOpIdx); 1818 1819 unsigned LaneShift; 1820 if ((Binary & (1 << 22)) != 0) 1821 LaneShift = 0; // 8-bit elements 1822 else if ((Binary & (1 << 5)) != 0) 1823 LaneShift = 1; // 16-bit elements 1824 else 1825 LaneShift = 2; // 32-bit elements 1826 1827 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1828 unsigned Opc1 = Lane >> 2; 1829 unsigned Opc2 = Lane & 3; 1830 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1831 Binary |= (Opc1 << 21); 1832 Binary |= (Opc2 << 5); 1833 1834 emitWordLE(Binary); 1835} 1836 1837void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1838 unsigned Binary = getBinaryCodeForInstr(MI); 1839 1840 // Set the conditional execution predicate 1841 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1842 1843 unsigned RegT = MI.getOperand(1).getReg(); 1844 RegT = getARMRegisterNumbering(RegT); 1845 Binary |= (RegT << ARMII::RegRdShift); 1846 Binary |= encodeNEONRn(MI, 0); 1847 emitWordLE(Binary); 1848} 1849 1850void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1851 unsigned Binary = getBinaryCodeForInstr(MI); 1852 // Destination register is encoded in Dd. 1853 Binary |= encodeNEONRd(MI, 0); 1854 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1855 unsigned Imm = MI.getOperand(1).getImm(); 1856 unsigned Op = (Imm >> 12) & 1; 1857 unsigned Cmode = (Imm >> 8) & 0xf; 1858 unsigned I = (Imm >> 7) & 1; 1859 unsigned Imm3 = (Imm >> 4) & 0x7; 1860 unsigned Imm4 = Imm & 0xf; 1861 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1862 if (IsThumb) 1863 Binary = convertNEONDataProcToThumb(Binary); 1864 emitWordLE(Binary); 1865} 1866 1867void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1868 const MCInstrDesc &MCID = MI.getDesc(); 1869 unsigned Binary = getBinaryCodeForInstr(MI); 1870 // Destination register is encoded in Dd; source register in Dm. 1871 unsigned OpIdx = 0; 1872 Binary |= encodeNEONRd(MI, OpIdx++); 1873 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1874 ++OpIdx; 1875 Binary |= encodeNEONRm(MI, OpIdx); 1876 if (IsThumb) 1877 Binary = convertNEONDataProcToThumb(Binary); 1878 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1879 emitWordLE(Binary); 1880} 1881 1882void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1883 const MCInstrDesc &MCID = MI.getDesc(); 1884 unsigned Binary = getBinaryCodeForInstr(MI); 1885 // Destination register is encoded in Dd; source registers in Dn and Dm. 1886 unsigned OpIdx = 0; 1887 Binary |= encodeNEONRd(MI, OpIdx++); 1888 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1889 ++OpIdx; 1890 Binary |= encodeNEONRn(MI, OpIdx++); 1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1892 ++OpIdx; 1893 Binary |= encodeNEONRm(MI, OpIdx); 1894 if (IsThumb) 1895 Binary = convertNEONDataProcToThumb(Binary); 1896 // FIXME: This does not handle VMOVDneon or VMOVQ. 1897 emitWordLE(Binary); 1898} 1899 1900#include "ARMGenCodeEmitter.inc" 1901