TargetLowering.cpp revision 234353
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/MathExtras.h" 32#include <cctype> 33using namespace llvm; 34 35/// We are in the process of implementing a new TypeLegalization action 36/// - the promotion of vector elements. This feature is disabled by default 37/// and only enabled using this flag. 38static cl::opt<bool> 39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), 40 cl::desc("Allow promotion of integer vector element types")); 41 42/// InitLibcallNames - Set default libcall names. 43/// 44static void InitLibcallNames(const char **Names) { 45 Names[RTLIB::SHL_I16] = "__ashlhi3"; 46 Names[RTLIB::SHL_I32] = "__ashlsi3"; 47 Names[RTLIB::SHL_I64] = "__ashldi3"; 48 Names[RTLIB::SHL_I128] = "__ashlti3"; 49 Names[RTLIB::SRL_I16] = "__lshrhi3"; 50 Names[RTLIB::SRL_I32] = "__lshrsi3"; 51 Names[RTLIB::SRL_I64] = "__lshrdi3"; 52 Names[RTLIB::SRL_I128] = "__lshrti3"; 53 Names[RTLIB::SRA_I16] = "__ashrhi3"; 54 Names[RTLIB::SRA_I32] = "__ashrsi3"; 55 Names[RTLIB::SRA_I64] = "__ashrdi3"; 56 Names[RTLIB::SRA_I128] = "__ashrti3"; 57 Names[RTLIB::MUL_I8] = "__mulqi3"; 58 Names[RTLIB::MUL_I16] = "__mulhi3"; 59 Names[RTLIB::MUL_I32] = "__mulsi3"; 60 Names[RTLIB::MUL_I64] = "__muldi3"; 61 Names[RTLIB::MUL_I128] = "__multi3"; 62 Names[RTLIB::MULO_I32] = "__mulosi4"; 63 Names[RTLIB::MULO_I64] = "__mulodi4"; 64 Names[RTLIB::MULO_I128] = "__muloti4"; 65 Names[RTLIB::SDIV_I8] = "__divqi3"; 66 Names[RTLIB::SDIV_I16] = "__divhi3"; 67 Names[RTLIB::SDIV_I32] = "__divsi3"; 68 Names[RTLIB::SDIV_I64] = "__divdi3"; 69 Names[RTLIB::SDIV_I128] = "__divti3"; 70 Names[RTLIB::UDIV_I8] = "__udivqi3"; 71 Names[RTLIB::UDIV_I16] = "__udivhi3"; 72 Names[RTLIB::UDIV_I32] = "__udivsi3"; 73 Names[RTLIB::UDIV_I64] = "__udivdi3"; 74 Names[RTLIB::UDIV_I128] = "__udivti3"; 75 Names[RTLIB::SREM_I8] = "__modqi3"; 76 Names[RTLIB::SREM_I16] = "__modhi3"; 77 Names[RTLIB::SREM_I32] = "__modsi3"; 78 Names[RTLIB::SREM_I64] = "__moddi3"; 79 Names[RTLIB::SREM_I128] = "__modti3"; 80 Names[RTLIB::UREM_I8] = "__umodqi3"; 81 Names[RTLIB::UREM_I16] = "__umodhi3"; 82 Names[RTLIB::UREM_I32] = "__umodsi3"; 83 Names[RTLIB::UREM_I64] = "__umoddi3"; 84 Names[RTLIB::UREM_I128] = "__umodti3"; 85 86 // These are generally not available. 87 Names[RTLIB::SDIVREM_I8] = 0; 88 Names[RTLIB::SDIVREM_I16] = 0; 89 Names[RTLIB::SDIVREM_I32] = 0; 90 Names[RTLIB::SDIVREM_I64] = 0; 91 Names[RTLIB::SDIVREM_I128] = 0; 92 Names[RTLIB::UDIVREM_I8] = 0; 93 Names[RTLIB::UDIVREM_I16] = 0; 94 Names[RTLIB::UDIVREM_I32] = 0; 95 Names[RTLIB::UDIVREM_I64] = 0; 96 Names[RTLIB::UDIVREM_I128] = 0; 97 98 Names[RTLIB::NEG_I32] = "__negsi2"; 99 Names[RTLIB::NEG_I64] = "__negdi2"; 100 Names[RTLIB::ADD_F32] = "__addsf3"; 101 Names[RTLIB::ADD_F64] = "__adddf3"; 102 Names[RTLIB::ADD_F80] = "__addxf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 108 Names[RTLIB::MUL_F32] = "__mulsf3"; 109 Names[RTLIB::MUL_F64] = "__muldf3"; 110 Names[RTLIB::MUL_F80] = "__mulxf3"; 111 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 112 Names[RTLIB::DIV_F32] = "__divsf3"; 113 Names[RTLIB::DIV_F64] = "__divdf3"; 114 Names[RTLIB::DIV_F80] = "__divxf3"; 115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 116 Names[RTLIB::REM_F32] = "fmodf"; 117 Names[RTLIB::REM_F64] = "fmod"; 118 Names[RTLIB::REM_F80] = "fmodl"; 119 Names[RTLIB::REM_PPCF128] = "fmodl"; 120 Names[RTLIB::FMA_F32] = "fmaf"; 121 Names[RTLIB::FMA_F64] = "fma"; 122 Names[RTLIB::FMA_F80] = "fmal"; 123 Names[RTLIB::FMA_PPCF128] = "fmal"; 124 Names[RTLIB::POWI_F32] = "__powisf2"; 125 Names[RTLIB::POWI_F64] = "__powidf2"; 126 Names[RTLIB::POWI_F80] = "__powixf2"; 127 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 128 Names[RTLIB::SQRT_F32] = "sqrtf"; 129 Names[RTLIB::SQRT_F64] = "sqrt"; 130 Names[RTLIB::SQRT_F80] = "sqrtl"; 131 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 132 Names[RTLIB::LOG_F32] = "logf"; 133 Names[RTLIB::LOG_F64] = "log"; 134 Names[RTLIB::LOG_F80] = "logl"; 135 Names[RTLIB::LOG_PPCF128] = "logl"; 136 Names[RTLIB::LOG2_F32] = "log2f"; 137 Names[RTLIB::LOG2_F64] = "log2"; 138 Names[RTLIB::LOG2_F80] = "log2l"; 139 Names[RTLIB::LOG2_PPCF128] = "log2l"; 140 Names[RTLIB::LOG10_F32] = "log10f"; 141 Names[RTLIB::LOG10_F64] = "log10"; 142 Names[RTLIB::LOG10_F80] = "log10l"; 143 Names[RTLIB::LOG10_PPCF128] = "log10l"; 144 Names[RTLIB::EXP_F32] = "expf"; 145 Names[RTLIB::EXP_F64] = "exp"; 146 Names[RTLIB::EXP_F80] = "expl"; 147 Names[RTLIB::EXP_PPCF128] = "expl"; 148 Names[RTLIB::EXP2_F32] = "exp2f"; 149 Names[RTLIB::EXP2_F64] = "exp2"; 150 Names[RTLIB::EXP2_F80] = "exp2l"; 151 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 152 Names[RTLIB::SIN_F32] = "sinf"; 153 Names[RTLIB::SIN_F64] = "sin"; 154 Names[RTLIB::SIN_F80] = "sinl"; 155 Names[RTLIB::SIN_PPCF128] = "sinl"; 156 Names[RTLIB::COS_F32] = "cosf"; 157 Names[RTLIB::COS_F64] = "cos"; 158 Names[RTLIB::COS_F80] = "cosl"; 159 Names[RTLIB::COS_PPCF128] = "cosl"; 160 Names[RTLIB::POW_F32] = "powf"; 161 Names[RTLIB::POW_F64] = "pow"; 162 Names[RTLIB::POW_F80] = "powl"; 163 Names[RTLIB::POW_PPCF128] = "powl"; 164 Names[RTLIB::CEIL_F32] = "ceilf"; 165 Names[RTLIB::CEIL_F64] = "ceil"; 166 Names[RTLIB::CEIL_F80] = "ceill"; 167 Names[RTLIB::CEIL_PPCF128] = "ceill"; 168 Names[RTLIB::TRUNC_F32] = "truncf"; 169 Names[RTLIB::TRUNC_F64] = "trunc"; 170 Names[RTLIB::TRUNC_F80] = "truncl"; 171 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 172 Names[RTLIB::RINT_F32] = "rintf"; 173 Names[RTLIB::RINT_F64] = "rint"; 174 Names[RTLIB::RINT_F80] = "rintl"; 175 Names[RTLIB::RINT_PPCF128] = "rintl"; 176 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 177 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 178 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 179 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 180 Names[RTLIB::FLOOR_F32] = "floorf"; 181 Names[RTLIB::FLOOR_F64] = "floor"; 182 Names[RTLIB::FLOOR_F80] = "floorl"; 183 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 184 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 185 Names[RTLIB::COPYSIGN_F64] = "copysign"; 186 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 187 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 188 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 189 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 190 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 191 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 192 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 193 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 194 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 195 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 196 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 197 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 198 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 199 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 200 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 201 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 202 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 203 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 204 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 205 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 206 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 207 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 208 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 209 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 210 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 211 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 212 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 213 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 214 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 215 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 216 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 217 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 218 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 219 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 220 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 221 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 222 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 223 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 224 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 225 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 226 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 227 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 228 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 229 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 230 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 231 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 232 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 233 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 234 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 235 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 236 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 237 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 238 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 239 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 240 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 241 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 242 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 243 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 244 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 245 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 246 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 247 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 248 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 249 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 250 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 251 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 252 Names[RTLIB::OEQ_F32] = "__eqsf2"; 253 Names[RTLIB::OEQ_F64] = "__eqdf2"; 254 Names[RTLIB::UNE_F32] = "__nesf2"; 255 Names[RTLIB::UNE_F64] = "__nedf2"; 256 Names[RTLIB::OGE_F32] = "__gesf2"; 257 Names[RTLIB::OGE_F64] = "__gedf2"; 258 Names[RTLIB::OLT_F32] = "__ltsf2"; 259 Names[RTLIB::OLT_F64] = "__ltdf2"; 260 Names[RTLIB::OLE_F32] = "__lesf2"; 261 Names[RTLIB::OLE_F64] = "__ledf2"; 262 Names[RTLIB::OGT_F32] = "__gtsf2"; 263 Names[RTLIB::OGT_F64] = "__gtdf2"; 264 Names[RTLIB::UO_F32] = "__unordsf2"; 265 Names[RTLIB::UO_F64] = "__unorddf2"; 266 Names[RTLIB::O_F32] = "__unordsf2"; 267 Names[RTLIB::O_F64] = "__unorddf2"; 268 Names[RTLIB::MEMCPY] = "memcpy"; 269 Names[RTLIB::MEMMOVE] = "memmove"; 270 Names[RTLIB::MEMSET] = "memset"; 271 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 272 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 276 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 280 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 281 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 282 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 283 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 284 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 285 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 286 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 287 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 288 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 289 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 290 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 291 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 292 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 293 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 294 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 295 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 296 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 297 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 298 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 299 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 300 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 301 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 302 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 303 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 304} 305 306/// InitLibcallCallingConvs - Set default libcall CallingConvs. 307/// 308static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 309 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 310 CCs[i] = CallingConv::C; 311 } 312} 313 314/// getFPEXT - Return the FPEXT_*_* value for the given types, or 315/// UNKNOWN_LIBCALL if there is none. 316RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 317 if (OpVT == MVT::f32) { 318 if (RetVT == MVT::f64) 319 return FPEXT_F32_F64; 320 } 321 322 return UNKNOWN_LIBCALL; 323} 324 325/// getFPROUND - Return the FPROUND_*_* value for the given types, or 326/// UNKNOWN_LIBCALL if there is none. 327RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 328 if (RetVT == MVT::f32) { 329 if (OpVT == MVT::f64) 330 return FPROUND_F64_F32; 331 if (OpVT == MVT::f80) 332 return FPROUND_F80_F32; 333 if (OpVT == MVT::ppcf128) 334 return FPROUND_PPCF128_F32; 335 } else if (RetVT == MVT::f64) { 336 if (OpVT == MVT::f80) 337 return FPROUND_F80_F64; 338 if (OpVT == MVT::ppcf128) 339 return FPROUND_PPCF128_F64; 340 } 341 342 return UNKNOWN_LIBCALL; 343} 344 345/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 346/// UNKNOWN_LIBCALL if there is none. 347RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 348 if (OpVT == MVT::f32) { 349 if (RetVT == MVT::i8) 350 return FPTOSINT_F32_I8; 351 if (RetVT == MVT::i16) 352 return FPTOSINT_F32_I16; 353 if (RetVT == MVT::i32) 354 return FPTOSINT_F32_I32; 355 if (RetVT == MVT::i64) 356 return FPTOSINT_F32_I64; 357 if (RetVT == MVT::i128) 358 return FPTOSINT_F32_I128; 359 } else if (OpVT == MVT::f64) { 360 if (RetVT == MVT::i8) 361 return FPTOSINT_F64_I8; 362 if (RetVT == MVT::i16) 363 return FPTOSINT_F64_I16; 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F64_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F64_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F64_I128; 370 } else if (OpVT == MVT::f80) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_F80_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_F80_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_F80_I128; 377 } else if (OpVT == MVT::ppcf128) { 378 if (RetVT == MVT::i32) 379 return FPTOSINT_PPCF128_I32; 380 if (RetVT == MVT::i64) 381 return FPTOSINT_PPCF128_I64; 382 if (RetVT == MVT::i128) 383 return FPTOSINT_PPCF128_I128; 384 } 385 return UNKNOWN_LIBCALL; 386} 387 388/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 389/// UNKNOWN_LIBCALL if there is none. 390RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 391 if (OpVT == MVT::f32) { 392 if (RetVT == MVT::i8) 393 return FPTOUINT_F32_I8; 394 if (RetVT == MVT::i16) 395 return FPTOUINT_F32_I16; 396 if (RetVT == MVT::i32) 397 return FPTOUINT_F32_I32; 398 if (RetVT == MVT::i64) 399 return FPTOUINT_F32_I64; 400 if (RetVT == MVT::i128) 401 return FPTOUINT_F32_I128; 402 } else if (OpVT == MVT::f64) { 403 if (RetVT == MVT::i8) 404 return FPTOUINT_F64_I8; 405 if (RetVT == MVT::i16) 406 return FPTOUINT_F64_I16; 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F64_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F64_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F64_I128; 413 } else if (OpVT == MVT::f80) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_F80_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_F80_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_F80_I128; 420 } else if (OpVT == MVT::ppcf128) { 421 if (RetVT == MVT::i32) 422 return FPTOUINT_PPCF128_I32; 423 if (RetVT == MVT::i64) 424 return FPTOUINT_PPCF128_I64; 425 if (RetVT == MVT::i128) 426 return FPTOUINT_PPCF128_I128; 427 } 428 return UNKNOWN_LIBCALL; 429} 430 431/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 432/// UNKNOWN_LIBCALL if there is none. 433RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 434 if (OpVT == MVT::i32) { 435 if (RetVT == MVT::f32) 436 return SINTTOFP_I32_F32; 437 else if (RetVT == MVT::f64) 438 return SINTTOFP_I32_F64; 439 else if (RetVT == MVT::f80) 440 return SINTTOFP_I32_F80; 441 else if (RetVT == MVT::ppcf128) 442 return SINTTOFP_I32_PPCF128; 443 } else if (OpVT == MVT::i64) { 444 if (RetVT == MVT::f32) 445 return SINTTOFP_I64_F32; 446 else if (RetVT == MVT::f64) 447 return SINTTOFP_I64_F64; 448 else if (RetVT == MVT::f80) 449 return SINTTOFP_I64_F80; 450 else if (RetVT == MVT::ppcf128) 451 return SINTTOFP_I64_PPCF128; 452 } else if (OpVT == MVT::i128) { 453 if (RetVT == MVT::f32) 454 return SINTTOFP_I128_F32; 455 else if (RetVT == MVT::f64) 456 return SINTTOFP_I128_F64; 457 else if (RetVT == MVT::f80) 458 return SINTTOFP_I128_F80; 459 else if (RetVT == MVT::ppcf128) 460 return SINTTOFP_I128_PPCF128; 461 } 462 return UNKNOWN_LIBCALL; 463} 464 465/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 466/// UNKNOWN_LIBCALL if there is none. 467RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 468 if (OpVT == MVT::i32) { 469 if (RetVT == MVT::f32) 470 return UINTTOFP_I32_F32; 471 else if (RetVT == MVT::f64) 472 return UINTTOFP_I32_F64; 473 else if (RetVT == MVT::f80) 474 return UINTTOFP_I32_F80; 475 else if (RetVT == MVT::ppcf128) 476 return UINTTOFP_I32_PPCF128; 477 } else if (OpVT == MVT::i64) { 478 if (RetVT == MVT::f32) 479 return UINTTOFP_I64_F32; 480 else if (RetVT == MVT::f64) 481 return UINTTOFP_I64_F64; 482 else if (RetVT == MVT::f80) 483 return UINTTOFP_I64_F80; 484 else if (RetVT == MVT::ppcf128) 485 return UINTTOFP_I64_PPCF128; 486 } else if (OpVT == MVT::i128) { 487 if (RetVT == MVT::f32) 488 return UINTTOFP_I128_F32; 489 else if (RetVT == MVT::f64) 490 return UINTTOFP_I128_F64; 491 else if (RetVT == MVT::f80) 492 return UINTTOFP_I128_F80; 493 else if (RetVT == MVT::ppcf128) 494 return UINTTOFP_I128_PPCF128; 495 } 496 return UNKNOWN_LIBCALL; 497} 498 499/// InitCmpLibcallCCs - Set default comparison libcall CC. 500/// 501static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 502 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 503 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 504 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 505 CCs[RTLIB::UNE_F32] = ISD::SETNE; 506 CCs[RTLIB::UNE_F64] = ISD::SETNE; 507 CCs[RTLIB::OGE_F32] = ISD::SETGE; 508 CCs[RTLIB::OGE_F64] = ISD::SETGE; 509 CCs[RTLIB::OLT_F32] = ISD::SETLT; 510 CCs[RTLIB::OLT_F64] = ISD::SETLT; 511 CCs[RTLIB::OLE_F32] = ISD::SETLE; 512 CCs[RTLIB::OLE_F64] = ISD::SETLE; 513 CCs[RTLIB::OGT_F32] = ISD::SETGT; 514 CCs[RTLIB::OGT_F64] = ISD::SETGT; 515 CCs[RTLIB::UO_F32] = ISD::SETNE; 516 CCs[RTLIB::UO_F64] = ISD::SETNE; 517 CCs[RTLIB::O_F32] = ISD::SETEQ; 518 CCs[RTLIB::O_F64] = ISD::SETEQ; 519} 520 521/// NOTE: The constructor takes ownership of TLOF. 522TargetLowering::TargetLowering(const TargetMachine &tm, 523 const TargetLoweringObjectFile *tlof) 524 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 525 mayPromoteElements(AllowPromoteIntElem) { 526 // All operations default to being supported. 527 memset(OpActions, 0, sizeof(OpActions)); 528 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 529 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 530 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 531 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 532 533 // Set default actions for various operations. 534 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 535 // Default all indexed load / store to expand. 536 for (unsigned IM = (unsigned)ISD::PRE_INC; 537 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 538 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 539 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 540 } 541 542 // These operations default to expand. 543 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 545 } 546 547 // Most targets ignore the @llvm.prefetch intrinsic. 548 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 549 550 // ConstantFP nodes default to expand. Targets can either change this to 551 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 552 // to optimize expansions for certain constants. 553 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 554 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 555 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 556 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 557 558 // These library functions default to expand. 559 setOperationAction(ISD::FLOG , MVT::f16, Expand); 560 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 561 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 562 setOperationAction(ISD::FEXP , MVT::f16, Expand); 563 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 564 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 565 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 566 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 567 setOperationAction(ISD::FRINT, MVT::f16, Expand); 568 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 569 setOperationAction(ISD::FLOG , MVT::f32, Expand); 570 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 571 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 572 setOperationAction(ISD::FEXP , MVT::f32, Expand); 573 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 574 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 575 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 576 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 577 setOperationAction(ISD::FRINT, MVT::f32, Expand); 578 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 579 setOperationAction(ISD::FLOG , MVT::f64, Expand); 580 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 581 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 582 setOperationAction(ISD::FEXP , MVT::f64, Expand); 583 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 584 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 585 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 586 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 587 setOperationAction(ISD::FRINT, MVT::f64, Expand); 588 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 589 590 // Default ISD::TRAP to expand (which turns it into abort). 591 setOperationAction(ISD::TRAP, MVT::Other, Expand); 592 593 IsLittleEndian = TD->isLittleEndian(); 594 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 595 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 596 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 597 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 598 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 599 = maxStoresPerMemmoveOptSize = 4; 600 benefitFromCodePlacementOpt = false; 601 UseUnderscoreSetJmp = false; 602 UseUnderscoreLongJmp = false; 603 SelectIsExpensive = false; 604 IntDivIsCheap = false; 605 Pow2DivIsCheap = false; 606 JumpIsExpensive = false; 607 StackPointerRegisterToSaveRestore = 0; 608 ExceptionPointerRegister = 0; 609 ExceptionSelectorRegister = 0; 610 BooleanContents = UndefinedBooleanContent; 611 BooleanVectorContents = UndefinedBooleanContent; 612 SchedPreferenceInfo = Sched::ILP; 613 JumpBufSize = 0; 614 JumpBufAlignment = 0; 615 MinFunctionAlignment = 0; 616 PrefFunctionAlignment = 0; 617 PrefLoopAlignment = 0; 618 MinStackArgumentAlignment = 1; 619 ShouldFoldAtomicFences = false; 620 InsertFencesForAtomic = false; 621 622 InitLibcallNames(LibcallRoutineNames); 623 InitCmpLibcallCCs(CmpLibcallCCs); 624 InitLibcallCallingConvs(LibcallCallingConvs); 625} 626 627TargetLowering::~TargetLowering() { 628 delete &TLOF; 629} 630 631MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 632 return MVT::getIntegerVT(8*TD->getPointerSize()); 633} 634 635/// canOpTrap - Returns true if the operation can trap for the value type. 636/// VT must be a legal type. 637bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 638 assert(isTypeLegal(VT)); 639 switch (Op) { 640 default: 641 return false; 642 case ISD::FDIV: 643 case ISD::FREM: 644 case ISD::SDIV: 645 case ISD::UDIV: 646 case ISD::SREM: 647 case ISD::UREM: 648 return true; 649 } 650} 651 652 653static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 654 unsigned &NumIntermediates, 655 EVT &RegisterVT, 656 TargetLowering *TLI) { 657 // Figure out the right, legal destination reg to copy into. 658 unsigned NumElts = VT.getVectorNumElements(); 659 MVT EltTy = VT.getVectorElementType(); 660 661 unsigned NumVectorRegs = 1; 662 663 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 664 // could break down into LHS/RHS like LegalizeDAG does. 665 if (!isPowerOf2_32(NumElts)) { 666 NumVectorRegs = NumElts; 667 NumElts = 1; 668 } 669 670 // Divide the input until we get to a supported size. This will always 671 // end with a scalar if the target doesn't support vectors. 672 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 673 NumElts >>= 1; 674 NumVectorRegs <<= 1; 675 } 676 677 NumIntermediates = NumVectorRegs; 678 679 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 680 if (!TLI->isTypeLegal(NewVT)) 681 NewVT = EltTy; 682 IntermediateVT = NewVT; 683 684 unsigned NewVTSize = NewVT.getSizeInBits(); 685 686 // Convert sizes such as i33 to i64. 687 if (!isPowerOf2_32(NewVTSize)) 688 NewVTSize = NextPowerOf2(NewVTSize); 689 690 EVT DestVT = TLI->getRegisterType(NewVT); 691 RegisterVT = DestVT; 692 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 693 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 694 695 // Otherwise, promotion or legal types use the same number of registers as 696 // the vector decimated to the appropriate level. 697 return NumVectorRegs; 698} 699 700/// isLegalRC - Return true if the value types that can be represented by the 701/// specified register class are all legal. 702bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 703 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 704 I != E; ++I) { 705 if (isTypeLegal(*I)) 706 return true; 707 } 708 return false; 709} 710 711/// hasLegalSuperRegRegClasses - Return true if the specified register class 712/// has one or more super-reg register classes that are legal. 713bool 714TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 715 if (*RC->superregclasses_begin() == 0) 716 return false; 717 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 718 E = RC->superregclasses_end(); I != E; ++I) { 719 const TargetRegisterClass *RRC = *I; 720 if (isLegalRC(RRC)) 721 return true; 722 } 723 return false; 724} 725 726/// findRepresentativeClass - Return the largest legal super-reg register class 727/// of the register class for the specified type and its associated "cost". 728std::pair<const TargetRegisterClass*, uint8_t> 729TargetLowering::findRepresentativeClass(EVT VT) const { 730 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 731 if (!RC) 732 return std::make_pair(RC, 0); 733 const TargetRegisterClass *BestRC = RC; 734 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 735 E = RC->superregclasses_end(); I != E; ++I) { 736 const TargetRegisterClass *RRC = *I; 737 if (RRC->isASubClass() || !isLegalRC(RRC)) 738 continue; 739 if (!hasLegalSuperRegRegClasses(RRC)) 740 return std::make_pair(RRC, 1); 741 BestRC = RRC; 742 } 743 return std::make_pair(BestRC, 1); 744} 745 746 747/// computeRegisterProperties - Once all of the register classes are added, 748/// this allows us to compute derived properties we expose. 749void TargetLowering::computeRegisterProperties() { 750 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 751 "Too many value types for ValueTypeActions to hold!"); 752 753 // Everything defaults to needing one register. 754 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 755 NumRegistersForVT[i] = 1; 756 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 757 } 758 // ...except isVoid, which doesn't need any registers. 759 NumRegistersForVT[MVT::isVoid] = 0; 760 761 // Find the largest integer register class. 762 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 763 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 764 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 765 766 // Every integer value type larger than this largest register takes twice as 767 // many registers to represent as the previous ValueType. 768 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 769 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 770 if (!ExpandedVT.isInteger()) 771 break; 772 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 773 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 774 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 775 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 776 } 777 778 // Inspect all of the ValueType's smaller than the largest integer 779 // register to see which ones need promotion. 780 unsigned LegalIntReg = LargestIntReg; 781 for (unsigned IntReg = LargestIntReg - 1; 782 IntReg >= (unsigned)MVT::i1; --IntReg) { 783 EVT IVT = (MVT::SimpleValueType)IntReg; 784 if (isTypeLegal(IVT)) { 785 LegalIntReg = IntReg; 786 } else { 787 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 788 (MVT::SimpleValueType)LegalIntReg; 789 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 790 } 791 } 792 793 // ppcf128 type is really two f64's. 794 if (!isTypeLegal(MVT::ppcf128)) { 795 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 796 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 797 TransformToType[MVT::ppcf128] = MVT::f64; 798 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 799 } 800 801 // Decide how to handle f64. If the target does not have native f64 support, 802 // expand it to i64 and we will be generating soft float library calls. 803 if (!isTypeLegal(MVT::f64)) { 804 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 805 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 806 TransformToType[MVT::f64] = MVT::i64; 807 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 808 } 809 810 // Decide how to handle f32. If the target does not have native support for 811 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 812 if (!isTypeLegal(MVT::f32)) { 813 if (isTypeLegal(MVT::f64)) { 814 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 815 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 816 TransformToType[MVT::f32] = MVT::f64; 817 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 818 } else { 819 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 820 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 821 TransformToType[MVT::f32] = MVT::i32; 822 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 823 } 824 } 825 826 // Loop over all of the vector value types to see which need transformations. 827 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 828 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 829 MVT VT = (MVT::SimpleValueType)i; 830 if (isTypeLegal(VT)) continue; 831 832 // Determine if there is a legal wider type. If so, we should promote to 833 // that wider vector type. 834 EVT EltVT = VT.getVectorElementType(); 835 unsigned NElts = VT.getVectorNumElements(); 836 if (NElts != 1) { 837 bool IsLegalWiderType = false; 838 // If we allow the promotion of vector elements using a flag, 839 // then return TypePromoteInteger on vector elements. 840 // First try to promote the elements of integer vectors. If no legal 841 // promotion was found, fallback to the widen-vector method. 842 if (mayPromoteElements) 843 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 844 EVT SVT = (MVT::SimpleValueType)nVT; 845 // Promote vectors of integers to vectors with the same number 846 // of elements, with a wider element type. 847 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 848 && SVT.getVectorNumElements() == NElts && 849 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 850 TransformToType[i] = SVT; 851 RegisterTypeForVT[i] = SVT; 852 NumRegistersForVT[i] = 1; 853 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 854 IsLegalWiderType = true; 855 break; 856 } 857 } 858 859 if (IsLegalWiderType) continue; 860 861 // Try to widen the vector. 862 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 863 EVT SVT = (MVT::SimpleValueType)nVT; 864 if (SVT.getVectorElementType() == EltVT && 865 SVT.getVectorNumElements() > NElts && 866 isTypeLegal(SVT)) { 867 TransformToType[i] = SVT; 868 RegisterTypeForVT[i] = SVT; 869 NumRegistersForVT[i] = 1; 870 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 871 IsLegalWiderType = true; 872 break; 873 } 874 } 875 if (IsLegalWiderType) continue; 876 } 877 878 MVT IntermediateVT; 879 EVT RegisterVT; 880 unsigned NumIntermediates; 881 NumRegistersForVT[i] = 882 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 883 RegisterVT, this); 884 RegisterTypeForVT[i] = RegisterVT; 885 886 EVT NVT = VT.getPow2VectorType(); 887 if (NVT == VT) { 888 // Type is already a power of 2. The default action is to split. 889 TransformToType[i] = MVT::Other; 890 unsigned NumElts = VT.getVectorNumElements(); 891 ValueTypeActions.setTypeAction(VT, 892 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 893 } else { 894 TransformToType[i] = NVT; 895 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 896 } 897 } 898 899 // Determine the 'representative' register class for each value type. 900 // An representative register class is the largest (meaning one which is 901 // not a sub-register class / subreg register class) legal register class for 902 // a group of value types. For example, on i386, i8, i16, and i32 903 // representative would be GR32; while on x86_64 it's GR64. 904 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 905 const TargetRegisterClass* RRC; 906 uint8_t Cost; 907 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 908 RepRegClassForVT[i] = RRC; 909 RepRegClassCostForVT[i] = Cost; 910 } 911} 912 913const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 914 return NULL; 915} 916 917 918EVT TargetLowering::getSetCCResultType(EVT VT) const { 919 assert(!VT.isVector() && "No default SetCC type for vectors!"); 920 return PointerTy.SimpleTy; 921} 922 923MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 924 return MVT::i32; // return the default value 925} 926 927/// getVectorTypeBreakdown - Vector types are broken down into some number of 928/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 929/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 930/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 931/// 932/// This method returns the number of registers needed, and the VT for each 933/// register. It also returns the VT and quantity of the intermediate values 934/// before they are promoted/expanded. 935/// 936unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 937 EVT &IntermediateVT, 938 unsigned &NumIntermediates, 939 EVT &RegisterVT) const { 940 unsigned NumElts = VT.getVectorNumElements(); 941 942 // If there is a wider vector type with the same element type as this one, 943 // we should widen to that legal vector type. This handles things like 944 // <2 x float> -> <4 x float>. 945 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 946 RegisterVT = getTypeToTransformTo(Context, VT); 947 if (isTypeLegal(RegisterVT)) { 948 IntermediateVT = RegisterVT; 949 NumIntermediates = 1; 950 return 1; 951 } 952 } 953 954 // Figure out the right, legal destination reg to copy into. 955 EVT EltTy = VT.getVectorElementType(); 956 957 unsigned NumVectorRegs = 1; 958 959 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 960 // could break down into LHS/RHS like LegalizeDAG does. 961 if (!isPowerOf2_32(NumElts)) { 962 NumVectorRegs = NumElts; 963 NumElts = 1; 964 } 965 966 // Divide the input until we get to a supported size. This will always 967 // end with a scalar if the target doesn't support vectors. 968 while (NumElts > 1 && !isTypeLegal( 969 EVT::getVectorVT(Context, EltTy, NumElts))) { 970 NumElts >>= 1; 971 NumVectorRegs <<= 1; 972 } 973 974 NumIntermediates = NumVectorRegs; 975 976 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 977 if (!isTypeLegal(NewVT)) 978 NewVT = EltTy; 979 IntermediateVT = NewVT; 980 981 EVT DestVT = getRegisterType(Context, NewVT); 982 RegisterVT = DestVT; 983 unsigned NewVTSize = NewVT.getSizeInBits(); 984 985 // Convert sizes such as i33 to i64. 986 if (!isPowerOf2_32(NewVTSize)) 987 NewVTSize = NextPowerOf2(NewVTSize); 988 989 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 990 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 991 992 // Otherwise, promotion or legal types use the same number of registers as 993 // the vector decimated to the appropriate level. 994 return NumVectorRegs; 995} 996 997/// Get the EVTs and ArgFlags collections that represent the legalized return 998/// type of the given function. This does not require a DAG or a return value, 999/// and is suitable for use before any DAGs for the function are constructed. 1000/// TODO: Move this out of TargetLowering.cpp. 1001void llvm::GetReturnInfo(Type* ReturnType, Attributes attr, 1002 SmallVectorImpl<ISD::OutputArg> &Outs, 1003 const TargetLowering &TLI, 1004 SmallVectorImpl<uint64_t> *Offsets) { 1005 SmallVector<EVT, 4> ValueVTs; 1006 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1007 unsigned NumValues = ValueVTs.size(); 1008 if (NumValues == 0) return; 1009 unsigned Offset = 0; 1010 1011 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1012 EVT VT = ValueVTs[j]; 1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1014 1015 if (attr & Attribute::SExt) 1016 ExtendKind = ISD::SIGN_EXTEND; 1017 else if (attr & Attribute::ZExt) 1018 ExtendKind = ISD::ZERO_EXTEND; 1019 1020 // FIXME: C calling convention requires the return type to be promoted to 1021 // at least 32-bit. But this is not necessary for non-C calling 1022 // conventions. The frontend should mark functions whose return values 1023 // require promoting with signext or zeroext attributes. 1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1025 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1026 if (VT.bitsLT(MinVT)) 1027 VT = MinVT; 1028 } 1029 1030 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1031 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1032 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 1033 PartVT.getTypeForEVT(ReturnType->getContext())); 1034 1035 // 'inreg' on function refers to return value 1036 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1037 if (attr & Attribute::InReg) 1038 Flags.setInReg(); 1039 1040 // Propagate extension type if any 1041 if (attr & Attribute::SExt) 1042 Flags.setSExt(); 1043 else if (attr & Attribute::ZExt) 1044 Flags.setZExt(); 1045 1046 for (unsigned i = 0; i < NumParts; ++i) { 1047 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1048 if (Offsets) { 1049 Offsets->push_back(Offset); 1050 Offset += PartSize; 1051 } 1052 } 1053 } 1054} 1055 1056/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1057/// function arguments in the caller parameter area. This is the actual 1058/// alignment, not its logarithm. 1059unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1060 return TD->getCallFrameTypeAlignment(Ty); 1061} 1062 1063/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1064/// current function. The returned value is a member of the 1065/// MachineJumpTableInfo::JTEntryKind enum. 1066unsigned TargetLowering::getJumpTableEncoding() const { 1067 // In non-pic modes, just use the address of a block. 1068 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1069 return MachineJumpTableInfo::EK_BlockAddress; 1070 1071 // In PIC mode, if the target supports a GPRel32 directive, use it. 1072 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1073 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1074 1075 // Otherwise, use a label difference. 1076 return MachineJumpTableInfo::EK_LabelDifference32; 1077} 1078 1079SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1080 SelectionDAG &DAG) const { 1081 // If our PIC model is GP relative, use the global offset table as the base. 1082 unsigned JTEncoding = getJumpTableEncoding(); 1083 1084 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 1085 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 1086 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1087 1088 return Table; 1089} 1090 1091/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1092/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1093/// MCExpr. 1094const MCExpr * 1095TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1096 unsigned JTI,MCContext &Ctx) const{ 1097 // The normal PIC reloc base is the label at the start of the jump table. 1098 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1099} 1100 1101bool 1102TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1103 // Assume that everything is safe in static mode. 1104 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1105 return true; 1106 1107 // In dynamic-no-pic mode, assume that known defined values are safe. 1108 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1109 GA && 1110 !GA->getGlobal()->isDeclaration() && 1111 !GA->getGlobal()->isWeakForLinker()) 1112 return true; 1113 1114 // Otherwise assume nothing is safe. 1115 return false; 1116} 1117 1118//===----------------------------------------------------------------------===// 1119// Optimization Methods 1120//===----------------------------------------------------------------------===// 1121 1122/// ShrinkDemandedConstant - Check to see if the specified operand of the 1123/// specified instruction is a constant integer. If so, check to see if there 1124/// are any bits set in the constant that are not demanded. If so, shrink the 1125/// constant and return true. 1126bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1127 const APInt &Demanded) { 1128 DebugLoc dl = Op.getDebugLoc(); 1129 1130 // FIXME: ISD::SELECT, ISD::SELECT_CC 1131 switch (Op.getOpcode()) { 1132 default: break; 1133 case ISD::XOR: 1134 case ISD::AND: 1135 case ISD::OR: { 1136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1137 if (!C) return false; 1138 1139 if (Op.getOpcode() == ISD::XOR && 1140 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1141 return false; 1142 1143 // if we can expand it to have all bits set, do it 1144 if (C->getAPIntValue().intersects(~Demanded)) { 1145 EVT VT = Op.getValueType(); 1146 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1147 DAG.getConstant(Demanded & 1148 C->getAPIntValue(), 1149 VT)); 1150 return CombineTo(Op, New); 1151 } 1152 1153 break; 1154 } 1155 } 1156 1157 return false; 1158} 1159 1160/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1161/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1162/// cast, but it could be generalized for targets with other types of 1163/// implicit widening casts. 1164bool 1165TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1166 unsigned BitWidth, 1167 const APInt &Demanded, 1168 DebugLoc dl) { 1169 assert(Op.getNumOperands() == 2 && 1170 "ShrinkDemandedOp only supports binary operators!"); 1171 assert(Op.getNode()->getNumValues() == 1 && 1172 "ShrinkDemandedOp only supports nodes with one result!"); 1173 1174 // Don't do this if the node has another user, which may require the 1175 // full value. 1176 if (!Op.getNode()->hasOneUse()) 1177 return false; 1178 1179 // Search for the smallest integer type with free casts to and from 1180 // Op's type. For expedience, just check power-of-2 integer types. 1181 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1182 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1183 if (!isPowerOf2_32(SmallVTBits)) 1184 SmallVTBits = NextPowerOf2(SmallVTBits); 1185 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1186 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1187 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1188 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1189 // We found a type with free casts. 1190 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1191 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1192 Op.getNode()->getOperand(0)), 1193 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1194 Op.getNode()->getOperand(1))); 1195 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1196 return CombineTo(Op, Z); 1197 } 1198 } 1199 return false; 1200} 1201 1202/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1203/// DemandedMask bits of the result of Op are ever used downstream. If we can 1204/// use this information to simplify Op, create a new simplified DAG node and 1205/// return true, returning the original and new nodes in Old and New. Otherwise, 1206/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1207/// the expression (used to simplify the caller). The KnownZero/One bits may 1208/// only be accurate for those bits in the DemandedMask. 1209bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1210 const APInt &DemandedMask, 1211 APInt &KnownZero, 1212 APInt &KnownOne, 1213 TargetLoweringOpt &TLO, 1214 unsigned Depth) const { 1215 unsigned BitWidth = DemandedMask.getBitWidth(); 1216 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1217 "Mask size mismatches value type size!"); 1218 APInt NewMask = DemandedMask; 1219 DebugLoc dl = Op.getDebugLoc(); 1220 1221 // Don't know anything. 1222 KnownZero = KnownOne = APInt(BitWidth, 0); 1223 1224 // Other users may use these bits. 1225 if (!Op.getNode()->hasOneUse()) { 1226 if (Depth != 0) { 1227 // If not at the root, Just compute the KnownZero/KnownOne bits to 1228 // simplify things downstream. 1229 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1230 return false; 1231 } 1232 // If this is the root being simplified, allow it to have multiple uses, 1233 // just set the NewMask to all bits. 1234 NewMask = APInt::getAllOnesValue(BitWidth); 1235 } else if (DemandedMask == 0) { 1236 // Not demanding any bits from Op. 1237 if (Op.getOpcode() != ISD::UNDEF) 1238 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1239 return false; 1240 } else if (Depth == 6) { // Limit search depth. 1241 return false; 1242 } 1243 1244 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1245 switch (Op.getOpcode()) { 1246 case ISD::Constant: 1247 // We know all of the bits for a constant! 1248 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 1249 KnownZero = ~KnownOne; 1250 return false; // Don't fall through, will infinitely loop. 1251 case ISD::AND: 1252 // If the RHS is a constant, check to see if the LHS would be zero without 1253 // using the bits from the RHS. Below, we use knowledge about the RHS to 1254 // simplify the LHS, here we're using information from the LHS to simplify 1255 // the RHS. 1256 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1257 APInt LHSZero, LHSOne; 1258 // Do not increment Depth here; that can cause an infinite loop. 1259 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 1260 // If the LHS already has zeros where RHSC does, this and is dead. 1261 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1262 return TLO.CombineTo(Op, Op.getOperand(0)); 1263 // If any of the set bits in the RHS are known zero on the LHS, shrink 1264 // the constant. 1265 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1266 return true; 1267 } 1268 1269 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1270 KnownOne, TLO, Depth+1)) 1271 return true; 1272 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1273 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1274 KnownZero2, KnownOne2, TLO, Depth+1)) 1275 return true; 1276 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1277 1278 // If all of the demanded bits are known one on one side, return the other. 1279 // These bits cannot contribute to the result of the 'and'. 1280 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1281 return TLO.CombineTo(Op, Op.getOperand(0)); 1282 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1283 return TLO.CombineTo(Op, Op.getOperand(1)); 1284 // If all of the demanded bits in the inputs are known zeros, return zero. 1285 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1286 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1287 // If the RHS is a constant, see if we can simplify it. 1288 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1289 return true; 1290 // If the operation can be done in a smaller type, do so. 1291 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1292 return true; 1293 1294 // Output known-1 bits are only known if set in both the LHS & RHS. 1295 KnownOne &= KnownOne2; 1296 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1297 KnownZero |= KnownZero2; 1298 break; 1299 case ISD::OR: 1300 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1301 KnownOne, TLO, Depth+1)) 1302 return true; 1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1304 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1305 KnownZero2, KnownOne2, TLO, Depth+1)) 1306 return true; 1307 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1308 1309 // If all of the demanded bits are known zero on one side, return the other. 1310 // These bits cannot contribute to the result of the 'or'. 1311 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1312 return TLO.CombineTo(Op, Op.getOperand(0)); 1313 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1314 return TLO.CombineTo(Op, Op.getOperand(1)); 1315 // If all of the potentially set bits on one side are known to be set on 1316 // the other side, just use the 'other' side. 1317 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1318 return TLO.CombineTo(Op, Op.getOperand(0)); 1319 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1320 return TLO.CombineTo(Op, Op.getOperand(1)); 1321 // If the RHS is a constant, see if we can simplify it. 1322 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1323 return true; 1324 // If the operation can be done in a smaller type, do so. 1325 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1326 return true; 1327 1328 // Output known-0 bits are only known if clear in both the LHS & RHS. 1329 KnownZero &= KnownZero2; 1330 // Output known-1 are known to be set if set in either the LHS | RHS. 1331 KnownOne |= KnownOne2; 1332 break; 1333 case ISD::XOR: 1334 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1335 KnownOne, TLO, Depth+1)) 1336 return true; 1337 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1338 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1339 KnownOne2, TLO, Depth+1)) 1340 return true; 1341 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1342 1343 // If all of the demanded bits are known zero on one side, return the other. 1344 // These bits cannot contribute to the result of the 'xor'. 1345 if ((KnownZero & NewMask) == NewMask) 1346 return TLO.CombineTo(Op, Op.getOperand(0)); 1347 if ((KnownZero2 & NewMask) == NewMask) 1348 return TLO.CombineTo(Op, Op.getOperand(1)); 1349 // If the operation can be done in a smaller type, do so. 1350 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1351 return true; 1352 1353 // If all of the unknown bits are known to be zero on one side or the other 1354 // (but not both) turn this into an *inclusive* or. 1355 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1356 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1357 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1358 Op.getOperand(0), 1359 Op.getOperand(1))); 1360 1361 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1362 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1363 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1364 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1365 1366 // If all of the demanded bits on one side are known, and all of the set 1367 // bits on that side are also known to be set on the other side, turn this 1368 // into an AND, as we know the bits will be cleared. 1369 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1370 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1371 if ((KnownOne & KnownOne2) == KnownOne) { 1372 EVT VT = Op.getValueType(); 1373 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1374 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1375 Op.getOperand(0), ANDC)); 1376 } 1377 } 1378 1379 // If the RHS is a constant, see if we can simplify it. 1380 // for XOR, we prefer to force bits to 1 if they will make a -1. 1381 // if we can't force bits, try to shrink constant 1382 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1383 APInt Expanded = C->getAPIntValue() | (~NewMask); 1384 // if we can expand it to have all bits set, do it 1385 if (Expanded.isAllOnesValue()) { 1386 if (Expanded != C->getAPIntValue()) { 1387 EVT VT = Op.getValueType(); 1388 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1389 TLO.DAG.getConstant(Expanded, VT)); 1390 return TLO.CombineTo(Op, New); 1391 } 1392 // if it already has all the bits set, nothing to change 1393 // but don't shrink either! 1394 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1395 return true; 1396 } 1397 } 1398 1399 KnownZero = KnownZeroOut; 1400 KnownOne = KnownOneOut; 1401 break; 1402 case ISD::SELECT: 1403 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1404 KnownOne, TLO, Depth+1)) 1405 return true; 1406 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1407 KnownOne2, TLO, Depth+1)) 1408 return true; 1409 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1410 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1411 1412 // If the operands are constants, see if we can simplify them. 1413 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1414 return true; 1415 1416 // Only known if known in both the LHS and RHS. 1417 KnownOne &= KnownOne2; 1418 KnownZero &= KnownZero2; 1419 break; 1420 case ISD::SELECT_CC: 1421 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1422 KnownOne, TLO, Depth+1)) 1423 return true; 1424 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1425 KnownOne2, TLO, Depth+1)) 1426 return true; 1427 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1428 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1429 1430 // If the operands are constants, see if we can simplify them. 1431 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1432 return true; 1433 1434 // Only known if known in both the LHS and RHS. 1435 KnownOne &= KnownOne2; 1436 KnownZero &= KnownZero2; 1437 break; 1438 case ISD::SHL: 1439 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1440 unsigned ShAmt = SA->getZExtValue(); 1441 SDValue InOp = Op.getOperand(0); 1442 1443 // If the shift count is an invalid immediate, don't do anything. 1444 if (ShAmt >= BitWidth) 1445 break; 1446 1447 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1448 // single shift. We can do this if the bottom bits (which are shifted 1449 // out) are never demanded. 1450 if (InOp.getOpcode() == ISD::SRL && 1451 isa<ConstantSDNode>(InOp.getOperand(1))) { 1452 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1453 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1454 unsigned Opc = ISD::SHL; 1455 int Diff = ShAmt-C1; 1456 if (Diff < 0) { 1457 Diff = -Diff; 1458 Opc = ISD::SRL; 1459 } 1460 1461 SDValue NewSA = 1462 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1463 EVT VT = Op.getValueType(); 1464 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1465 InOp.getOperand(0), NewSA)); 1466 } 1467 } 1468 1469 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1470 KnownZero, KnownOne, TLO, Depth+1)) 1471 return true; 1472 1473 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1474 // are not demanded. This will likely allow the anyext to be folded away. 1475 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1476 SDValue InnerOp = InOp.getNode()->getOperand(0); 1477 EVT InnerVT = InnerOp.getValueType(); 1478 unsigned InnerBits = InnerVT.getSizeInBits(); 1479 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 1480 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1481 EVT ShTy = getShiftAmountTy(InnerVT); 1482 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1483 ShTy = InnerVT; 1484 SDValue NarrowShl = 1485 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1486 TLO.DAG.getConstant(ShAmt, ShTy)); 1487 return 1488 TLO.CombineTo(Op, 1489 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1490 NarrowShl)); 1491 } 1492 } 1493 1494 KnownZero <<= SA->getZExtValue(); 1495 KnownOne <<= SA->getZExtValue(); 1496 // low bits known zero. 1497 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1498 } 1499 break; 1500 case ISD::SRL: 1501 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1502 EVT VT = Op.getValueType(); 1503 unsigned ShAmt = SA->getZExtValue(); 1504 unsigned VTSize = VT.getSizeInBits(); 1505 SDValue InOp = Op.getOperand(0); 1506 1507 // If the shift count is an invalid immediate, don't do anything. 1508 if (ShAmt >= BitWidth) 1509 break; 1510 1511 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1512 // single shift. We can do this if the top bits (which are shifted out) 1513 // are never demanded. 1514 if (InOp.getOpcode() == ISD::SHL && 1515 isa<ConstantSDNode>(InOp.getOperand(1))) { 1516 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1517 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1518 unsigned Opc = ISD::SRL; 1519 int Diff = ShAmt-C1; 1520 if (Diff < 0) { 1521 Diff = -Diff; 1522 Opc = ISD::SHL; 1523 } 1524 1525 SDValue NewSA = 1526 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1527 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1528 InOp.getOperand(0), NewSA)); 1529 } 1530 } 1531 1532 // Compute the new bits that are at the top now. 1533 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1534 KnownZero, KnownOne, TLO, Depth+1)) 1535 return true; 1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1537 KnownZero = KnownZero.lshr(ShAmt); 1538 KnownOne = KnownOne.lshr(ShAmt); 1539 1540 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1541 KnownZero |= HighBits; // High bits known zero. 1542 } 1543 break; 1544 case ISD::SRA: 1545 // If this is an arithmetic shift right and only the low-bit is set, we can 1546 // always convert this into a logical shr, even if the shift amount is 1547 // variable. The low bit of the shift cannot be an input sign bit unless 1548 // the shift amount is >= the size of the datatype, which is undefined. 1549 if (NewMask == 1) 1550 return TLO.CombineTo(Op, 1551 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1552 Op.getOperand(0), Op.getOperand(1))); 1553 1554 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1555 EVT VT = Op.getValueType(); 1556 unsigned ShAmt = SA->getZExtValue(); 1557 1558 // If the shift count is an invalid immediate, don't do anything. 1559 if (ShAmt >= BitWidth) 1560 break; 1561 1562 APInt InDemandedMask = (NewMask << ShAmt); 1563 1564 // If any of the demanded bits are produced by the sign extension, we also 1565 // demand the input sign bit. 1566 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1567 if (HighBits.intersects(NewMask)) 1568 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1569 1570 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1571 KnownZero, KnownOne, TLO, Depth+1)) 1572 return true; 1573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1574 KnownZero = KnownZero.lshr(ShAmt); 1575 KnownOne = KnownOne.lshr(ShAmt); 1576 1577 // Handle the sign bit, adjusted to where it is now in the mask. 1578 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1579 1580 // If the input sign bit is known to be zero, or if none of the top bits 1581 // are demanded, turn this into an unsigned shift right. 1582 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1583 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1584 Op.getOperand(0), 1585 Op.getOperand(1))); 1586 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1587 KnownOne |= HighBits; 1588 } 1589 } 1590 break; 1591 case ISD::SIGN_EXTEND_INREG: { 1592 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1593 1594 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 1595 // If we only care about the highest bit, don't bother shifting right. 1596 if (MsbMask == DemandedMask) { 1597 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 1598 SDValue InOp = Op.getOperand(0); 1599 1600 // Compute the correct shift amount type, which must be getShiftAmountTy 1601 // for scalar types after legalization. 1602 EVT ShiftAmtTy = Op.getValueType(); 1603 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 1604 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 1605 1606 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 1607 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1608 Op.getValueType(), InOp, ShiftAmt)); 1609 } 1610 1611 // Sign extension. Compute the demanded bits in the result that are not 1612 // present in the input. 1613 APInt NewBits = 1614 APInt::getHighBitsSet(BitWidth, 1615 BitWidth - ExVT.getScalarType().getSizeInBits()); 1616 1617 // If none of the extended bits are demanded, eliminate the sextinreg. 1618 if ((NewBits & NewMask) == 0) 1619 return TLO.CombineTo(Op, Op.getOperand(0)); 1620 1621 APInt InSignBit = 1622 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 1623 APInt InputDemandedBits = 1624 APInt::getLowBitsSet(BitWidth, 1625 ExVT.getScalarType().getSizeInBits()) & 1626 NewMask; 1627 1628 // Since the sign extended bits are demanded, we know that the sign 1629 // bit is demanded. 1630 InputDemandedBits |= InSignBit; 1631 1632 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1633 KnownZero, KnownOne, TLO, Depth+1)) 1634 return true; 1635 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1636 1637 // If the sign bit of the input is known set or clear, then we know the 1638 // top bits of the result. 1639 1640 // If the input sign bit is known zero, convert this into a zero extension. 1641 if (KnownZero.intersects(InSignBit)) 1642 return TLO.CombineTo(Op, 1643 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 1644 1645 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1646 KnownOne |= NewBits; 1647 KnownZero &= ~NewBits; 1648 } else { // Input sign bit unknown 1649 KnownZero &= ~NewBits; 1650 KnownOne &= ~NewBits; 1651 } 1652 break; 1653 } 1654 case ISD::ZERO_EXTEND: { 1655 unsigned OperandBitWidth = 1656 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1657 APInt InMask = NewMask.trunc(OperandBitWidth); 1658 1659 // If none of the top bits are demanded, convert this into an any_extend. 1660 APInt NewBits = 1661 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1662 if (!NewBits.intersects(NewMask)) 1663 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1664 Op.getValueType(), 1665 Op.getOperand(0))); 1666 1667 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1668 KnownZero, KnownOne, TLO, Depth+1)) 1669 return true; 1670 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1671 KnownZero = KnownZero.zext(BitWidth); 1672 KnownOne = KnownOne.zext(BitWidth); 1673 KnownZero |= NewBits; 1674 break; 1675 } 1676 case ISD::SIGN_EXTEND: { 1677 EVT InVT = Op.getOperand(0).getValueType(); 1678 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1679 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1680 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1681 APInt NewBits = ~InMask & NewMask; 1682 1683 // If none of the top bits are demanded, convert this into an any_extend. 1684 if (NewBits == 0) 1685 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1686 Op.getValueType(), 1687 Op.getOperand(0))); 1688 1689 // Since some of the sign extended bits are demanded, we know that the sign 1690 // bit is demanded. 1691 APInt InDemandedBits = InMask & NewMask; 1692 InDemandedBits |= InSignBit; 1693 InDemandedBits = InDemandedBits.trunc(InBits); 1694 1695 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1696 KnownOne, TLO, Depth+1)) 1697 return true; 1698 KnownZero = KnownZero.zext(BitWidth); 1699 KnownOne = KnownOne.zext(BitWidth); 1700 1701 // If the sign bit is known zero, convert this to a zero extend. 1702 if (KnownZero.intersects(InSignBit)) 1703 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1704 Op.getValueType(), 1705 Op.getOperand(0))); 1706 1707 // If the sign bit is known one, the top bits match. 1708 if (KnownOne.intersects(InSignBit)) { 1709 KnownOne |= NewBits; 1710 assert((KnownZero & NewBits) == 0); 1711 } else { // Otherwise, top bits aren't known. 1712 assert((KnownOne & NewBits) == 0); 1713 assert((KnownZero & NewBits) == 0); 1714 } 1715 break; 1716 } 1717 case ISD::ANY_EXTEND: { 1718 unsigned OperandBitWidth = 1719 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1720 APInt InMask = NewMask.trunc(OperandBitWidth); 1721 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1722 KnownZero, KnownOne, TLO, Depth+1)) 1723 return true; 1724 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1725 KnownZero = KnownZero.zext(BitWidth); 1726 KnownOne = KnownOne.zext(BitWidth); 1727 break; 1728 } 1729 case ISD::TRUNCATE: { 1730 // Simplify the input, using demanded bit information, and compute the known 1731 // zero/one bits live out. 1732 unsigned OperandBitWidth = 1733 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1734 APInt TruncMask = NewMask.zext(OperandBitWidth); 1735 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1736 KnownZero, KnownOne, TLO, Depth+1)) 1737 return true; 1738 KnownZero = KnownZero.trunc(BitWidth); 1739 KnownOne = KnownOne.trunc(BitWidth); 1740 1741 // If the input is only used by this truncate, see if we can shrink it based 1742 // on the known demanded bits. 1743 if (Op.getOperand(0).getNode()->hasOneUse()) { 1744 SDValue In = Op.getOperand(0); 1745 switch (In.getOpcode()) { 1746 default: break; 1747 case ISD::SRL: 1748 // Shrink SRL by a constant if none of the high bits shifted in are 1749 // demanded. 1750 if (TLO.LegalTypes() && 1751 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1752 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1753 // undesirable. 1754 break; 1755 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1756 if (!ShAmt) 1757 break; 1758 SDValue Shift = In.getOperand(1); 1759 if (TLO.LegalTypes()) { 1760 uint64_t ShVal = ShAmt->getZExtValue(); 1761 Shift = 1762 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1763 } 1764 1765 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1766 OperandBitWidth - BitWidth); 1767 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1768 1769 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1770 // None of the shifted in bits are needed. Add a truncate of the 1771 // shift input, then shift it. 1772 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1773 Op.getValueType(), 1774 In.getOperand(0)); 1775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1776 Op.getValueType(), 1777 NewTrunc, 1778 Shift)); 1779 } 1780 break; 1781 } 1782 } 1783 1784 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1785 break; 1786 } 1787 case ISD::AssertZext: { 1788 // AssertZext demands all of the high bits, plus any of the low bits 1789 // demanded by its users. 1790 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1791 APInt InMask = APInt::getLowBitsSet(BitWidth, 1792 VT.getSizeInBits()); 1793 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1794 KnownZero, KnownOne, TLO, Depth+1)) 1795 return true; 1796 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1797 1798 KnownZero |= ~InMask & NewMask; 1799 break; 1800 } 1801 case ISD::BITCAST: 1802 // If this is an FP->Int bitcast and if the sign bit is the only 1803 // thing demanded, turn this into a FGETSIGN. 1804 if (!TLO.LegalOperations() && 1805 !Op.getValueType().isVector() && 1806 !Op.getOperand(0).getValueType().isVector() && 1807 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1808 Op.getOperand(0).getValueType().isFloatingPoint()) { 1809 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1810 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1811 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1812 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1813 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1814 // place. We expect the SHL to be eliminated by other optimizations. 1815 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1816 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1817 if (!OpVTLegal && OpVTSizeInBits > 32) 1818 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1819 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1820 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1821 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1822 Op.getValueType(), 1823 Sign, ShAmt)); 1824 } 1825 } 1826 break; 1827 case ISD::ADD: 1828 case ISD::MUL: 1829 case ISD::SUB: { 1830 // Add, Sub, and Mul don't demand any bits in positions beyond that 1831 // of the highest bit demanded of them. 1832 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1833 BitWidth - NewMask.countLeadingZeros()); 1834 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1835 KnownOne2, TLO, Depth+1)) 1836 return true; 1837 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1838 KnownOne2, TLO, Depth+1)) 1839 return true; 1840 // See if the operation should be performed at a smaller bit width. 1841 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1842 return true; 1843 } 1844 // FALL THROUGH 1845 default: 1846 // Just use ComputeMaskedBits to compute output bits. 1847 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1848 break; 1849 } 1850 1851 // If we know the value of all of the demanded bits, return this as a 1852 // constant. 1853 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1854 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1855 1856 return false; 1857} 1858 1859/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1860/// in Mask are known to be either zero or one and return them in the 1861/// KnownZero/KnownOne bitsets. 1862void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1863 APInt &KnownZero, 1864 APInt &KnownOne, 1865 const SelectionDAG &DAG, 1866 unsigned Depth) const { 1867 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1868 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1869 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1870 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1871 "Should use MaskedValueIsZero if you don't know whether Op" 1872 " is a target node!"); 1873 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1874} 1875 1876/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1877/// targets that want to expose additional information about sign bits to the 1878/// DAG Combiner. 1879unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1880 unsigned Depth) const { 1881 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1882 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1883 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1884 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1885 "Should use ComputeNumSignBits if you don't know whether Op" 1886 " is a target node!"); 1887 return 1; 1888} 1889 1890/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1891/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1892/// determine which bit is set. 1893/// 1894static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1895 // A left-shift of a constant one will have exactly one bit set, because 1896 // shifting the bit off the end is undefined. 1897 if (Val.getOpcode() == ISD::SHL) 1898 if (ConstantSDNode *C = 1899 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1900 if (C->getAPIntValue() == 1) 1901 return true; 1902 1903 // Similarly, a right-shift of a constant sign-bit will have exactly 1904 // one bit set. 1905 if (Val.getOpcode() == ISD::SRL) 1906 if (ConstantSDNode *C = 1907 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1908 if (C->getAPIntValue().isSignBit()) 1909 return true; 1910 1911 // More could be done here, though the above checks are enough 1912 // to handle some common cases. 1913 1914 // Fall back to ComputeMaskedBits to catch other known cases. 1915 EVT OpVT = Val.getValueType(); 1916 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1917 APInt KnownZero, KnownOne; 1918 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1919 return (KnownZero.countPopulation() == BitWidth - 1) && 1920 (KnownOne.countPopulation() == 1); 1921} 1922 1923/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1924/// and cc. If it is unable to simplify it, return a null SDValue. 1925SDValue 1926TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1927 ISD::CondCode Cond, bool foldBooleans, 1928 DAGCombinerInfo &DCI, DebugLoc dl) const { 1929 SelectionDAG &DAG = DCI.DAG; 1930 1931 // These setcc operations always fold. 1932 switch (Cond) { 1933 default: break; 1934 case ISD::SETFALSE: 1935 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1936 case ISD::SETTRUE: 1937 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1938 } 1939 1940 // Ensure that the constant occurs on the RHS, and fold constant 1941 // comparisons. 1942 if (isa<ConstantSDNode>(N0.getNode())) 1943 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1944 1945 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1946 const APInt &C1 = N1C->getAPIntValue(); 1947 1948 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1949 // equality comparison, then we're just comparing whether X itself is 1950 // zero. 1951 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1952 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1953 N0.getOperand(1).getOpcode() == ISD::Constant) { 1954 const APInt &ShAmt 1955 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1956 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1957 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1958 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1959 // (srl (ctlz x), 5) == 0 -> X != 0 1960 // (srl (ctlz x), 5) != 1 -> X != 0 1961 Cond = ISD::SETNE; 1962 } else { 1963 // (srl (ctlz x), 5) != 0 -> X == 0 1964 // (srl (ctlz x), 5) == 1 -> X == 0 1965 Cond = ISD::SETEQ; 1966 } 1967 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1968 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1969 Zero, Cond); 1970 } 1971 } 1972 1973 SDValue CTPOP = N0; 1974 // Look through truncs that don't change the value of a ctpop. 1975 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1976 CTPOP = N0.getOperand(0); 1977 1978 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1979 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1980 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1981 EVT CTVT = CTPOP.getValueType(); 1982 SDValue CTOp = CTPOP.getOperand(0); 1983 1984 // (ctpop x) u< 2 -> (x & x-1) == 0 1985 // (ctpop x) u> 1 -> (x & x-1) != 0 1986 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1987 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1988 DAG.getConstant(1, CTVT)); 1989 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1990 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1991 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1992 } 1993 1994 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1995 } 1996 1997 // (zext x) == C --> x == (trunc C) 1998 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1999 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2000 unsigned MinBits = N0.getValueSizeInBits(); 2001 SDValue PreZExt; 2002 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 2003 // ZExt 2004 MinBits = N0->getOperand(0).getValueSizeInBits(); 2005 PreZExt = N0->getOperand(0); 2006 } else if (N0->getOpcode() == ISD::AND) { 2007 // DAGCombine turns costly ZExts into ANDs 2008 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 2009 if ((C->getAPIntValue()+1).isPowerOf2()) { 2010 MinBits = C->getAPIntValue().countTrailingOnes(); 2011 PreZExt = N0->getOperand(0); 2012 } 2013 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 2014 // ZEXTLOAD 2015 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 2016 MinBits = LN0->getMemoryVT().getSizeInBits(); 2017 PreZExt = N0; 2018 } 2019 } 2020 2021 // Make sure we're not loosing bits from the constant. 2022 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2023 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2024 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2025 // Will get folded away. 2026 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2027 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2028 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2029 } 2030 } 2031 } 2032 2033 // If the LHS is '(and load, const)', the RHS is 0, 2034 // the test is for equality or unsigned, and all 1 bits of the const are 2035 // in the same partial word, see if we can shorten the load. 2036 if (DCI.isBeforeLegalize() && 2037 N0.getOpcode() == ISD::AND && C1 == 0 && 2038 N0.getNode()->hasOneUse() && 2039 isa<LoadSDNode>(N0.getOperand(0)) && 2040 N0.getOperand(0).getNode()->hasOneUse() && 2041 isa<ConstantSDNode>(N0.getOperand(1))) { 2042 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2043 APInt bestMask; 2044 unsigned bestWidth = 0, bestOffset = 0; 2045 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2046 unsigned origWidth = N0.getValueType().getSizeInBits(); 2047 unsigned maskWidth = origWidth; 2048 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2049 // 8 bits, but have to be careful... 2050 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2051 origWidth = Lod->getMemoryVT().getSizeInBits(); 2052 const APInt &Mask = 2053 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2054 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2055 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2056 for (unsigned offset=0; offset<origWidth/width; offset++) { 2057 if ((newMask & Mask) == Mask) { 2058 if (!TD->isLittleEndian()) 2059 bestOffset = (origWidth/width - offset - 1) * (width/8); 2060 else 2061 bestOffset = (uint64_t)offset * (width/8); 2062 bestMask = Mask.lshr(offset * (width/8) * 8); 2063 bestWidth = width; 2064 break; 2065 } 2066 newMask = newMask << width; 2067 } 2068 } 2069 } 2070 if (bestWidth) { 2071 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2072 if (newVT.isRound()) { 2073 EVT PtrType = Lod->getOperand(1).getValueType(); 2074 SDValue Ptr = Lod->getBasePtr(); 2075 if (bestOffset != 0) 2076 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2077 DAG.getConstant(bestOffset, PtrType)); 2078 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2079 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2080 Lod->getPointerInfo().getWithOffset(bestOffset), 2081 false, false, false, NewAlign); 2082 return DAG.getSetCC(dl, VT, 2083 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2084 DAG.getConstant(bestMask.trunc(bestWidth), 2085 newVT)), 2086 DAG.getConstant(0LL, newVT), Cond); 2087 } 2088 } 2089 } 2090 2091 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2092 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2093 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2094 2095 // If the comparison constant has bits in the upper part, the 2096 // zero-extended value could never match. 2097 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2098 C1.getBitWidth() - InSize))) { 2099 switch (Cond) { 2100 case ISD::SETUGT: 2101 case ISD::SETUGE: 2102 case ISD::SETEQ: return DAG.getConstant(0, VT); 2103 case ISD::SETULT: 2104 case ISD::SETULE: 2105 case ISD::SETNE: return DAG.getConstant(1, VT); 2106 case ISD::SETGT: 2107 case ISD::SETGE: 2108 // True if the sign bit of C1 is set. 2109 return DAG.getConstant(C1.isNegative(), VT); 2110 case ISD::SETLT: 2111 case ISD::SETLE: 2112 // True if the sign bit of C1 isn't set. 2113 return DAG.getConstant(C1.isNonNegative(), VT); 2114 default: 2115 break; 2116 } 2117 } 2118 2119 // Otherwise, we can perform the comparison with the low bits. 2120 switch (Cond) { 2121 case ISD::SETEQ: 2122 case ISD::SETNE: 2123 case ISD::SETUGT: 2124 case ISD::SETUGE: 2125 case ISD::SETULT: 2126 case ISD::SETULE: { 2127 EVT newVT = N0.getOperand(0).getValueType(); 2128 if (DCI.isBeforeLegalizeOps() || 2129 (isOperationLegal(ISD::SETCC, newVT) && 2130 getCondCodeAction(Cond, newVT)==Legal)) 2131 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2132 DAG.getConstant(C1.trunc(InSize), newVT), 2133 Cond); 2134 break; 2135 } 2136 default: 2137 break; // todo, be more careful with signed comparisons 2138 } 2139 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2140 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2141 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2142 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2143 EVT ExtDstTy = N0.getValueType(); 2144 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2145 2146 // If the constant doesn't fit into the number of bits for the source of 2147 // the sign extension, it is impossible for both sides to be equal. 2148 if (C1.getMinSignedBits() > ExtSrcTyBits) 2149 return DAG.getConstant(Cond == ISD::SETNE, VT); 2150 2151 SDValue ZextOp; 2152 EVT Op0Ty = N0.getOperand(0).getValueType(); 2153 if (Op0Ty == ExtSrcTy) { 2154 ZextOp = N0.getOperand(0); 2155 } else { 2156 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2157 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2158 DAG.getConstant(Imm, Op0Ty)); 2159 } 2160 if (!DCI.isCalledByLegalizer()) 2161 DCI.AddToWorklist(ZextOp.getNode()); 2162 // Otherwise, make this a use of a zext. 2163 return DAG.getSetCC(dl, VT, ZextOp, 2164 DAG.getConstant(C1 & APInt::getLowBitsSet( 2165 ExtDstTyBits, 2166 ExtSrcTyBits), 2167 ExtDstTy), 2168 Cond); 2169 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2170 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2171 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2172 if (N0.getOpcode() == ISD::SETCC && 2173 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2174 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2175 if (TrueWhenTrue) 2176 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2177 // Invert the condition. 2178 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2179 CC = ISD::getSetCCInverse(CC, 2180 N0.getOperand(0).getValueType().isInteger()); 2181 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2182 } 2183 2184 if ((N0.getOpcode() == ISD::XOR || 2185 (N0.getOpcode() == ISD::AND && 2186 N0.getOperand(0).getOpcode() == ISD::XOR && 2187 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2188 isa<ConstantSDNode>(N0.getOperand(1)) && 2189 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2190 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2191 // can only do this if the top bits are known zero. 2192 unsigned BitWidth = N0.getValueSizeInBits(); 2193 if (DAG.MaskedValueIsZero(N0, 2194 APInt::getHighBitsSet(BitWidth, 2195 BitWidth-1))) { 2196 // Okay, get the un-inverted input value. 2197 SDValue Val; 2198 if (N0.getOpcode() == ISD::XOR) 2199 Val = N0.getOperand(0); 2200 else { 2201 assert(N0.getOpcode() == ISD::AND && 2202 N0.getOperand(0).getOpcode() == ISD::XOR); 2203 // ((X^1)&1)^1 -> X & 1 2204 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2205 N0.getOperand(0).getOperand(0), 2206 N0.getOperand(1)); 2207 } 2208 2209 return DAG.getSetCC(dl, VT, Val, N1, 2210 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2211 } 2212 } else if (N1C->getAPIntValue() == 1 && 2213 (VT == MVT::i1 || 2214 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2215 SDValue Op0 = N0; 2216 if (Op0.getOpcode() == ISD::TRUNCATE) 2217 Op0 = Op0.getOperand(0); 2218 2219 if ((Op0.getOpcode() == ISD::XOR) && 2220 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2221 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2222 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2223 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2224 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2225 Cond); 2226 } else if (Op0.getOpcode() == ISD::AND && 2227 isa<ConstantSDNode>(Op0.getOperand(1)) && 2228 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2229 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2230 if (Op0.getValueType().bitsGT(VT)) 2231 Op0 = DAG.getNode(ISD::AND, dl, VT, 2232 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2233 DAG.getConstant(1, VT)); 2234 else if (Op0.getValueType().bitsLT(VT)) 2235 Op0 = DAG.getNode(ISD::AND, dl, VT, 2236 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2237 DAG.getConstant(1, VT)); 2238 2239 return DAG.getSetCC(dl, VT, Op0, 2240 DAG.getConstant(0, Op0.getValueType()), 2241 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2242 } 2243 } 2244 } 2245 2246 APInt MinVal, MaxVal; 2247 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2248 if (ISD::isSignedIntSetCC(Cond)) { 2249 MinVal = APInt::getSignedMinValue(OperandBitSize); 2250 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2251 } else { 2252 MinVal = APInt::getMinValue(OperandBitSize); 2253 MaxVal = APInt::getMaxValue(OperandBitSize); 2254 } 2255 2256 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2257 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2258 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2259 // X >= C0 --> X > (C0-1) 2260 return DAG.getSetCC(dl, VT, N0, 2261 DAG.getConstant(C1-1, N1.getValueType()), 2262 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2263 } 2264 2265 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2266 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2267 // X <= C0 --> X < (C0+1) 2268 return DAG.getSetCC(dl, VT, N0, 2269 DAG.getConstant(C1+1, N1.getValueType()), 2270 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2271 } 2272 2273 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2274 return DAG.getConstant(0, VT); // X < MIN --> false 2275 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2276 return DAG.getConstant(1, VT); // X >= MIN --> true 2277 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2278 return DAG.getConstant(0, VT); // X > MAX --> false 2279 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2280 return DAG.getConstant(1, VT); // X <= MAX --> true 2281 2282 // Canonicalize setgt X, Min --> setne X, Min 2283 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2284 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2285 // Canonicalize setlt X, Max --> setne X, Max 2286 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2287 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2288 2289 // If we have setult X, 1, turn it into seteq X, 0 2290 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2291 return DAG.getSetCC(dl, VT, N0, 2292 DAG.getConstant(MinVal, N0.getValueType()), 2293 ISD::SETEQ); 2294 // If we have setugt X, Max-1, turn it into seteq X, Max 2295 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2296 return DAG.getSetCC(dl, VT, N0, 2297 DAG.getConstant(MaxVal, N0.getValueType()), 2298 ISD::SETEQ); 2299 2300 // If we have "setcc X, C0", check to see if we can shrink the immediate 2301 // by changing cc. 2302 2303 // SETUGT X, SINTMAX -> SETLT X, 0 2304 if (Cond == ISD::SETUGT && 2305 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2306 return DAG.getSetCC(dl, VT, N0, 2307 DAG.getConstant(0, N1.getValueType()), 2308 ISD::SETLT); 2309 2310 // SETULT X, SINTMIN -> SETGT X, -1 2311 if (Cond == ISD::SETULT && 2312 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2313 SDValue ConstMinusOne = 2314 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2315 N1.getValueType()); 2316 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2317 } 2318 2319 // Fold bit comparisons when we can. 2320 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2321 (VT == N0.getValueType() || 2322 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2323 N0.getOpcode() == ISD::AND) 2324 if (ConstantSDNode *AndRHS = 2325 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2326 EVT ShiftTy = DCI.isBeforeLegalize() ? 2327 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2328 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2329 // Perform the xform if the AND RHS is a single bit. 2330 if (AndRHS->getAPIntValue().isPowerOf2()) { 2331 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2332 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2333 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2334 } 2335 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2336 // (X & 8) == 8 --> (X & 8) >> 3 2337 // Perform the xform if C1 is a single bit. 2338 if (C1.isPowerOf2()) { 2339 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2340 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2341 DAG.getConstant(C1.logBase2(), ShiftTy))); 2342 } 2343 } 2344 } 2345 } 2346 2347 if (isa<ConstantFPSDNode>(N0.getNode())) { 2348 // Constant fold or commute setcc. 2349 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2350 if (O.getNode()) return O; 2351 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2352 // If the RHS of an FP comparison is a constant, simplify it away in 2353 // some cases. 2354 if (CFP->getValueAPF().isNaN()) { 2355 // If an operand is known to be a nan, we can fold it. 2356 switch (ISD::getUnorderedFlavor(Cond)) { 2357 default: llvm_unreachable("Unknown flavor!"); 2358 case 0: // Known false. 2359 return DAG.getConstant(0, VT); 2360 case 1: // Known true. 2361 return DAG.getConstant(1, VT); 2362 case 2: // Undefined. 2363 return DAG.getUNDEF(VT); 2364 } 2365 } 2366 2367 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2368 // constant if knowing that the operand is non-nan is enough. We prefer to 2369 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2370 // materialize 0.0. 2371 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2372 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2373 2374 // If the condition is not legal, see if we can find an equivalent one 2375 // which is legal. 2376 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2377 // If the comparison was an awkward floating-point == or != and one of 2378 // the comparison operands is infinity or negative infinity, convert the 2379 // condition to a less-awkward <= or >=. 2380 if (CFP->getValueAPF().isInfinity()) { 2381 if (CFP->getValueAPF().isNegative()) { 2382 if (Cond == ISD::SETOEQ && 2383 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2384 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2385 if (Cond == ISD::SETUEQ && 2386 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2387 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2388 if (Cond == ISD::SETUNE && 2389 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2390 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2391 if (Cond == ISD::SETONE && 2392 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2393 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2394 } else { 2395 if (Cond == ISD::SETOEQ && 2396 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2397 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2398 if (Cond == ISD::SETUEQ && 2399 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2400 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2401 if (Cond == ISD::SETUNE && 2402 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2403 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2404 if (Cond == ISD::SETONE && 2405 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2406 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2407 } 2408 } 2409 } 2410 } 2411 2412 if (N0 == N1) { 2413 // We can always fold X == X for integer setcc's. 2414 if (N0.getValueType().isInteger()) { 2415 switch (getBooleanContents(N0.getValueType().isVector())) { 2416 case UndefinedBooleanContent: 2417 case ZeroOrOneBooleanContent: 2418 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2419 case ZeroOrNegativeOneBooleanContent: 2420 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT); 2421 } 2422 } 2423 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2424 if (UOF == 2) // FP operators that are undefined on NaNs. 2425 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2426 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2427 return DAG.getConstant(UOF, VT); 2428 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2429 // if it is not already. 2430 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2431 if (NewCond != Cond) 2432 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2433 } 2434 2435 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2436 N0.getValueType().isInteger()) { 2437 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2438 N0.getOpcode() == ISD::XOR) { 2439 // Simplify (X+Y) == (X+Z) --> Y == Z 2440 if (N0.getOpcode() == N1.getOpcode()) { 2441 if (N0.getOperand(0) == N1.getOperand(0)) 2442 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2443 if (N0.getOperand(1) == N1.getOperand(1)) 2444 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2445 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2446 // If X op Y == Y op X, try other combinations. 2447 if (N0.getOperand(0) == N1.getOperand(1)) 2448 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2449 Cond); 2450 if (N0.getOperand(1) == N1.getOperand(0)) 2451 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2452 Cond); 2453 } 2454 } 2455 2456 // If RHS is a legal immediate value for a compare instruction, we need 2457 // to be careful about increasing register pressure needlessly. 2458 bool LegalRHSImm = false; 2459 2460 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2461 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2462 // Turn (X+C1) == C2 --> X == C2-C1 2463 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2464 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2465 DAG.getConstant(RHSC->getAPIntValue()- 2466 LHSR->getAPIntValue(), 2467 N0.getValueType()), Cond); 2468 } 2469 2470 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2471 if (N0.getOpcode() == ISD::XOR) 2472 // If we know that all of the inverted bits are zero, don't bother 2473 // performing the inversion. 2474 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2475 return 2476 DAG.getSetCC(dl, VT, N0.getOperand(0), 2477 DAG.getConstant(LHSR->getAPIntValue() ^ 2478 RHSC->getAPIntValue(), 2479 N0.getValueType()), 2480 Cond); 2481 } 2482 2483 // Turn (C1-X) == C2 --> X == C1-C2 2484 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2485 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2486 return 2487 DAG.getSetCC(dl, VT, N0.getOperand(1), 2488 DAG.getConstant(SUBC->getAPIntValue() - 2489 RHSC->getAPIntValue(), 2490 N0.getValueType()), 2491 Cond); 2492 } 2493 } 2494 2495 // Could RHSC fold directly into a compare? 2496 if (RHSC->getValueType(0).getSizeInBits() <= 64) 2497 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 2498 } 2499 2500 // Simplify (X+Z) == X --> Z == 0 2501 // Don't do this if X is an immediate that can fold into a cmp 2502 // instruction and X+Z has other uses. It could be an induction variable 2503 // chain, and the transform would increase register pressure. 2504 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 2505 if (N0.getOperand(0) == N1) 2506 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2507 DAG.getConstant(0, N0.getValueType()), Cond); 2508 if (N0.getOperand(1) == N1) { 2509 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2510 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2511 DAG.getConstant(0, N0.getValueType()), Cond); 2512 else if (N0.getNode()->hasOneUse()) { 2513 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2514 // (Z-X) == X --> Z == X<<1 2515 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 2516 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2517 if (!DCI.isCalledByLegalizer()) 2518 DCI.AddToWorklist(SH.getNode()); 2519 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2520 } 2521 } 2522 } 2523 } 2524 2525 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2526 N1.getOpcode() == ISD::XOR) { 2527 // Simplify X == (X+Z) --> Z == 0 2528 if (N1.getOperand(0) == N0) { 2529 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2530 DAG.getConstant(0, N1.getValueType()), Cond); 2531 } else if (N1.getOperand(1) == N0) { 2532 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2533 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2534 DAG.getConstant(0, N1.getValueType()), Cond); 2535 } else if (N1.getNode()->hasOneUse()) { 2536 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2537 // X == (Z-X) --> X<<1 == Z 2538 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2539 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2540 if (!DCI.isCalledByLegalizer()) 2541 DCI.AddToWorklist(SH.getNode()); 2542 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2543 } 2544 } 2545 } 2546 2547 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2548 // Note that where y is variable and is known to have at most 2549 // one bit set (for example, if it is z&1) we cannot do this; 2550 // the expressions are not equivalent when y==0. 2551 if (N0.getOpcode() == ISD::AND) 2552 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2553 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2554 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2555 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2556 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2557 } 2558 } 2559 if (N1.getOpcode() == ISD::AND) 2560 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2561 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2562 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2563 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2564 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2565 } 2566 } 2567 } 2568 2569 // Fold away ALL boolean setcc's. 2570 SDValue Temp; 2571 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2572 switch (Cond) { 2573 default: llvm_unreachable("Unknown integer setcc!"); 2574 case ISD::SETEQ: // X == Y -> ~(X^Y) 2575 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2576 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2577 if (!DCI.isCalledByLegalizer()) 2578 DCI.AddToWorklist(Temp.getNode()); 2579 break; 2580 case ISD::SETNE: // X != Y --> (X^Y) 2581 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2582 break; 2583 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2584 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2585 Temp = DAG.getNOT(dl, N0, MVT::i1); 2586 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2587 if (!DCI.isCalledByLegalizer()) 2588 DCI.AddToWorklist(Temp.getNode()); 2589 break; 2590 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2591 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2592 Temp = DAG.getNOT(dl, N1, MVT::i1); 2593 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2594 if (!DCI.isCalledByLegalizer()) 2595 DCI.AddToWorklist(Temp.getNode()); 2596 break; 2597 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2598 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2599 Temp = DAG.getNOT(dl, N0, MVT::i1); 2600 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2601 if (!DCI.isCalledByLegalizer()) 2602 DCI.AddToWorklist(Temp.getNode()); 2603 break; 2604 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2605 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2606 Temp = DAG.getNOT(dl, N1, MVT::i1); 2607 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2608 break; 2609 } 2610 if (VT != MVT::i1) { 2611 if (!DCI.isCalledByLegalizer()) 2612 DCI.AddToWorklist(N0.getNode()); 2613 // FIXME: If running after legalize, we probably can't do this. 2614 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2615 } 2616 return N0; 2617 } 2618 2619 // Could not fold it. 2620 return SDValue(); 2621} 2622 2623/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2624/// node is a GlobalAddress + offset. 2625bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2626 int64_t &Offset) const { 2627 if (isa<GlobalAddressSDNode>(N)) { 2628 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2629 GA = GASD->getGlobal(); 2630 Offset += GASD->getOffset(); 2631 return true; 2632 } 2633 2634 if (N->getOpcode() == ISD::ADD) { 2635 SDValue N1 = N->getOperand(0); 2636 SDValue N2 = N->getOperand(1); 2637 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2638 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2639 if (V) { 2640 Offset += V->getSExtValue(); 2641 return true; 2642 } 2643 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2644 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2645 if (V) { 2646 Offset += V->getSExtValue(); 2647 return true; 2648 } 2649 } 2650 } 2651 2652 return false; 2653} 2654 2655 2656SDValue TargetLowering:: 2657PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2658 // Default implementation: no optimization. 2659 return SDValue(); 2660} 2661 2662//===----------------------------------------------------------------------===// 2663// Inline Assembler Implementation Methods 2664//===----------------------------------------------------------------------===// 2665 2666 2667TargetLowering::ConstraintType 2668TargetLowering::getConstraintType(const std::string &Constraint) const { 2669 if (Constraint.size() == 1) { 2670 switch (Constraint[0]) { 2671 default: break; 2672 case 'r': return C_RegisterClass; 2673 case 'm': // memory 2674 case 'o': // offsetable 2675 case 'V': // not offsetable 2676 return C_Memory; 2677 case 'i': // Simple Integer or Relocatable Constant 2678 case 'n': // Simple Integer 2679 case 'E': // Floating Point Constant 2680 case 'F': // Floating Point Constant 2681 case 's': // Relocatable Constant 2682 case 'p': // Address. 2683 case 'X': // Allow ANY value. 2684 case 'I': // Target registers. 2685 case 'J': 2686 case 'K': 2687 case 'L': 2688 case 'M': 2689 case 'N': 2690 case 'O': 2691 case 'P': 2692 case '<': 2693 case '>': 2694 return C_Other; 2695 } 2696 } 2697 2698 if (Constraint.size() > 1 && Constraint[0] == '{' && 2699 Constraint[Constraint.size()-1] == '}') 2700 return C_Register; 2701 return C_Unknown; 2702} 2703 2704/// LowerXConstraint - try to replace an X constraint, which matches anything, 2705/// with another that has more specific requirements based on the type of the 2706/// corresponding operand. 2707const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2708 if (ConstraintVT.isInteger()) 2709 return "r"; 2710 if (ConstraintVT.isFloatingPoint()) 2711 return "f"; // works for many targets 2712 return 0; 2713} 2714 2715/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2716/// vector. If it is invalid, don't add anything to Ops. 2717void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2718 std::string &Constraint, 2719 std::vector<SDValue> &Ops, 2720 SelectionDAG &DAG) const { 2721 2722 if (Constraint.length() > 1) return; 2723 2724 char ConstraintLetter = Constraint[0]; 2725 switch (ConstraintLetter) { 2726 default: break; 2727 case 'X': // Allows any operand; labels (basic block) use this. 2728 if (Op.getOpcode() == ISD::BasicBlock) { 2729 Ops.push_back(Op); 2730 return; 2731 } 2732 // fall through 2733 case 'i': // Simple Integer or Relocatable Constant 2734 case 'n': // Simple Integer 2735 case 's': { // Relocatable Constant 2736 // These operands are interested in values of the form (GV+C), where C may 2737 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2738 // is possible and fine if either GV or C are missing. 2739 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2740 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2741 2742 // If we have "(add GV, C)", pull out GV/C 2743 if (Op.getOpcode() == ISD::ADD) { 2744 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2745 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2746 if (C == 0 || GA == 0) { 2747 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2748 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2749 } 2750 if (C == 0 || GA == 0) 2751 C = 0, GA = 0; 2752 } 2753 2754 // If we find a valid operand, map to the TargetXXX version so that the 2755 // value itself doesn't get selected. 2756 if (GA) { // Either &GV or &GV+C 2757 if (ConstraintLetter != 'n') { 2758 int64_t Offs = GA->getOffset(); 2759 if (C) Offs += C->getZExtValue(); 2760 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2761 C ? C->getDebugLoc() : DebugLoc(), 2762 Op.getValueType(), Offs)); 2763 return; 2764 } 2765 } 2766 if (C) { // just C, no GV. 2767 // Simple constants are not allowed for 's'. 2768 if (ConstraintLetter != 's') { 2769 // gcc prints these as sign extended. Sign extend value to 64 bits 2770 // now; without this it would get ZExt'd later in 2771 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2772 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2773 MVT::i64)); 2774 return; 2775 } 2776 } 2777 break; 2778 } 2779 } 2780} 2781 2782std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2783getRegForInlineAsmConstraint(const std::string &Constraint, 2784 EVT VT) const { 2785 if (Constraint[0] != '{') 2786 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2787 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2788 2789 // Remove the braces from around the name. 2790 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2791 2792 // Figure out which register class contains this reg. 2793 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2794 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2795 E = RI->regclass_end(); RCI != E; ++RCI) { 2796 const TargetRegisterClass *RC = *RCI; 2797 2798 // If none of the value types for this register class are valid, we 2799 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2800 if (!isLegalRC(RC)) 2801 continue; 2802 2803 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2804 I != E; ++I) { 2805 if (RegName.equals_lower(RI->getName(*I))) 2806 return std::make_pair(*I, RC); 2807 } 2808 } 2809 2810 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2811} 2812 2813//===----------------------------------------------------------------------===// 2814// Constraint Selection. 2815 2816/// isMatchingInputConstraint - Return true of this is an input operand that is 2817/// a matching constraint like "4". 2818bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2819 assert(!ConstraintCode.empty() && "No known constraint!"); 2820 return isdigit(ConstraintCode[0]); 2821} 2822 2823/// getMatchedOperand - If this is an input matching constraint, this method 2824/// returns the output operand it matches. 2825unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2826 assert(!ConstraintCode.empty() && "No known constraint!"); 2827 return atoi(ConstraintCode.c_str()); 2828} 2829 2830 2831/// ParseConstraints - Split up the constraint string from the inline 2832/// assembly value into the specific constraints and their prefixes, 2833/// and also tie in the associated operand values. 2834/// If this returns an empty vector, and if the constraint string itself 2835/// isn't empty, there was an error parsing. 2836TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2837 ImmutableCallSite CS) const { 2838 /// ConstraintOperands - Information about all of the constraints. 2839 AsmOperandInfoVector ConstraintOperands; 2840 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2841 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2842 2843 // Do a prepass over the constraints, canonicalizing them, and building up the 2844 // ConstraintOperands list. 2845 InlineAsm::ConstraintInfoVector 2846 ConstraintInfos = IA->ParseConstraints(); 2847 2848 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2849 unsigned ResNo = 0; // ResNo - The result number of the next output. 2850 2851 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2852 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2853 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2854 2855 // Update multiple alternative constraint count. 2856 if (OpInfo.multipleAlternatives.size() > maCount) 2857 maCount = OpInfo.multipleAlternatives.size(); 2858 2859 OpInfo.ConstraintVT = MVT::Other; 2860 2861 // Compute the value type for each operand. 2862 switch (OpInfo.Type) { 2863 case InlineAsm::isOutput: 2864 // Indirect outputs just consume an argument. 2865 if (OpInfo.isIndirect) { 2866 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2867 break; 2868 } 2869 2870 // The return value of the call is this value. As such, there is no 2871 // corresponding argument. 2872 assert(!CS.getType()->isVoidTy() && 2873 "Bad inline asm!"); 2874 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2875 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2876 } else { 2877 assert(ResNo == 0 && "Asm only has one result!"); 2878 OpInfo.ConstraintVT = getValueType(CS.getType()); 2879 } 2880 ++ResNo; 2881 break; 2882 case InlineAsm::isInput: 2883 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2884 break; 2885 case InlineAsm::isClobber: 2886 // Nothing to do. 2887 break; 2888 } 2889 2890 if (OpInfo.CallOperandVal) { 2891 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2892 if (OpInfo.isIndirect) { 2893 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2894 if (!PtrTy) 2895 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2896 OpTy = PtrTy->getElementType(); 2897 } 2898 2899 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2900 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2901 if (STy->getNumElements() == 1) 2902 OpTy = STy->getElementType(0); 2903 2904 // If OpTy is not a single value, it may be a struct/union that we 2905 // can tile with integers. 2906 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2907 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2908 switch (BitSize) { 2909 default: break; 2910 case 1: 2911 case 8: 2912 case 16: 2913 case 32: 2914 case 64: 2915 case 128: 2916 OpInfo.ConstraintVT = 2917 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2918 break; 2919 } 2920 } else if (dyn_cast<PointerType>(OpTy)) { 2921 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2922 } else { 2923 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2924 } 2925 } 2926 } 2927 2928 // If we have multiple alternative constraints, select the best alternative. 2929 if (ConstraintInfos.size()) { 2930 if (maCount) { 2931 unsigned bestMAIndex = 0; 2932 int bestWeight = -1; 2933 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2934 int weight = -1; 2935 unsigned maIndex; 2936 // Compute the sums of the weights for each alternative, keeping track 2937 // of the best (highest weight) one so far. 2938 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2939 int weightSum = 0; 2940 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2941 cIndex != eIndex; ++cIndex) { 2942 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2943 if (OpInfo.Type == InlineAsm::isClobber) 2944 continue; 2945 2946 // If this is an output operand with a matching input operand, 2947 // look up the matching input. If their types mismatch, e.g. one 2948 // is an integer, the other is floating point, or their sizes are 2949 // different, flag it as an maCantMatch. 2950 if (OpInfo.hasMatchingInput()) { 2951 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2952 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2953 if ((OpInfo.ConstraintVT.isInteger() != 2954 Input.ConstraintVT.isInteger()) || 2955 (OpInfo.ConstraintVT.getSizeInBits() != 2956 Input.ConstraintVT.getSizeInBits())) { 2957 weightSum = -1; // Can't match. 2958 break; 2959 } 2960 } 2961 } 2962 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2963 if (weight == -1) { 2964 weightSum = -1; 2965 break; 2966 } 2967 weightSum += weight; 2968 } 2969 // Update best. 2970 if (weightSum > bestWeight) { 2971 bestWeight = weightSum; 2972 bestMAIndex = maIndex; 2973 } 2974 } 2975 2976 // Now select chosen alternative in each constraint. 2977 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2978 cIndex != eIndex; ++cIndex) { 2979 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2980 if (cInfo.Type == InlineAsm::isClobber) 2981 continue; 2982 cInfo.selectAlternative(bestMAIndex); 2983 } 2984 } 2985 } 2986 2987 // Check and hook up tied operands, choose constraint code to use. 2988 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2989 cIndex != eIndex; ++cIndex) { 2990 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2991 2992 // If this is an output operand with a matching input operand, look up the 2993 // matching input. If their types mismatch, e.g. one is an integer, the 2994 // other is floating point, or their sizes are different, flag it as an 2995 // error. 2996 if (OpInfo.hasMatchingInput()) { 2997 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2998 2999 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3000 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 3001 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 3002 std::pair<unsigned, const TargetRegisterClass*> InputRC = 3003 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 3004 if ((OpInfo.ConstraintVT.isInteger() != 3005 Input.ConstraintVT.isInteger()) || 3006 (MatchRC.second != InputRC.second)) { 3007 report_fatal_error("Unsupported asm: input constraint" 3008 " with a matching output constraint of" 3009 " incompatible type!"); 3010 } 3011 } 3012 3013 } 3014 } 3015 3016 return ConstraintOperands; 3017} 3018 3019 3020/// getConstraintGenerality - Return an integer indicating how general CT 3021/// is. 3022static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3023 switch (CT) { 3024 case TargetLowering::C_Other: 3025 case TargetLowering::C_Unknown: 3026 return 0; 3027 case TargetLowering::C_Register: 3028 return 1; 3029 case TargetLowering::C_RegisterClass: 3030 return 2; 3031 case TargetLowering::C_Memory: 3032 return 3; 3033 } 3034 llvm_unreachable("Invalid constraint type"); 3035} 3036 3037/// Examine constraint type and operand type and determine a weight value. 3038/// This object must already have been set up with the operand type 3039/// and the current alternative constraint selected. 3040TargetLowering::ConstraintWeight 3041 TargetLowering::getMultipleConstraintMatchWeight( 3042 AsmOperandInfo &info, int maIndex) const { 3043 InlineAsm::ConstraintCodeVector *rCodes; 3044 if (maIndex >= (int)info.multipleAlternatives.size()) 3045 rCodes = &info.Codes; 3046 else 3047 rCodes = &info.multipleAlternatives[maIndex].Codes; 3048 ConstraintWeight BestWeight = CW_Invalid; 3049 3050 // Loop over the options, keeping track of the most general one. 3051 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3052 ConstraintWeight weight = 3053 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3054 if (weight > BestWeight) 3055 BestWeight = weight; 3056 } 3057 3058 return BestWeight; 3059} 3060 3061/// Examine constraint type and operand type and determine a weight value. 3062/// This object must already have been set up with the operand type 3063/// and the current alternative constraint selected. 3064TargetLowering::ConstraintWeight 3065 TargetLowering::getSingleConstraintMatchWeight( 3066 AsmOperandInfo &info, const char *constraint) const { 3067 ConstraintWeight weight = CW_Invalid; 3068 Value *CallOperandVal = info.CallOperandVal; 3069 // If we don't have a value, we can't do a match, 3070 // but allow it at the lowest weight. 3071 if (CallOperandVal == NULL) 3072 return CW_Default; 3073 // Look at the constraint type. 3074 switch (*constraint) { 3075 case 'i': // immediate integer. 3076 case 'n': // immediate integer with a known value. 3077 if (isa<ConstantInt>(CallOperandVal)) 3078 weight = CW_Constant; 3079 break; 3080 case 's': // non-explicit intregal immediate. 3081 if (isa<GlobalValue>(CallOperandVal)) 3082 weight = CW_Constant; 3083 break; 3084 case 'E': // immediate float if host format. 3085 case 'F': // immediate float. 3086 if (isa<ConstantFP>(CallOperandVal)) 3087 weight = CW_Constant; 3088 break; 3089 case '<': // memory operand with autodecrement. 3090 case '>': // memory operand with autoincrement. 3091 case 'm': // memory operand. 3092 case 'o': // offsettable memory operand 3093 case 'V': // non-offsettable memory operand 3094 weight = CW_Memory; 3095 break; 3096 case 'r': // general register. 3097 case 'g': // general register, memory operand or immediate integer. 3098 // note: Clang converts "g" to "imr". 3099 if (CallOperandVal->getType()->isIntegerTy()) 3100 weight = CW_Register; 3101 break; 3102 case 'X': // any operand. 3103 default: 3104 weight = CW_Default; 3105 break; 3106 } 3107 return weight; 3108} 3109 3110/// ChooseConstraint - If there are multiple different constraints that we 3111/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3112/// This is somewhat tricky: constraints fall into four classes: 3113/// Other -> immediates and magic values 3114/// Register -> one specific register 3115/// RegisterClass -> a group of regs 3116/// Memory -> memory 3117/// Ideally, we would pick the most specific constraint possible: if we have 3118/// something that fits into a register, we would pick it. The problem here 3119/// is that if we have something that could either be in a register or in 3120/// memory that use of the register could cause selection of *other* 3121/// operands to fail: they might only succeed if we pick memory. Because of 3122/// this the heuristic we use is: 3123/// 3124/// 1) If there is an 'other' constraint, and if the operand is valid for 3125/// that constraint, use it. This makes us take advantage of 'i' 3126/// constraints when available. 3127/// 2) Otherwise, pick the most general constraint present. This prefers 3128/// 'm' over 'r', for example. 3129/// 3130static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3131 const TargetLowering &TLI, 3132 SDValue Op, SelectionDAG *DAG) { 3133 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3134 unsigned BestIdx = 0; 3135 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3136 int BestGenerality = -1; 3137 3138 // Loop over the options, keeping track of the most general one. 3139 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3140 TargetLowering::ConstraintType CType = 3141 TLI.getConstraintType(OpInfo.Codes[i]); 3142 3143 // If this is an 'other' constraint, see if the operand is valid for it. 3144 // For example, on X86 we might have an 'rI' constraint. If the operand 3145 // is an integer in the range [0..31] we want to use I (saving a load 3146 // of a register), otherwise we must use 'r'. 3147 if (CType == TargetLowering::C_Other && Op.getNode()) { 3148 assert(OpInfo.Codes[i].size() == 1 && 3149 "Unhandled multi-letter 'other' constraint"); 3150 std::vector<SDValue> ResultOps; 3151 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3152 ResultOps, *DAG); 3153 if (!ResultOps.empty()) { 3154 BestType = CType; 3155 BestIdx = i; 3156 break; 3157 } 3158 } 3159 3160 // Things with matching constraints can only be registers, per gcc 3161 // documentation. This mainly affects "g" constraints. 3162 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3163 continue; 3164 3165 // This constraint letter is more general than the previous one, use it. 3166 int Generality = getConstraintGenerality(CType); 3167 if (Generality > BestGenerality) { 3168 BestType = CType; 3169 BestIdx = i; 3170 BestGenerality = Generality; 3171 } 3172 } 3173 3174 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3175 OpInfo.ConstraintType = BestType; 3176} 3177 3178/// ComputeConstraintToUse - Determines the constraint code and constraint 3179/// type to use for the specific AsmOperandInfo, setting 3180/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3181void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3182 SDValue Op, 3183 SelectionDAG *DAG) const { 3184 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3185 3186 // Single-letter constraints ('r') are very common. 3187 if (OpInfo.Codes.size() == 1) { 3188 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3189 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3190 } else { 3191 ChooseConstraint(OpInfo, *this, Op, DAG); 3192 } 3193 3194 // 'X' matches anything. 3195 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3196 // Labels and constants are handled elsewhere ('X' is the only thing 3197 // that matches labels). For Functions, the type here is the type of 3198 // the result, which is not what we want to look at; leave them alone. 3199 Value *v = OpInfo.CallOperandVal; 3200 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3201 OpInfo.CallOperandVal = v; 3202 return; 3203 } 3204 3205 // Otherwise, try to resolve it to something we know about by looking at 3206 // the actual operand type. 3207 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3208 OpInfo.ConstraintCode = Repl; 3209 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3210 } 3211 } 3212} 3213 3214//===----------------------------------------------------------------------===// 3215// Loop Strength Reduction hooks 3216//===----------------------------------------------------------------------===// 3217 3218/// isLegalAddressingMode - Return true if the addressing mode represented 3219/// by AM is legal for this target, for a load/store of the specified type. 3220bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3221 Type *Ty) const { 3222 // The default implementation of this implements a conservative RISCy, r+r and 3223 // r+i addr mode. 3224 3225 // Allows a sign-extended 16-bit immediate field. 3226 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3227 return false; 3228 3229 // No global is ever allowed as a base. 3230 if (AM.BaseGV) 3231 return false; 3232 3233 // Only support r+r, 3234 switch (AM.Scale) { 3235 case 0: // "r+i" or just "i", depending on HasBaseReg. 3236 break; 3237 case 1: 3238 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3239 return false; 3240 // Otherwise we have r+r or r+i. 3241 break; 3242 case 2: 3243 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3244 return false; 3245 // Allow 2*r as r+r. 3246 break; 3247 } 3248 3249 return true; 3250} 3251 3252/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3253/// with the multiplicative inverse of the constant. 3254SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3255 SelectionDAG &DAG) const { 3256 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3257 APInt d = C->getAPIntValue(); 3258 assert(d != 0 && "Division by zero!"); 3259 3260 // Shift the value upfront if it is even, so the LSB is one. 3261 unsigned ShAmt = d.countTrailingZeros(); 3262 if (ShAmt) { 3263 // TODO: For UDIV use SRL instead of SRA. 3264 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3265 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3266 d = d.ashr(ShAmt); 3267 } 3268 3269 // Calculate the multiplicative inverse, using Newton's method. 3270 APInt t, xn = d; 3271 while ((t = d*xn) != 1) 3272 xn *= APInt(d.getBitWidth(), 2) - t; 3273 3274 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3275 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3276} 3277 3278/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3279/// return a DAG expression to select that will generate the same value by 3280/// multiplying by a magic number. See: 3281/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3282SDValue TargetLowering:: 3283BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3284 std::vector<SDNode*>* Created) const { 3285 EVT VT = N->getValueType(0); 3286 DebugLoc dl= N->getDebugLoc(); 3287 3288 // Check to see if we can do this. 3289 // FIXME: We should be more aggressive here. 3290 if (!isTypeLegal(VT)) 3291 return SDValue(); 3292 3293 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3294 APInt::ms magics = d.magic(); 3295 3296 // Multiply the numerator (operand 0) by the magic value 3297 // FIXME: We should support doing a MUL in a wider type 3298 SDValue Q; 3299 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3300 isOperationLegalOrCustom(ISD::MULHS, VT)) 3301 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3302 DAG.getConstant(magics.m, VT)); 3303 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3304 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3305 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3306 N->getOperand(0), 3307 DAG.getConstant(magics.m, VT)).getNode(), 1); 3308 else 3309 return SDValue(); // No mulhs or equvialent 3310 // If d > 0 and m < 0, add the numerator 3311 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3312 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3313 if (Created) 3314 Created->push_back(Q.getNode()); 3315 } 3316 // If d < 0 and m > 0, subtract the numerator. 3317 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3318 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3319 if (Created) 3320 Created->push_back(Q.getNode()); 3321 } 3322 // Shift right algebraic if shift value is nonzero 3323 if (magics.s > 0) { 3324 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3325 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3326 if (Created) 3327 Created->push_back(Q.getNode()); 3328 } 3329 // Extract the sign bit and add it to the quotient 3330 SDValue T = 3331 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3332 getShiftAmountTy(Q.getValueType()))); 3333 if (Created) 3334 Created->push_back(T.getNode()); 3335 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3336} 3337 3338/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3339/// return a DAG expression to select that will generate the same value by 3340/// multiplying by a magic number. See: 3341/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3342SDValue TargetLowering:: 3343BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3344 std::vector<SDNode*>* Created) const { 3345 EVT VT = N->getValueType(0); 3346 DebugLoc dl = N->getDebugLoc(); 3347 3348 // Check to see if we can do this. 3349 // FIXME: We should be more aggressive here. 3350 if (!isTypeLegal(VT)) 3351 return SDValue(); 3352 3353 // FIXME: We should use a narrower constant when the upper 3354 // bits are known to be zero. 3355 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3356 APInt::mu magics = N1C.magicu(); 3357 3358 SDValue Q = N->getOperand(0); 3359 3360 // If the divisor is even, we can avoid using the expensive fixup by shifting 3361 // the divided value upfront. 3362 if (magics.a != 0 && !N1C[0]) { 3363 unsigned Shift = N1C.countTrailingZeros(); 3364 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3365 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3366 if (Created) 3367 Created->push_back(Q.getNode()); 3368 3369 // Get magic number for the shifted divisor. 3370 magics = N1C.lshr(Shift).magicu(Shift); 3371 assert(magics.a == 0 && "Should use cheap fixup now"); 3372 } 3373 3374 // Multiply the numerator (operand 0) by the magic value 3375 // FIXME: We should support doing a MUL in a wider type 3376 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3377 isOperationLegalOrCustom(ISD::MULHU, VT)) 3378 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3379 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3380 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3381 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3382 DAG.getConstant(magics.m, VT)).getNode(), 1); 3383 else 3384 return SDValue(); // No mulhu or equvialent 3385 if (Created) 3386 Created->push_back(Q.getNode()); 3387 3388 if (magics.a == 0) { 3389 assert(magics.s < N1C.getBitWidth() && 3390 "We shouldn't generate an undefined shift!"); 3391 return DAG.getNode(ISD::SRL, dl, VT, Q, 3392 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3393 } else { 3394 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3395 if (Created) 3396 Created->push_back(NPQ.getNode()); 3397 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3398 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3399 if (Created) 3400 Created->push_back(NPQ.getNode()); 3401 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3402 if (Created) 3403 Created->push_back(NPQ.getNode()); 3404 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3405 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3406 } 3407} 3408