TargetLowering.cpp revision 207618
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Target/TargetSubtarget.h" 22#include "llvm/GlobalVariable.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 245 Names[RTLIB::OEQ_F32] = "__eqsf2"; 246 Names[RTLIB::OEQ_F64] = "__eqdf2"; 247 Names[RTLIB::UNE_F32] = "__nesf2"; 248 Names[RTLIB::UNE_F64] = "__nedf2"; 249 Names[RTLIB::OGE_F32] = "__gesf2"; 250 Names[RTLIB::OGE_F64] = "__gedf2"; 251 Names[RTLIB::OLT_F32] = "__ltsf2"; 252 Names[RTLIB::OLT_F64] = "__ltdf2"; 253 Names[RTLIB::OLE_F32] = "__lesf2"; 254 Names[RTLIB::OLE_F64] = "__ledf2"; 255 Names[RTLIB::OGT_F32] = "__gtsf2"; 256 Names[RTLIB::OGT_F64] = "__gtdf2"; 257 Names[RTLIB::UO_F32] = "__unordsf2"; 258 Names[RTLIB::UO_F64] = "__unorddf2"; 259 Names[RTLIB::O_F32] = "__unordsf2"; 260 Names[RTLIB::O_F64] = "__unorddf2"; 261 Names[RTLIB::MEMCPY] = "memcpy"; 262 Names[RTLIB::MEMMOVE] = "memmove"; 263 Names[RTLIB::MEMSET] = "memset"; 264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 265} 266 267/// InitLibcallCallingConvs - Set default libcall CallingConvs. 268/// 269static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 270 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 271 CCs[i] = CallingConv::C; 272 } 273} 274 275/// getFPEXT - Return the FPEXT_*_* value for the given types, or 276/// UNKNOWN_LIBCALL if there is none. 277RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 278 if (OpVT == MVT::f32) { 279 if (RetVT == MVT::f64) 280 return FPEXT_F32_F64; 281 } 282 283 return UNKNOWN_LIBCALL; 284} 285 286/// getFPROUND - Return the FPROUND_*_* value for the given types, or 287/// UNKNOWN_LIBCALL if there is none. 288RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 289 if (RetVT == MVT::f32) { 290 if (OpVT == MVT::f64) 291 return FPROUND_F64_F32; 292 if (OpVT == MVT::f80) 293 return FPROUND_F80_F32; 294 if (OpVT == MVT::ppcf128) 295 return FPROUND_PPCF128_F32; 296 } else if (RetVT == MVT::f64) { 297 if (OpVT == MVT::f80) 298 return FPROUND_F80_F64; 299 if (OpVT == MVT::ppcf128) 300 return FPROUND_PPCF128_F64; 301 } 302 303 return UNKNOWN_LIBCALL; 304} 305 306/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 307/// UNKNOWN_LIBCALL if there is none. 308RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 309 if (OpVT == MVT::f32) { 310 if (RetVT == MVT::i8) 311 return FPTOSINT_F32_I8; 312 if (RetVT == MVT::i16) 313 return FPTOSINT_F32_I16; 314 if (RetVT == MVT::i32) 315 return FPTOSINT_F32_I32; 316 if (RetVT == MVT::i64) 317 return FPTOSINT_F32_I64; 318 if (RetVT == MVT::i128) 319 return FPTOSINT_F32_I128; 320 } else if (OpVT == MVT::f64) { 321 if (RetVT == MVT::i8) 322 return FPTOSINT_F64_I8; 323 if (RetVT == MVT::i16) 324 return FPTOSINT_F64_I16; 325 if (RetVT == MVT::i32) 326 return FPTOSINT_F64_I32; 327 if (RetVT == MVT::i64) 328 return FPTOSINT_F64_I64; 329 if (RetVT == MVT::i128) 330 return FPTOSINT_F64_I128; 331 } else if (OpVT == MVT::f80) { 332 if (RetVT == MVT::i32) 333 return FPTOSINT_F80_I32; 334 if (RetVT == MVT::i64) 335 return FPTOSINT_F80_I64; 336 if (RetVT == MVT::i128) 337 return FPTOSINT_F80_I128; 338 } else if (OpVT == MVT::ppcf128) { 339 if (RetVT == MVT::i32) 340 return FPTOSINT_PPCF128_I32; 341 if (RetVT == MVT::i64) 342 return FPTOSINT_PPCF128_I64; 343 if (RetVT == MVT::i128) 344 return FPTOSINT_PPCF128_I128; 345 } 346 return UNKNOWN_LIBCALL; 347} 348 349/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 350/// UNKNOWN_LIBCALL if there is none. 351RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 352 if (OpVT == MVT::f32) { 353 if (RetVT == MVT::i8) 354 return FPTOUINT_F32_I8; 355 if (RetVT == MVT::i16) 356 return FPTOUINT_F32_I16; 357 if (RetVT == MVT::i32) 358 return FPTOUINT_F32_I32; 359 if (RetVT == MVT::i64) 360 return FPTOUINT_F32_I64; 361 if (RetVT == MVT::i128) 362 return FPTOUINT_F32_I128; 363 } else if (OpVT == MVT::f64) { 364 if (RetVT == MVT::i8) 365 return FPTOUINT_F64_I8; 366 if (RetVT == MVT::i16) 367 return FPTOUINT_F64_I16; 368 if (RetVT == MVT::i32) 369 return FPTOUINT_F64_I32; 370 if (RetVT == MVT::i64) 371 return FPTOUINT_F64_I64; 372 if (RetVT == MVT::i128) 373 return FPTOUINT_F64_I128; 374 } else if (OpVT == MVT::f80) { 375 if (RetVT == MVT::i32) 376 return FPTOUINT_F80_I32; 377 if (RetVT == MVT::i64) 378 return FPTOUINT_F80_I64; 379 if (RetVT == MVT::i128) 380 return FPTOUINT_F80_I128; 381 } else if (OpVT == MVT::ppcf128) { 382 if (RetVT == MVT::i32) 383 return FPTOUINT_PPCF128_I32; 384 if (RetVT == MVT::i64) 385 return FPTOUINT_PPCF128_I64; 386 if (RetVT == MVT::i128) 387 return FPTOUINT_PPCF128_I128; 388 } 389 return UNKNOWN_LIBCALL; 390} 391 392/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 393/// UNKNOWN_LIBCALL if there is none. 394RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 395 if (OpVT == MVT::i32) { 396 if (RetVT == MVT::f32) 397 return SINTTOFP_I32_F32; 398 else if (RetVT == MVT::f64) 399 return SINTTOFP_I32_F64; 400 else if (RetVT == MVT::f80) 401 return SINTTOFP_I32_F80; 402 else if (RetVT == MVT::ppcf128) 403 return SINTTOFP_I32_PPCF128; 404 } else if (OpVT == MVT::i64) { 405 if (RetVT == MVT::f32) 406 return SINTTOFP_I64_F32; 407 else if (RetVT == MVT::f64) 408 return SINTTOFP_I64_F64; 409 else if (RetVT == MVT::f80) 410 return SINTTOFP_I64_F80; 411 else if (RetVT == MVT::ppcf128) 412 return SINTTOFP_I64_PPCF128; 413 } else if (OpVT == MVT::i128) { 414 if (RetVT == MVT::f32) 415 return SINTTOFP_I128_F32; 416 else if (RetVT == MVT::f64) 417 return SINTTOFP_I128_F64; 418 else if (RetVT == MVT::f80) 419 return SINTTOFP_I128_F80; 420 else if (RetVT == MVT::ppcf128) 421 return SINTTOFP_I128_PPCF128; 422 } 423 return UNKNOWN_LIBCALL; 424} 425 426/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 427/// UNKNOWN_LIBCALL if there is none. 428RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 429 if (OpVT == MVT::i32) { 430 if (RetVT == MVT::f32) 431 return UINTTOFP_I32_F32; 432 else if (RetVT == MVT::f64) 433 return UINTTOFP_I32_F64; 434 else if (RetVT == MVT::f80) 435 return UINTTOFP_I32_F80; 436 else if (RetVT == MVT::ppcf128) 437 return UINTTOFP_I32_PPCF128; 438 } else if (OpVT == MVT::i64) { 439 if (RetVT == MVT::f32) 440 return UINTTOFP_I64_F32; 441 else if (RetVT == MVT::f64) 442 return UINTTOFP_I64_F64; 443 else if (RetVT == MVT::f80) 444 return UINTTOFP_I64_F80; 445 else if (RetVT == MVT::ppcf128) 446 return UINTTOFP_I64_PPCF128; 447 } else if (OpVT == MVT::i128) { 448 if (RetVT == MVT::f32) 449 return UINTTOFP_I128_F32; 450 else if (RetVT == MVT::f64) 451 return UINTTOFP_I128_F64; 452 else if (RetVT == MVT::f80) 453 return UINTTOFP_I128_F80; 454 else if (RetVT == MVT::ppcf128) 455 return UINTTOFP_I128_PPCF128; 456 } 457 return UNKNOWN_LIBCALL; 458} 459 460/// InitCmpLibcallCCs - Set default comparison libcall CC. 461/// 462static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 463 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 464 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 465 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 466 CCs[RTLIB::UNE_F32] = ISD::SETNE; 467 CCs[RTLIB::UNE_F64] = ISD::SETNE; 468 CCs[RTLIB::OGE_F32] = ISD::SETGE; 469 CCs[RTLIB::OGE_F64] = ISD::SETGE; 470 CCs[RTLIB::OLT_F32] = ISD::SETLT; 471 CCs[RTLIB::OLT_F64] = ISD::SETLT; 472 CCs[RTLIB::OLE_F32] = ISD::SETLE; 473 CCs[RTLIB::OLE_F64] = ISD::SETLE; 474 CCs[RTLIB::OGT_F32] = ISD::SETGT; 475 CCs[RTLIB::OGT_F64] = ISD::SETGT; 476 CCs[RTLIB::UO_F32] = ISD::SETNE; 477 CCs[RTLIB::UO_F64] = ISD::SETNE; 478 CCs[RTLIB::O_F32] = ISD::SETEQ; 479 CCs[RTLIB::O_F64] = ISD::SETEQ; 480} 481 482/// NOTE: The constructor takes ownership of TLOF. 483TargetLowering::TargetLowering(const TargetMachine &tm, 484 const TargetLoweringObjectFile *tlof) 485 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 486 // All operations default to being supported. 487 memset(OpActions, 0, sizeof(OpActions)); 488 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 489 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 490 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 491 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 492 493 // Set default actions for various operations. 494 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 495 // Default all indexed load / store to expand. 496 for (unsigned IM = (unsigned)ISD::PRE_INC; 497 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 498 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 499 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 500 } 501 502 // These operations default to expand. 503 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 504 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 505 } 506 507 // Most targets ignore the @llvm.prefetch intrinsic. 508 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 509 510 // ConstantFP nodes default to expand. Targets can either change this to 511 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 512 // to optimize expansions for certain constants. 513 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 514 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 515 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 516 517 // These library functions default to expand. 518 setOperationAction(ISD::FLOG , MVT::f64, Expand); 519 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 520 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 521 setOperationAction(ISD::FEXP , MVT::f64, Expand); 522 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 523 setOperationAction(ISD::FLOG , MVT::f32, Expand); 524 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 525 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 526 setOperationAction(ISD::FEXP , MVT::f32, Expand); 527 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 528 529 // Default ISD::TRAP to expand (which turns it into abort). 530 setOperationAction(ISD::TRAP, MVT::Other, Expand); 531 532 IsLittleEndian = TD->isLittleEndian(); 533 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 534 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 535 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 536 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 537 benefitFromCodePlacementOpt = false; 538 UseUnderscoreSetJmp = false; 539 UseUnderscoreLongJmp = false; 540 SelectIsExpensive = false; 541 IntDivIsCheap = false; 542 Pow2DivIsCheap = false; 543 StackPointerRegisterToSaveRestore = 0; 544 ExceptionPointerRegister = 0; 545 ExceptionSelectorRegister = 0; 546 BooleanContents = UndefinedBooleanContent; 547 SchedPreferenceInfo = SchedulingForLatency; 548 JumpBufSize = 0; 549 JumpBufAlignment = 0; 550 IfCvtBlockSizeLimit = 2; 551 IfCvtDupBlockSizeLimit = 0; 552 PrefLoopAlignment = 0; 553 554 InitLibcallNames(LibcallRoutineNames); 555 InitCmpLibcallCCs(CmpLibcallCCs); 556 InitLibcallCallingConvs(LibcallCallingConvs); 557} 558 559TargetLowering::~TargetLowering() { 560 delete &TLOF; 561} 562 563/// canOpTrap - Returns true if the operation can trap for the value type. 564/// VT must be a legal type. 565bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 566 assert(isTypeLegal(VT)); 567 switch (Op) { 568 default: 569 return false; 570 case ISD::FDIV: 571 case ISD::FREM: 572 case ISD::SDIV: 573 case ISD::UDIV: 574 case ISD::SREM: 575 case ISD::UREM: 576 return true; 577 } 578} 579 580 581static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 582 unsigned &NumIntermediates, 583 EVT &RegisterVT, 584 TargetLowering* TLI) { 585 // Figure out the right, legal destination reg to copy into. 586 unsigned NumElts = VT.getVectorNumElements(); 587 MVT EltTy = VT.getVectorElementType(); 588 589 unsigned NumVectorRegs = 1; 590 591 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 592 // could break down into LHS/RHS like LegalizeDAG does. 593 if (!isPowerOf2_32(NumElts)) { 594 NumVectorRegs = NumElts; 595 NumElts = 1; 596 } 597 598 // Divide the input until we get to a supported size. This will always 599 // end with a scalar if the target doesn't support vectors. 600 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 601 NumElts >>= 1; 602 NumVectorRegs <<= 1; 603 } 604 605 NumIntermediates = NumVectorRegs; 606 607 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 608 if (!TLI->isTypeLegal(NewVT)) 609 NewVT = EltTy; 610 IntermediateVT = NewVT; 611 612 EVT DestVT = TLI->getRegisterType(NewVT); 613 RegisterVT = DestVT; 614 if (EVT(DestVT).bitsLT(NewVT)) { 615 // Value is expanded, e.g. i64 -> i16. 616 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 617 } else { 618 // Otherwise, promotion or legal types use the same number of registers as 619 // the vector decimated to the appropriate level. 620 return NumVectorRegs; 621 } 622 623 return 1; 624} 625 626/// computeRegisterProperties - Once all of the register classes are added, 627/// this allows us to compute derived properties we expose. 628void TargetLowering::computeRegisterProperties() { 629 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 630 "Too many value types for ValueTypeActions to hold!"); 631 632 // Everything defaults to needing one register. 633 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 634 NumRegistersForVT[i] = 1; 635 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 636 } 637 // ...except isVoid, which doesn't need any registers. 638 NumRegistersForVT[MVT::isVoid] = 0; 639 640 // Find the largest integer register class. 641 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 642 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 643 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 644 645 // Every integer value type larger than this largest register takes twice as 646 // many registers to represent as the previous ValueType. 647 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 648 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 649 if (!ExpandedVT.isInteger()) 650 break; 651 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 652 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 653 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 654 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 655 } 656 657 // Inspect all of the ValueType's smaller than the largest integer 658 // register to see which ones need promotion. 659 unsigned LegalIntReg = LargestIntReg; 660 for (unsigned IntReg = LargestIntReg - 1; 661 IntReg >= (unsigned)MVT::i1; --IntReg) { 662 EVT IVT = (MVT::SimpleValueType)IntReg; 663 if (isTypeLegal(IVT)) { 664 LegalIntReg = IntReg; 665 } else { 666 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 667 (MVT::SimpleValueType)LegalIntReg; 668 ValueTypeActions.setTypeAction(IVT, Promote); 669 } 670 } 671 672 // ppcf128 type is really two f64's. 673 if (!isTypeLegal(MVT::ppcf128)) { 674 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 675 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 676 TransformToType[MVT::ppcf128] = MVT::f64; 677 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 678 } 679 680 // Decide how to handle f64. If the target does not have native f64 support, 681 // expand it to i64 and we will be generating soft float library calls. 682 if (!isTypeLegal(MVT::f64)) { 683 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 684 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 685 TransformToType[MVT::f64] = MVT::i64; 686 ValueTypeActions.setTypeAction(MVT::f64, Expand); 687 } 688 689 // Decide how to handle f32. If the target does not have native support for 690 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 691 if (!isTypeLegal(MVT::f32)) { 692 if (isTypeLegal(MVT::f64)) { 693 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 694 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 695 TransformToType[MVT::f32] = MVT::f64; 696 ValueTypeActions.setTypeAction(MVT::f32, Promote); 697 } else { 698 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 699 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 700 TransformToType[MVT::f32] = MVT::i32; 701 ValueTypeActions.setTypeAction(MVT::f32, Expand); 702 } 703 } 704 705 // Loop over all of the vector value types to see which need transformations. 706 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 707 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 708 MVT VT = (MVT::SimpleValueType)i; 709 if (!isTypeLegal(VT)) { 710 MVT IntermediateVT; 711 EVT RegisterVT; 712 unsigned NumIntermediates; 713 NumRegistersForVT[i] = 714 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 715 RegisterVT, this); 716 RegisterTypeForVT[i] = RegisterVT; 717 718 // Determine if there is a legal wider type. 719 bool IsLegalWiderType = false; 720 EVT EltVT = VT.getVectorElementType(); 721 unsigned NElts = VT.getVectorNumElements(); 722 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 723 EVT SVT = (MVT::SimpleValueType)nVT; 724 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 725 SVT.getVectorNumElements() > NElts && NElts != 1) { 726 TransformToType[i] = SVT; 727 ValueTypeActions.setTypeAction(VT, Promote); 728 IsLegalWiderType = true; 729 break; 730 } 731 } 732 if (!IsLegalWiderType) { 733 EVT NVT = VT.getPow2VectorType(); 734 if (NVT == VT) { 735 // Type is already a power of 2. The default action is to split. 736 TransformToType[i] = MVT::Other; 737 ValueTypeActions.setTypeAction(VT, Expand); 738 } else { 739 TransformToType[i] = NVT; 740 ValueTypeActions.setTypeAction(VT, Promote); 741 } 742 } 743 } 744 } 745} 746 747const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 748 return NULL; 749} 750 751 752MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 753 return PointerTy.SimpleTy; 754} 755 756MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 757 return MVT::i32; // return the default value 758} 759 760/// getVectorTypeBreakdown - Vector types are broken down into some number of 761/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 762/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 763/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 764/// 765/// This method returns the number of registers needed, and the VT for each 766/// register. It also returns the VT and quantity of the intermediate values 767/// before they are promoted/expanded. 768/// 769unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 770 EVT &IntermediateVT, 771 unsigned &NumIntermediates, 772 EVT &RegisterVT) const { 773 // Figure out the right, legal destination reg to copy into. 774 unsigned NumElts = VT.getVectorNumElements(); 775 EVT EltTy = VT.getVectorElementType(); 776 777 unsigned NumVectorRegs = 1; 778 779 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 780 // could break down into LHS/RHS like LegalizeDAG does. 781 if (!isPowerOf2_32(NumElts)) { 782 NumVectorRegs = NumElts; 783 NumElts = 1; 784 } 785 786 // Divide the input until we get to a supported size. This will always 787 // end with a scalar if the target doesn't support vectors. 788 while (NumElts > 1 && !isTypeLegal( 789 EVT::getVectorVT(Context, EltTy, NumElts))) { 790 NumElts >>= 1; 791 NumVectorRegs <<= 1; 792 } 793 794 NumIntermediates = NumVectorRegs; 795 796 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 797 if (!isTypeLegal(NewVT)) 798 NewVT = EltTy; 799 IntermediateVT = NewVT; 800 801 EVT DestVT = getRegisterType(Context, NewVT); 802 RegisterVT = DestVT; 803 if (DestVT.bitsLT(NewVT)) { 804 // Value is expanded, e.g. i64 -> i16. 805 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 806 } else { 807 // Otherwise, promotion or legal types use the same number of registers as 808 // the vector decimated to the appropriate level. 809 return NumVectorRegs; 810 } 811 812 return 1; 813} 814 815/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 816/// function arguments in the caller parameter area. This is the actual 817/// alignment, not its logarithm. 818unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 819 return TD->getCallFrameTypeAlignment(Ty); 820} 821 822/// getJumpTableEncoding - Return the entry encoding for a jump table in the 823/// current function. The returned value is a member of the 824/// MachineJumpTableInfo::JTEntryKind enum. 825unsigned TargetLowering::getJumpTableEncoding() const { 826 // In non-pic modes, just use the address of a block. 827 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 828 return MachineJumpTableInfo::EK_BlockAddress; 829 830 // In PIC mode, if the target supports a GPRel32 directive, use it. 831 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 832 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 833 834 // Otherwise, use a label difference. 835 return MachineJumpTableInfo::EK_LabelDifference32; 836} 837 838SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 839 SelectionDAG &DAG) const { 840 // If our PIC model is GP relative, use the global offset table as the base. 841 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 842 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 843 return Table; 844} 845 846/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 847/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 848/// MCExpr. 849const MCExpr * 850TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 851 unsigned JTI,MCContext &Ctx) const{ 852 // The normal PIC reloc base is the label at the start of the jump table. 853 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 854} 855 856bool 857TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 858 // Assume that everything is safe in static mode. 859 if (getTargetMachine().getRelocationModel() == Reloc::Static) 860 return true; 861 862 // In dynamic-no-pic mode, assume that known defined values are safe. 863 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 864 GA && 865 !GA->getGlobal()->isDeclaration() && 866 !GA->getGlobal()->isWeakForLinker()) 867 return true; 868 869 // Otherwise assume nothing is safe. 870 return false; 871} 872 873//===----------------------------------------------------------------------===// 874// Optimization Methods 875//===----------------------------------------------------------------------===// 876 877/// ShrinkDemandedConstant - Check to see if the specified operand of the 878/// specified instruction is a constant integer. If so, check to see if there 879/// are any bits set in the constant that are not demanded. If so, shrink the 880/// constant and return true. 881bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 882 const APInt &Demanded) { 883 DebugLoc dl = Op.getDebugLoc(); 884 885 // FIXME: ISD::SELECT, ISD::SELECT_CC 886 switch (Op.getOpcode()) { 887 default: break; 888 case ISD::XOR: 889 case ISD::AND: 890 case ISD::OR: { 891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 892 if (!C) return false; 893 894 if (Op.getOpcode() == ISD::XOR && 895 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 896 return false; 897 898 // if we can expand it to have all bits set, do it 899 if (C->getAPIntValue().intersects(~Demanded)) { 900 EVT VT = Op.getValueType(); 901 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 902 DAG.getConstant(Demanded & 903 C->getAPIntValue(), 904 VT)); 905 return CombineTo(Op, New); 906 } 907 908 break; 909 } 910 } 911 912 return false; 913} 914 915/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 916/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 917/// cast, but it could be generalized for targets with other types of 918/// implicit widening casts. 919bool 920TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 921 unsigned BitWidth, 922 const APInt &Demanded, 923 DebugLoc dl) { 924 assert(Op.getNumOperands() == 2 && 925 "ShrinkDemandedOp only supports binary operators!"); 926 assert(Op.getNode()->getNumValues() == 1 && 927 "ShrinkDemandedOp only supports nodes with one result!"); 928 929 // Don't do this if the node has another user, which may require the 930 // full value. 931 if (!Op.getNode()->hasOneUse()) 932 return false; 933 934 // Search for the smallest integer type with free casts to and from 935 // Op's type. For expedience, just check power-of-2 integer types. 936 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 937 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 938 if (!isPowerOf2_32(SmallVTBits)) 939 SmallVTBits = NextPowerOf2(SmallVTBits); 940 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 941 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 942 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 943 TLI.isZExtFree(SmallVT, Op.getValueType())) { 944 // We found a type with free casts. 945 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 946 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 947 Op.getNode()->getOperand(0)), 948 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 949 Op.getNode()->getOperand(1))); 950 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 951 return CombineTo(Op, Z); 952 } 953 } 954 return false; 955} 956 957/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 958/// DemandedMask bits of the result of Op are ever used downstream. If we can 959/// use this information to simplify Op, create a new simplified DAG node and 960/// return true, returning the original and new nodes in Old and New. Otherwise, 961/// analyze the expression and return a mask of KnownOne and KnownZero bits for 962/// the expression (used to simplify the caller). The KnownZero/One bits may 963/// only be accurate for those bits in the DemandedMask. 964bool TargetLowering::SimplifyDemandedBits(SDValue Op, 965 const APInt &DemandedMask, 966 APInt &KnownZero, 967 APInt &KnownOne, 968 TargetLoweringOpt &TLO, 969 unsigned Depth) const { 970 unsigned BitWidth = DemandedMask.getBitWidth(); 971 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 972 "Mask size mismatches value type size!"); 973 APInt NewMask = DemandedMask; 974 DebugLoc dl = Op.getDebugLoc(); 975 976 // Don't know anything. 977 KnownZero = KnownOne = APInt(BitWidth, 0); 978 979 // Other users may use these bits. 980 if (!Op.getNode()->hasOneUse()) { 981 if (Depth != 0) { 982 // If not at the root, Just compute the KnownZero/KnownOne bits to 983 // simplify things downstream. 984 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 985 return false; 986 } 987 // If this is the root being simplified, allow it to have multiple uses, 988 // just set the NewMask to all bits. 989 NewMask = APInt::getAllOnesValue(BitWidth); 990 } else if (DemandedMask == 0) { 991 // Not demanding any bits from Op. 992 if (Op.getOpcode() != ISD::UNDEF) 993 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 994 return false; 995 } else if (Depth == 6) { // Limit search depth. 996 return false; 997 } 998 999 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1000 switch (Op.getOpcode()) { 1001 case ISD::Constant: 1002 // We know all of the bits for a constant! 1003 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1004 KnownZero = ~KnownOne & NewMask; 1005 return false; // Don't fall through, will infinitely loop. 1006 case ISD::AND: 1007 // If the RHS is a constant, check to see if the LHS would be zero without 1008 // using the bits from the RHS. Below, we use knowledge about the RHS to 1009 // simplify the LHS, here we're using information from the LHS to simplify 1010 // the RHS. 1011 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1012 APInt LHSZero, LHSOne; 1013 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1014 LHSZero, LHSOne, Depth+1); 1015 // If the LHS already has zeros where RHSC does, this and is dead. 1016 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1017 return TLO.CombineTo(Op, Op.getOperand(0)); 1018 // If any of the set bits in the RHS are known zero on the LHS, shrink 1019 // the constant. 1020 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1021 return true; 1022 } 1023 1024 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1025 KnownOne, TLO, Depth+1)) 1026 return true; 1027 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1028 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1029 KnownZero2, KnownOne2, TLO, Depth+1)) 1030 return true; 1031 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1032 1033 // If all of the demanded bits are known one on one side, return the other. 1034 // These bits cannot contribute to the result of the 'and'. 1035 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1036 return TLO.CombineTo(Op, Op.getOperand(0)); 1037 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1038 return TLO.CombineTo(Op, Op.getOperand(1)); 1039 // If all of the demanded bits in the inputs are known zeros, return zero. 1040 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1041 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1042 // If the RHS is a constant, see if we can simplify it. 1043 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1044 return true; 1045 // If the operation can be done in a smaller type, do so. 1046 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1047 return true; 1048 1049 // Output known-1 bits are only known if set in both the LHS & RHS. 1050 KnownOne &= KnownOne2; 1051 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1052 KnownZero |= KnownZero2; 1053 break; 1054 case ISD::OR: 1055 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1056 KnownOne, TLO, Depth+1)) 1057 return true; 1058 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1059 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1060 KnownZero2, KnownOne2, TLO, Depth+1)) 1061 return true; 1062 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1063 1064 // If all of the demanded bits are known zero on one side, return the other. 1065 // These bits cannot contribute to the result of the 'or'. 1066 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1067 return TLO.CombineTo(Op, Op.getOperand(0)); 1068 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1069 return TLO.CombineTo(Op, Op.getOperand(1)); 1070 // If all of the potentially set bits on one side are known to be set on 1071 // the other side, just use the 'other' side. 1072 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1073 return TLO.CombineTo(Op, Op.getOperand(0)); 1074 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1075 return TLO.CombineTo(Op, Op.getOperand(1)); 1076 // If the RHS is a constant, see if we can simplify it. 1077 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1078 return true; 1079 // If the operation can be done in a smaller type, do so. 1080 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1081 return true; 1082 1083 // Output known-0 bits are only known if clear in both the LHS & RHS. 1084 KnownZero &= KnownZero2; 1085 // Output known-1 are known to be set if set in either the LHS | RHS. 1086 KnownOne |= KnownOne2; 1087 break; 1088 case ISD::XOR: 1089 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1090 KnownOne, TLO, Depth+1)) 1091 return true; 1092 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1093 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1094 KnownOne2, TLO, Depth+1)) 1095 return true; 1096 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1097 1098 // If all of the demanded bits are known zero on one side, return the other. 1099 // These bits cannot contribute to the result of the 'xor'. 1100 if ((KnownZero & NewMask) == NewMask) 1101 return TLO.CombineTo(Op, Op.getOperand(0)); 1102 if ((KnownZero2 & NewMask) == NewMask) 1103 return TLO.CombineTo(Op, Op.getOperand(1)); 1104 // If the operation can be done in a smaller type, do so. 1105 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1106 return true; 1107 1108 // If all of the unknown bits are known to be zero on one side or the other 1109 // (but not both) turn this into an *inclusive* or. 1110 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1111 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1112 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1113 Op.getOperand(0), 1114 Op.getOperand(1))); 1115 1116 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1117 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1118 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1119 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1120 1121 // If all of the demanded bits on one side are known, and all of the set 1122 // bits on that side are also known to be set on the other side, turn this 1123 // into an AND, as we know the bits will be cleared. 1124 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1125 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1126 if ((KnownOne & KnownOne2) == KnownOne) { 1127 EVT VT = Op.getValueType(); 1128 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1129 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1130 Op.getOperand(0), ANDC)); 1131 } 1132 } 1133 1134 // If the RHS is a constant, see if we can simplify it. 1135 // for XOR, we prefer to force bits to 1 if they will make a -1. 1136 // if we can't force bits, try to shrink constant 1137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1138 APInt Expanded = C->getAPIntValue() | (~NewMask); 1139 // if we can expand it to have all bits set, do it 1140 if (Expanded.isAllOnesValue()) { 1141 if (Expanded != C->getAPIntValue()) { 1142 EVT VT = Op.getValueType(); 1143 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1144 TLO.DAG.getConstant(Expanded, VT)); 1145 return TLO.CombineTo(Op, New); 1146 } 1147 // if it already has all the bits set, nothing to change 1148 // but don't shrink either! 1149 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1150 return true; 1151 } 1152 } 1153 1154 KnownZero = KnownZeroOut; 1155 KnownOne = KnownOneOut; 1156 break; 1157 case ISD::SELECT: 1158 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1159 KnownOne, TLO, Depth+1)) 1160 return true; 1161 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1162 KnownOne2, TLO, Depth+1)) 1163 return true; 1164 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1165 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1166 1167 // If the operands are constants, see if we can simplify them. 1168 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1169 return true; 1170 1171 // Only known if known in both the LHS and RHS. 1172 KnownOne &= KnownOne2; 1173 KnownZero &= KnownZero2; 1174 break; 1175 case ISD::SELECT_CC: 1176 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1177 KnownOne, TLO, Depth+1)) 1178 return true; 1179 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1180 KnownOne2, TLO, Depth+1)) 1181 return true; 1182 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1183 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1184 1185 // If the operands are constants, see if we can simplify them. 1186 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1187 return true; 1188 1189 // Only known if known in both the LHS and RHS. 1190 KnownOne &= KnownOne2; 1191 KnownZero &= KnownZero2; 1192 break; 1193 case ISD::SHL: 1194 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1195 unsigned ShAmt = SA->getZExtValue(); 1196 SDValue InOp = Op.getOperand(0); 1197 1198 // If the shift count is an invalid immediate, don't do anything. 1199 if (ShAmt >= BitWidth) 1200 break; 1201 1202 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1203 // single shift. We can do this if the bottom bits (which are shifted 1204 // out) are never demanded. 1205 if (InOp.getOpcode() == ISD::SRL && 1206 isa<ConstantSDNode>(InOp.getOperand(1))) { 1207 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1208 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1209 unsigned Opc = ISD::SHL; 1210 int Diff = ShAmt-C1; 1211 if (Diff < 0) { 1212 Diff = -Diff; 1213 Opc = ISD::SRL; 1214 } 1215 1216 SDValue NewSA = 1217 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1218 EVT VT = Op.getValueType(); 1219 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1220 InOp.getOperand(0), NewSA)); 1221 } 1222 } 1223 1224 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1225 KnownZero, KnownOne, TLO, Depth+1)) 1226 return true; 1227 KnownZero <<= SA->getZExtValue(); 1228 KnownOne <<= SA->getZExtValue(); 1229 // low bits known zero. 1230 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1231 } 1232 break; 1233 case ISD::SRL: 1234 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1235 EVT VT = Op.getValueType(); 1236 unsigned ShAmt = SA->getZExtValue(); 1237 unsigned VTSize = VT.getSizeInBits(); 1238 SDValue InOp = Op.getOperand(0); 1239 1240 // If the shift count is an invalid immediate, don't do anything. 1241 if (ShAmt >= BitWidth) 1242 break; 1243 1244 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1245 // single shift. We can do this if the top bits (which are shifted out) 1246 // are never demanded. 1247 if (InOp.getOpcode() == ISD::SHL && 1248 isa<ConstantSDNode>(InOp.getOperand(1))) { 1249 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1250 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1251 unsigned Opc = ISD::SRL; 1252 int Diff = ShAmt-C1; 1253 if (Diff < 0) { 1254 Diff = -Diff; 1255 Opc = ISD::SHL; 1256 } 1257 1258 SDValue NewSA = 1259 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1260 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1261 InOp.getOperand(0), NewSA)); 1262 } 1263 } 1264 1265 // Compute the new bits that are at the top now. 1266 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1267 KnownZero, KnownOne, TLO, Depth+1)) 1268 return true; 1269 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1270 KnownZero = KnownZero.lshr(ShAmt); 1271 KnownOne = KnownOne.lshr(ShAmt); 1272 1273 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1274 KnownZero |= HighBits; // High bits known zero. 1275 } 1276 break; 1277 case ISD::SRA: 1278 // If this is an arithmetic shift right and only the low-bit is set, we can 1279 // always convert this into a logical shr, even if the shift amount is 1280 // variable. The low bit of the shift cannot be an input sign bit unless 1281 // the shift amount is >= the size of the datatype, which is undefined. 1282 if (DemandedMask == 1) 1283 return TLO.CombineTo(Op, 1284 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1285 Op.getOperand(0), Op.getOperand(1))); 1286 1287 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1288 EVT VT = Op.getValueType(); 1289 unsigned ShAmt = SA->getZExtValue(); 1290 1291 // If the shift count is an invalid immediate, don't do anything. 1292 if (ShAmt >= BitWidth) 1293 break; 1294 1295 APInt InDemandedMask = (NewMask << ShAmt); 1296 1297 // If any of the demanded bits are produced by the sign extension, we also 1298 // demand the input sign bit. 1299 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1300 if (HighBits.intersects(NewMask)) 1301 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1302 1303 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1304 KnownZero, KnownOne, TLO, Depth+1)) 1305 return true; 1306 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1307 KnownZero = KnownZero.lshr(ShAmt); 1308 KnownOne = KnownOne.lshr(ShAmt); 1309 1310 // Handle the sign bit, adjusted to where it is now in the mask. 1311 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1312 1313 // If the input sign bit is known to be zero, or if none of the top bits 1314 // are demanded, turn this into an unsigned shift right. 1315 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1316 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1317 Op.getOperand(0), 1318 Op.getOperand(1))); 1319 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1320 KnownOne |= HighBits; 1321 } 1322 } 1323 break; 1324 case ISD::SIGN_EXTEND_INREG: { 1325 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1326 1327 // Sign extension. Compute the demanded bits in the result that are not 1328 // present in the input. 1329 APInt NewBits = 1330 APInt::getHighBitsSet(BitWidth, 1331 BitWidth - EVT.getScalarType().getSizeInBits()) & 1332 NewMask; 1333 1334 // If none of the extended bits are demanded, eliminate the sextinreg. 1335 if (NewBits == 0) 1336 return TLO.CombineTo(Op, Op.getOperand(0)); 1337 1338 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1339 InSignBit.zext(BitWidth); 1340 APInt InputDemandedBits = 1341 APInt::getLowBitsSet(BitWidth, 1342 EVT.getScalarType().getSizeInBits()) & 1343 NewMask; 1344 1345 // Since the sign extended bits are demanded, we know that the sign 1346 // bit is demanded. 1347 InputDemandedBits |= InSignBit; 1348 1349 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1350 KnownZero, KnownOne, TLO, Depth+1)) 1351 return true; 1352 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1353 1354 // If the sign bit of the input is known set or clear, then we know the 1355 // top bits of the result. 1356 1357 // If the input sign bit is known zero, convert this into a zero extension. 1358 if (KnownZero.intersects(InSignBit)) 1359 return TLO.CombineTo(Op, 1360 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1361 1362 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1363 KnownOne |= NewBits; 1364 KnownZero &= ~NewBits; 1365 } else { // Input sign bit unknown 1366 KnownZero &= ~NewBits; 1367 KnownOne &= ~NewBits; 1368 } 1369 break; 1370 } 1371 case ISD::ZERO_EXTEND: { 1372 unsigned OperandBitWidth = 1373 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1374 APInt InMask = NewMask; 1375 InMask.trunc(OperandBitWidth); 1376 1377 // If none of the top bits are demanded, convert this into an any_extend. 1378 APInt NewBits = 1379 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1380 if (!NewBits.intersects(NewMask)) 1381 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1382 Op.getValueType(), 1383 Op.getOperand(0))); 1384 1385 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1386 KnownZero, KnownOne, TLO, Depth+1)) 1387 return true; 1388 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1389 KnownZero.zext(BitWidth); 1390 KnownOne.zext(BitWidth); 1391 KnownZero |= NewBits; 1392 break; 1393 } 1394 case ISD::SIGN_EXTEND: { 1395 EVT InVT = Op.getOperand(0).getValueType(); 1396 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1397 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1398 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1399 APInt NewBits = ~InMask & NewMask; 1400 1401 // If none of the top bits are demanded, convert this into an any_extend. 1402 if (NewBits == 0) 1403 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1404 Op.getValueType(), 1405 Op.getOperand(0))); 1406 1407 // Since some of the sign extended bits are demanded, we know that the sign 1408 // bit is demanded. 1409 APInt InDemandedBits = InMask & NewMask; 1410 InDemandedBits |= InSignBit; 1411 InDemandedBits.trunc(InBits); 1412 1413 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1414 KnownOne, TLO, Depth+1)) 1415 return true; 1416 KnownZero.zext(BitWidth); 1417 KnownOne.zext(BitWidth); 1418 1419 // If the sign bit is known zero, convert this to a zero extend. 1420 if (KnownZero.intersects(InSignBit)) 1421 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1422 Op.getValueType(), 1423 Op.getOperand(0))); 1424 1425 // If the sign bit is known one, the top bits match. 1426 if (KnownOne.intersects(InSignBit)) { 1427 KnownOne |= NewBits; 1428 KnownZero &= ~NewBits; 1429 } else { // Otherwise, top bits aren't known. 1430 KnownOne &= ~NewBits; 1431 KnownZero &= ~NewBits; 1432 } 1433 break; 1434 } 1435 case ISD::ANY_EXTEND: { 1436 unsigned OperandBitWidth = 1437 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1438 APInt InMask = NewMask; 1439 InMask.trunc(OperandBitWidth); 1440 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1441 KnownZero, KnownOne, TLO, Depth+1)) 1442 return true; 1443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1444 KnownZero.zext(BitWidth); 1445 KnownOne.zext(BitWidth); 1446 break; 1447 } 1448 case ISD::TRUNCATE: { 1449 // Simplify the input, using demanded bit information, and compute the known 1450 // zero/one bits live out. 1451 unsigned OperandBitWidth = 1452 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1453 APInt TruncMask = NewMask; 1454 TruncMask.zext(OperandBitWidth); 1455 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1456 KnownZero, KnownOne, TLO, Depth+1)) 1457 return true; 1458 KnownZero.trunc(BitWidth); 1459 KnownOne.trunc(BitWidth); 1460 1461 // If the input is only used by this truncate, see if we can shrink it based 1462 // on the known demanded bits. 1463 if (Op.getOperand(0).getNode()->hasOneUse()) { 1464 SDValue In = Op.getOperand(0); 1465 switch (In.getOpcode()) { 1466 default: break; 1467 case ISD::SRL: 1468 // Shrink SRL by a constant if none of the high bits shifted in are 1469 // demanded. 1470 if (TLO.LegalTypes() && 1471 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1472 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1473 // undesirable. 1474 break; 1475 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1476 if (!ShAmt) 1477 break; 1478 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1479 OperandBitWidth - BitWidth); 1480 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1481 HighBits.trunc(BitWidth); 1482 1483 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1484 // None of the shifted in bits are needed. Add a truncate of the 1485 // shift input, then shift it. 1486 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1487 Op.getValueType(), 1488 In.getOperand(0)); 1489 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1490 Op.getValueType(), 1491 NewTrunc, 1492 In.getOperand(1))); 1493 } 1494 break; 1495 } 1496 } 1497 1498 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1499 break; 1500 } 1501 case ISD::AssertZext: { 1502 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1503 APInt InMask = APInt::getLowBitsSet(BitWidth, 1504 VT.getSizeInBits()); 1505 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1506 KnownZero, KnownOne, TLO, Depth+1)) 1507 return true; 1508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1509 KnownZero |= ~InMask & NewMask; 1510 break; 1511 } 1512 case ISD::BIT_CONVERT: 1513#if 0 1514 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1515 // is demanded, turn this into a FGETSIGN. 1516 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1517 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1518 !MVT::isVector(Op.getOperand(0).getValueType())) { 1519 // Only do this xform if FGETSIGN is valid or if before legalize. 1520 if (!TLO.AfterLegalize || 1521 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1522 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1523 // place. We expect the SHL to be eliminated by other optimizations. 1524 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1525 Op.getOperand(0)); 1526 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1527 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1528 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1529 Sign, ShAmt)); 1530 } 1531 } 1532#endif 1533 break; 1534 case ISD::ADD: 1535 case ISD::MUL: 1536 case ISD::SUB: { 1537 // Add, Sub, and Mul don't demand any bits in positions beyond that 1538 // of the highest bit demanded of them. 1539 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1540 BitWidth - NewMask.countLeadingZeros()); 1541 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1542 KnownOne2, TLO, Depth+1)) 1543 return true; 1544 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1545 KnownOne2, TLO, Depth+1)) 1546 return true; 1547 // See if the operation should be performed at a smaller bit width. 1548 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1549 return true; 1550 } 1551 // FALL THROUGH 1552 default: 1553 // Just use ComputeMaskedBits to compute output bits. 1554 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1555 break; 1556 } 1557 1558 // If we know the value of all of the demanded bits, return this as a 1559 // constant. 1560 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1561 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1562 1563 return false; 1564} 1565 1566/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1567/// in Mask are known to be either zero or one and return them in the 1568/// KnownZero/KnownOne bitsets. 1569void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1570 const APInt &Mask, 1571 APInt &KnownZero, 1572 APInt &KnownOne, 1573 const SelectionDAG &DAG, 1574 unsigned Depth) const { 1575 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1576 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1577 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1578 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1579 "Should use MaskedValueIsZero if you don't know whether Op" 1580 " is a target node!"); 1581 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1582} 1583 1584/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1585/// targets that want to expose additional information about sign bits to the 1586/// DAG Combiner. 1587unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1588 unsigned Depth) const { 1589 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1590 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1591 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1592 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1593 "Should use ComputeNumSignBits if you don't know whether Op" 1594 " is a target node!"); 1595 return 1; 1596} 1597 1598/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1599/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1600/// determine which bit is set. 1601/// 1602static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1603 // A left-shift of a constant one will have exactly one bit set, because 1604 // shifting the bit off the end is undefined. 1605 if (Val.getOpcode() == ISD::SHL) 1606 if (ConstantSDNode *C = 1607 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1608 if (C->getAPIntValue() == 1) 1609 return true; 1610 1611 // Similarly, a right-shift of a constant sign-bit will have exactly 1612 // one bit set. 1613 if (Val.getOpcode() == ISD::SRL) 1614 if (ConstantSDNode *C = 1615 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1616 if (C->getAPIntValue().isSignBit()) 1617 return true; 1618 1619 // More could be done here, though the above checks are enough 1620 // to handle some common cases. 1621 1622 // Fall back to ComputeMaskedBits to catch other known cases. 1623 EVT OpVT = Val.getValueType(); 1624 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1625 APInt Mask = APInt::getAllOnesValue(BitWidth); 1626 APInt KnownZero, KnownOne; 1627 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1628 return (KnownZero.countPopulation() == BitWidth - 1) && 1629 (KnownOne.countPopulation() == 1); 1630} 1631 1632/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1633/// and cc. If it is unable to simplify it, return a null SDValue. 1634SDValue 1635TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1636 ISD::CondCode Cond, bool foldBooleans, 1637 DAGCombinerInfo &DCI, DebugLoc dl) const { 1638 SelectionDAG &DAG = DCI.DAG; 1639 LLVMContext &Context = *DAG.getContext(); 1640 1641 // These setcc operations always fold. 1642 switch (Cond) { 1643 default: break; 1644 case ISD::SETFALSE: 1645 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1646 case ISD::SETTRUE: 1647 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1648 } 1649 1650 if (isa<ConstantSDNode>(N0.getNode())) { 1651 // Ensure that the constant occurs on the RHS, and fold constant 1652 // comparisons. 1653 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1654 } 1655 1656 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1657 const APInt &C1 = N1C->getAPIntValue(); 1658 1659 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1660 // equality comparison, then we're just comparing whether X itself is 1661 // zero. 1662 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1663 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1664 N0.getOperand(1).getOpcode() == ISD::Constant) { 1665 const APInt &ShAmt 1666 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1667 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1668 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1669 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1670 // (srl (ctlz x), 5) == 0 -> X != 0 1671 // (srl (ctlz x), 5) != 1 -> X != 0 1672 Cond = ISD::SETNE; 1673 } else { 1674 // (srl (ctlz x), 5) != 0 -> X == 0 1675 // (srl (ctlz x), 5) == 1 -> X == 0 1676 Cond = ISD::SETEQ; 1677 } 1678 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1679 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1680 Zero, Cond); 1681 } 1682 } 1683 1684 // If the LHS is '(and load, const)', the RHS is 0, 1685 // the test is for equality or unsigned, and all 1 bits of the const are 1686 // in the same partial word, see if we can shorten the load. 1687 if (DCI.isBeforeLegalize() && 1688 N0.getOpcode() == ISD::AND && C1 == 0 && 1689 N0.getNode()->hasOneUse() && 1690 isa<LoadSDNode>(N0.getOperand(0)) && 1691 N0.getOperand(0).getNode()->hasOneUse() && 1692 isa<ConstantSDNode>(N0.getOperand(1))) { 1693 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1694 APInt bestMask; 1695 unsigned bestWidth = 0, bestOffset = 0; 1696 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1697 unsigned origWidth = N0.getValueType().getSizeInBits(); 1698 unsigned maskWidth = origWidth; 1699 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1700 // 8 bits, but have to be careful... 1701 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1702 origWidth = Lod->getMemoryVT().getSizeInBits(); 1703 const APInt &Mask = 1704 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1705 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1706 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1707 for (unsigned offset=0; offset<origWidth/width; offset++) { 1708 if ((newMask & Mask) == Mask) { 1709 if (!TD->isLittleEndian()) 1710 bestOffset = (origWidth/width - offset - 1) * (width/8); 1711 else 1712 bestOffset = (uint64_t)offset * (width/8); 1713 bestMask = Mask.lshr(offset * (width/8) * 8); 1714 bestWidth = width; 1715 break; 1716 } 1717 newMask = newMask << width; 1718 } 1719 } 1720 } 1721 if (bestWidth) { 1722 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1723 if (newVT.isRound()) { 1724 EVT PtrType = Lod->getOperand(1).getValueType(); 1725 SDValue Ptr = Lod->getBasePtr(); 1726 if (bestOffset != 0) 1727 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1728 DAG.getConstant(bestOffset, PtrType)); 1729 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1730 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1731 Lod->getSrcValue(), 1732 Lod->getSrcValueOffset() + bestOffset, 1733 false, false, NewAlign); 1734 return DAG.getSetCC(dl, VT, 1735 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1736 DAG.getConstant(bestMask.trunc(bestWidth), 1737 newVT)), 1738 DAG.getConstant(0LL, newVT), Cond); 1739 } 1740 } 1741 } 1742 1743 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1744 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1745 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1746 1747 // If the comparison constant has bits in the upper part, the 1748 // zero-extended value could never match. 1749 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1750 C1.getBitWidth() - InSize))) { 1751 switch (Cond) { 1752 case ISD::SETUGT: 1753 case ISD::SETUGE: 1754 case ISD::SETEQ: return DAG.getConstant(0, VT); 1755 case ISD::SETULT: 1756 case ISD::SETULE: 1757 case ISD::SETNE: return DAG.getConstant(1, VT); 1758 case ISD::SETGT: 1759 case ISD::SETGE: 1760 // True if the sign bit of C1 is set. 1761 return DAG.getConstant(C1.isNegative(), VT); 1762 case ISD::SETLT: 1763 case ISD::SETLE: 1764 // True if the sign bit of C1 isn't set. 1765 return DAG.getConstant(C1.isNonNegative(), VT); 1766 default: 1767 break; 1768 } 1769 } 1770 1771 // Otherwise, we can perform the comparison with the low bits. 1772 switch (Cond) { 1773 case ISD::SETEQ: 1774 case ISD::SETNE: 1775 case ISD::SETUGT: 1776 case ISD::SETUGE: 1777 case ISD::SETULT: 1778 case ISD::SETULE: { 1779 EVT newVT = N0.getOperand(0).getValueType(); 1780 if (DCI.isBeforeLegalizeOps() || 1781 (isOperationLegal(ISD::SETCC, newVT) && 1782 getCondCodeAction(Cond, newVT)==Legal)) 1783 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1784 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1785 Cond); 1786 break; 1787 } 1788 default: 1789 break; // todo, be more careful with signed comparisons 1790 } 1791 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1792 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1793 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1794 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1795 EVT ExtDstTy = N0.getValueType(); 1796 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1797 1798 // If the extended part has any inconsistent bits, it cannot ever 1799 // compare equal. In other words, they have to be all ones or all 1800 // zeros. 1801 APInt ExtBits = 1802 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1803 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1804 return DAG.getConstant(Cond == ISD::SETNE, VT); 1805 1806 SDValue ZextOp; 1807 EVT Op0Ty = N0.getOperand(0).getValueType(); 1808 if (Op0Ty == ExtSrcTy) { 1809 ZextOp = N0.getOperand(0); 1810 } else { 1811 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1812 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1813 DAG.getConstant(Imm, Op0Ty)); 1814 } 1815 if (!DCI.isCalledByLegalizer()) 1816 DCI.AddToWorklist(ZextOp.getNode()); 1817 // Otherwise, make this a use of a zext. 1818 return DAG.getSetCC(dl, VT, ZextOp, 1819 DAG.getConstant(C1 & APInt::getLowBitsSet( 1820 ExtDstTyBits, 1821 ExtSrcTyBits), 1822 ExtDstTy), 1823 Cond); 1824 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1825 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1826 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1827 if (N0.getOpcode() == ISD::SETCC && 1828 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1829 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1830 if (TrueWhenTrue) 1831 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1832 // Invert the condition. 1833 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1834 CC = ISD::getSetCCInverse(CC, 1835 N0.getOperand(0).getValueType().isInteger()); 1836 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1837 } 1838 1839 if ((N0.getOpcode() == ISD::XOR || 1840 (N0.getOpcode() == ISD::AND && 1841 N0.getOperand(0).getOpcode() == ISD::XOR && 1842 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1843 isa<ConstantSDNode>(N0.getOperand(1)) && 1844 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1845 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1846 // can only do this if the top bits are known zero. 1847 unsigned BitWidth = N0.getValueSizeInBits(); 1848 if (DAG.MaskedValueIsZero(N0, 1849 APInt::getHighBitsSet(BitWidth, 1850 BitWidth-1))) { 1851 // Okay, get the un-inverted input value. 1852 SDValue Val; 1853 if (N0.getOpcode() == ISD::XOR) 1854 Val = N0.getOperand(0); 1855 else { 1856 assert(N0.getOpcode() == ISD::AND && 1857 N0.getOperand(0).getOpcode() == ISD::XOR); 1858 // ((X^1)&1)^1 -> X & 1 1859 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1860 N0.getOperand(0).getOperand(0), 1861 N0.getOperand(1)); 1862 } 1863 1864 return DAG.getSetCC(dl, VT, Val, N1, 1865 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1866 } 1867 } else if (N1C->getAPIntValue() == 1 && 1868 (VT == MVT::i1 || 1869 getBooleanContents() == ZeroOrOneBooleanContent)) { 1870 SDValue Op0 = N0; 1871 if (Op0.getOpcode() == ISD::TRUNCATE) 1872 Op0 = Op0.getOperand(0); 1873 1874 if ((Op0.getOpcode() == ISD::XOR) && 1875 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1876 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1877 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1878 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1879 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1880 Cond); 1881 } else if (Op0.getOpcode() == ISD::AND && 1882 isa<ConstantSDNode>(Op0.getOperand(1)) && 1883 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1884 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1885 if (Op0.getValueType().bitsGT(VT)) 1886 Op0 = DAG.getNode(ISD::AND, dl, VT, 1887 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1888 DAG.getConstant(1, VT)); 1889 else if (Op0.getValueType().bitsLT(VT)) 1890 Op0 = DAG.getNode(ISD::AND, dl, VT, 1891 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1892 DAG.getConstant(1, VT)); 1893 1894 return DAG.getSetCC(dl, VT, Op0, 1895 DAG.getConstant(0, Op0.getValueType()), 1896 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1897 } 1898 } 1899 } 1900 1901 APInt MinVal, MaxVal; 1902 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1903 if (ISD::isSignedIntSetCC(Cond)) { 1904 MinVal = APInt::getSignedMinValue(OperandBitSize); 1905 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1906 } else { 1907 MinVal = APInt::getMinValue(OperandBitSize); 1908 MaxVal = APInt::getMaxValue(OperandBitSize); 1909 } 1910 1911 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1912 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1913 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1914 // X >= C0 --> X > (C0-1) 1915 return DAG.getSetCC(dl, VT, N0, 1916 DAG.getConstant(C1-1, N1.getValueType()), 1917 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1918 } 1919 1920 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1921 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1922 // X <= C0 --> X < (C0+1) 1923 return DAG.getSetCC(dl, VT, N0, 1924 DAG.getConstant(C1+1, N1.getValueType()), 1925 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1926 } 1927 1928 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1929 return DAG.getConstant(0, VT); // X < MIN --> false 1930 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1931 return DAG.getConstant(1, VT); // X >= MIN --> true 1932 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1933 return DAG.getConstant(0, VT); // X > MAX --> false 1934 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1935 return DAG.getConstant(1, VT); // X <= MAX --> true 1936 1937 // Canonicalize setgt X, Min --> setne X, Min 1938 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1939 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1940 // Canonicalize setlt X, Max --> setne X, Max 1941 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1942 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1943 1944 // If we have setult X, 1, turn it into seteq X, 0 1945 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1946 return DAG.getSetCC(dl, VT, N0, 1947 DAG.getConstant(MinVal, N0.getValueType()), 1948 ISD::SETEQ); 1949 // If we have setugt X, Max-1, turn it into seteq X, Max 1950 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1951 return DAG.getSetCC(dl, VT, N0, 1952 DAG.getConstant(MaxVal, N0.getValueType()), 1953 ISD::SETEQ); 1954 1955 // If we have "setcc X, C0", check to see if we can shrink the immediate 1956 // by changing cc. 1957 1958 // SETUGT X, SINTMAX -> SETLT X, 0 1959 if (Cond == ISD::SETUGT && 1960 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1961 return DAG.getSetCC(dl, VT, N0, 1962 DAG.getConstant(0, N1.getValueType()), 1963 ISD::SETLT); 1964 1965 // SETULT X, SINTMIN -> SETGT X, -1 1966 if (Cond == ISD::SETULT && 1967 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1968 SDValue ConstMinusOne = 1969 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1970 N1.getValueType()); 1971 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1972 } 1973 1974 // Fold bit comparisons when we can. 1975 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1976 (VT == N0.getValueType() || 1977 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1978 N0.getOpcode() == ISD::AND) 1979 if (ConstantSDNode *AndRHS = 1980 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1981 EVT ShiftTy = DCI.isBeforeLegalize() ? 1982 getPointerTy() : getShiftAmountTy(); 1983 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1984 // Perform the xform if the AND RHS is a single bit. 1985 if (AndRHS->getAPIntValue().isPowerOf2()) { 1986 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1987 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1988 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1989 } 1990 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1991 // (X & 8) == 8 --> (X & 8) >> 3 1992 // Perform the xform if C1 is a single bit. 1993 if (C1.isPowerOf2()) { 1994 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1995 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1996 DAG.getConstant(C1.logBase2(), ShiftTy))); 1997 } 1998 } 1999 } 2000 } 2001 2002 if (isa<ConstantFPSDNode>(N0.getNode())) { 2003 // Constant fold or commute setcc. 2004 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2005 if (O.getNode()) return O; 2006 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2007 // If the RHS of an FP comparison is a constant, simplify it away in 2008 // some cases. 2009 if (CFP->getValueAPF().isNaN()) { 2010 // If an operand is known to be a nan, we can fold it. 2011 switch (ISD::getUnorderedFlavor(Cond)) { 2012 default: llvm_unreachable("Unknown flavor!"); 2013 case 0: // Known false. 2014 return DAG.getConstant(0, VT); 2015 case 1: // Known true. 2016 return DAG.getConstant(1, VT); 2017 case 2: // Undefined. 2018 return DAG.getUNDEF(VT); 2019 } 2020 } 2021 2022 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2023 // constant if knowing that the operand is non-nan is enough. We prefer to 2024 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2025 // materialize 0.0. 2026 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2027 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2028 2029 // If the condition is not legal, see if we can find an equivalent one 2030 // which is legal. 2031 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2032 // If the comparison was an awkward floating-point == or != and one of 2033 // the comparison operands is infinity or negative infinity, convert the 2034 // condition to a less-awkward <= or >=. 2035 if (CFP->getValueAPF().isInfinity()) { 2036 if (CFP->getValueAPF().isNegative()) { 2037 if (Cond == ISD::SETOEQ && 2038 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2039 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2040 if (Cond == ISD::SETUEQ && 2041 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2042 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2043 if (Cond == ISD::SETUNE && 2044 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2045 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2046 if (Cond == ISD::SETONE && 2047 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2048 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2049 } else { 2050 if (Cond == ISD::SETOEQ && 2051 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2052 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2053 if (Cond == ISD::SETUEQ && 2054 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2055 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2056 if (Cond == ISD::SETUNE && 2057 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2058 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2059 if (Cond == ISD::SETONE && 2060 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2061 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2062 } 2063 } 2064 } 2065 } 2066 2067 if (N0 == N1) { 2068 // We can always fold X == X for integer setcc's. 2069 if (N0.getValueType().isInteger()) 2070 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2071 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2072 if (UOF == 2) // FP operators that are undefined on NaNs. 2073 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2074 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2075 return DAG.getConstant(UOF, VT); 2076 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2077 // if it is not already. 2078 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2079 if (NewCond != Cond) 2080 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2081 } 2082 2083 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2084 N0.getValueType().isInteger()) { 2085 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2086 N0.getOpcode() == ISD::XOR) { 2087 // Simplify (X+Y) == (X+Z) --> Y == Z 2088 if (N0.getOpcode() == N1.getOpcode()) { 2089 if (N0.getOperand(0) == N1.getOperand(0)) 2090 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2091 if (N0.getOperand(1) == N1.getOperand(1)) 2092 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2093 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2094 // If X op Y == Y op X, try other combinations. 2095 if (N0.getOperand(0) == N1.getOperand(1)) 2096 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2097 Cond); 2098 if (N0.getOperand(1) == N1.getOperand(0)) 2099 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2100 Cond); 2101 } 2102 } 2103 2104 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2105 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2106 // Turn (X+C1) == C2 --> X == C2-C1 2107 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2108 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2109 DAG.getConstant(RHSC->getAPIntValue()- 2110 LHSR->getAPIntValue(), 2111 N0.getValueType()), Cond); 2112 } 2113 2114 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2115 if (N0.getOpcode() == ISD::XOR) 2116 // If we know that all of the inverted bits are zero, don't bother 2117 // performing the inversion. 2118 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2119 return 2120 DAG.getSetCC(dl, VT, N0.getOperand(0), 2121 DAG.getConstant(LHSR->getAPIntValue() ^ 2122 RHSC->getAPIntValue(), 2123 N0.getValueType()), 2124 Cond); 2125 } 2126 2127 // Turn (C1-X) == C2 --> X == C1-C2 2128 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2129 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2130 return 2131 DAG.getSetCC(dl, VT, N0.getOperand(1), 2132 DAG.getConstant(SUBC->getAPIntValue() - 2133 RHSC->getAPIntValue(), 2134 N0.getValueType()), 2135 Cond); 2136 } 2137 } 2138 } 2139 2140 // Simplify (X+Z) == X --> Z == 0 2141 if (N0.getOperand(0) == N1) 2142 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2143 DAG.getConstant(0, N0.getValueType()), Cond); 2144 if (N0.getOperand(1) == N1) { 2145 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2146 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2147 DAG.getConstant(0, N0.getValueType()), Cond); 2148 else if (N0.getNode()->hasOneUse()) { 2149 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2150 // (Z-X) == X --> Z == X<<1 2151 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2152 N1, 2153 DAG.getConstant(1, getShiftAmountTy())); 2154 if (!DCI.isCalledByLegalizer()) 2155 DCI.AddToWorklist(SH.getNode()); 2156 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2157 } 2158 } 2159 } 2160 2161 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2162 N1.getOpcode() == ISD::XOR) { 2163 // Simplify X == (X+Z) --> Z == 0 2164 if (N1.getOperand(0) == N0) { 2165 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2166 DAG.getConstant(0, N1.getValueType()), Cond); 2167 } else if (N1.getOperand(1) == N0) { 2168 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2169 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2170 DAG.getConstant(0, N1.getValueType()), Cond); 2171 } else if (N1.getNode()->hasOneUse()) { 2172 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2173 // X == (Z-X) --> X<<1 == Z 2174 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2175 DAG.getConstant(1, getShiftAmountTy())); 2176 if (!DCI.isCalledByLegalizer()) 2177 DCI.AddToWorklist(SH.getNode()); 2178 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2179 } 2180 } 2181 } 2182 2183 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2184 // Note that where y is variable and is known to have at most 2185 // one bit set (for example, if it is z&1) we cannot do this; 2186 // the expressions are not equivalent when y==0. 2187 if (N0.getOpcode() == ISD::AND) 2188 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2189 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2190 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2191 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2192 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2193 } 2194 } 2195 if (N1.getOpcode() == ISD::AND) 2196 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2197 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2198 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2199 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2200 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2201 } 2202 } 2203 } 2204 2205 // Fold away ALL boolean setcc's. 2206 SDValue Temp; 2207 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2208 switch (Cond) { 2209 default: llvm_unreachable("Unknown integer setcc!"); 2210 case ISD::SETEQ: // X == Y -> ~(X^Y) 2211 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2212 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2213 if (!DCI.isCalledByLegalizer()) 2214 DCI.AddToWorklist(Temp.getNode()); 2215 break; 2216 case ISD::SETNE: // X != Y --> (X^Y) 2217 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2218 break; 2219 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2220 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2221 Temp = DAG.getNOT(dl, N0, MVT::i1); 2222 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2223 if (!DCI.isCalledByLegalizer()) 2224 DCI.AddToWorklist(Temp.getNode()); 2225 break; 2226 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2227 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2228 Temp = DAG.getNOT(dl, N1, MVT::i1); 2229 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2230 if (!DCI.isCalledByLegalizer()) 2231 DCI.AddToWorklist(Temp.getNode()); 2232 break; 2233 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2234 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2235 Temp = DAG.getNOT(dl, N0, MVT::i1); 2236 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2237 if (!DCI.isCalledByLegalizer()) 2238 DCI.AddToWorklist(Temp.getNode()); 2239 break; 2240 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2241 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2242 Temp = DAG.getNOT(dl, N1, MVT::i1); 2243 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2244 break; 2245 } 2246 if (VT != MVT::i1) { 2247 if (!DCI.isCalledByLegalizer()) 2248 DCI.AddToWorklist(N0.getNode()); 2249 // FIXME: If running after legalize, we probably can't do this. 2250 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2251 } 2252 return N0; 2253 } 2254 2255 // Could not fold it. 2256 return SDValue(); 2257} 2258 2259/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2260/// node is a GlobalAddress + offset. 2261bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2262 int64_t &Offset) const { 2263 if (isa<GlobalAddressSDNode>(N)) { 2264 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2265 GA = GASD->getGlobal(); 2266 Offset += GASD->getOffset(); 2267 return true; 2268 } 2269 2270 if (N->getOpcode() == ISD::ADD) { 2271 SDValue N1 = N->getOperand(0); 2272 SDValue N2 = N->getOperand(1); 2273 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2274 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2275 if (V) { 2276 Offset += V->getSExtValue(); 2277 return true; 2278 } 2279 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2280 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2281 if (V) { 2282 Offset += V->getSExtValue(); 2283 return true; 2284 } 2285 } 2286 } 2287 return false; 2288} 2289 2290 2291SDValue TargetLowering:: 2292PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2293 // Default implementation: no optimization. 2294 return SDValue(); 2295} 2296 2297//===----------------------------------------------------------------------===// 2298// Inline Assembler Implementation Methods 2299//===----------------------------------------------------------------------===// 2300 2301 2302TargetLowering::ConstraintType 2303TargetLowering::getConstraintType(const std::string &Constraint) const { 2304 // FIXME: lots more standard ones to handle. 2305 if (Constraint.size() == 1) { 2306 switch (Constraint[0]) { 2307 default: break; 2308 case 'r': return C_RegisterClass; 2309 case 'm': // memory 2310 case 'o': // offsetable 2311 case 'V': // not offsetable 2312 return C_Memory; 2313 case 'i': // Simple Integer or Relocatable Constant 2314 case 'n': // Simple Integer 2315 case 's': // Relocatable Constant 2316 case 'X': // Allow ANY value. 2317 case 'I': // Target registers. 2318 case 'J': 2319 case 'K': 2320 case 'L': 2321 case 'M': 2322 case 'N': 2323 case 'O': 2324 case 'P': 2325 return C_Other; 2326 } 2327 } 2328 2329 if (Constraint.size() > 1 && Constraint[0] == '{' && 2330 Constraint[Constraint.size()-1] == '}') 2331 return C_Register; 2332 return C_Unknown; 2333} 2334 2335/// LowerXConstraint - try to replace an X constraint, which matches anything, 2336/// with another that has more specific requirements based on the type of the 2337/// corresponding operand. 2338const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2339 if (ConstraintVT.isInteger()) 2340 return "r"; 2341 if (ConstraintVT.isFloatingPoint()) 2342 return "f"; // works for many targets 2343 return 0; 2344} 2345 2346/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2347/// vector. If it is invalid, don't add anything to Ops. 2348void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2349 char ConstraintLetter, 2350 bool hasMemory, 2351 std::vector<SDValue> &Ops, 2352 SelectionDAG &DAG) const { 2353 switch (ConstraintLetter) { 2354 default: break; 2355 case 'X': // Allows any operand; labels (basic block) use this. 2356 if (Op.getOpcode() == ISD::BasicBlock) { 2357 Ops.push_back(Op); 2358 return; 2359 } 2360 // fall through 2361 case 'i': // Simple Integer or Relocatable Constant 2362 case 'n': // Simple Integer 2363 case 's': { // Relocatable Constant 2364 // These operands are interested in values of the form (GV+C), where C may 2365 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2366 // is possible and fine if either GV or C are missing. 2367 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2368 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2369 2370 // If we have "(add GV, C)", pull out GV/C 2371 if (Op.getOpcode() == ISD::ADD) { 2372 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2373 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2374 if (C == 0 || GA == 0) { 2375 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2376 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2377 } 2378 if (C == 0 || GA == 0) 2379 C = 0, GA = 0; 2380 } 2381 2382 // If we find a valid operand, map to the TargetXXX version so that the 2383 // value itself doesn't get selected. 2384 if (GA) { // Either &GV or &GV+C 2385 if (ConstraintLetter != 'n') { 2386 int64_t Offs = GA->getOffset(); 2387 if (C) Offs += C->getZExtValue(); 2388 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2389 Op.getValueType(), Offs)); 2390 return; 2391 } 2392 } 2393 if (C) { // just C, no GV. 2394 // Simple constants are not allowed for 's'. 2395 if (ConstraintLetter != 's') { 2396 // gcc prints these as sign extended. Sign extend value to 64 bits 2397 // now; without this it would get ZExt'd later in 2398 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2399 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2400 MVT::i64)); 2401 return; 2402 } 2403 } 2404 break; 2405 } 2406 } 2407} 2408 2409std::vector<unsigned> TargetLowering:: 2410getRegClassForInlineAsmConstraint(const std::string &Constraint, 2411 EVT VT) const { 2412 return std::vector<unsigned>(); 2413} 2414 2415 2416std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2417getRegForInlineAsmConstraint(const std::string &Constraint, 2418 EVT VT) const { 2419 if (Constraint[0] != '{') 2420 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2421 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2422 2423 // Remove the braces from around the name. 2424 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2425 2426 // Figure out which register class contains this reg. 2427 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2428 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2429 E = RI->regclass_end(); RCI != E; ++RCI) { 2430 const TargetRegisterClass *RC = *RCI; 2431 2432 // If none of the value types for this register class are valid, we 2433 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2434 bool isLegal = false; 2435 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2436 I != E; ++I) { 2437 if (isTypeLegal(*I)) { 2438 isLegal = true; 2439 break; 2440 } 2441 } 2442 2443 if (!isLegal) continue; 2444 2445 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2446 I != E; ++I) { 2447 if (RegName.equals_lower(RI->getName(*I))) 2448 return std::make_pair(*I, RC); 2449 } 2450 } 2451 2452 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2453} 2454 2455//===----------------------------------------------------------------------===// 2456// Constraint Selection. 2457 2458/// isMatchingInputConstraint - Return true of this is an input operand that is 2459/// a matching constraint like "4". 2460bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2461 assert(!ConstraintCode.empty() && "No known constraint!"); 2462 return isdigit(ConstraintCode[0]); 2463} 2464 2465/// getMatchedOperand - If this is an input matching constraint, this method 2466/// returns the output operand it matches. 2467unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2468 assert(!ConstraintCode.empty() && "No known constraint!"); 2469 return atoi(ConstraintCode.c_str()); 2470} 2471 2472 2473/// getConstraintGenerality - Return an integer indicating how general CT 2474/// is. 2475static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2476 switch (CT) { 2477 default: llvm_unreachable("Unknown constraint type!"); 2478 case TargetLowering::C_Other: 2479 case TargetLowering::C_Unknown: 2480 return 0; 2481 case TargetLowering::C_Register: 2482 return 1; 2483 case TargetLowering::C_RegisterClass: 2484 return 2; 2485 case TargetLowering::C_Memory: 2486 return 3; 2487 } 2488} 2489 2490/// ChooseConstraint - If there are multiple different constraints that we 2491/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2492/// This is somewhat tricky: constraints fall into four classes: 2493/// Other -> immediates and magic values 2494/// Register -> one specific register 2495/// RegisterClass -> a group of regs 2496/// Memory -> memory 2497/// Ideally, we would pick the most specific constraint possible: if we have 2498/// something that fits into a register, we would pick it. The problem here 2499/// is that if we have something that could either be in a register or in 2500/// memory that use of the register could cause selection of *other* 2501/// operands to fail: they might only succeed if we pick memory. Because of 2502/// this the heuristic we use is: 2503/// 2504/// 1) If there is an 'other' constraint, and if the operand is valid for 2505/// that constraint, use it. This makes us take advantage of 'i' 2506/// constraints when available. 2507/// 2) Otherwise, pick the most general constraint present. This prefers 2508/// 'm' over 'r', for example. 2509/// 2510static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2511 bool hasMemory, const TargetLowering &TLI, 2512 SDValue Op, SelectionDAG *DAG) { 2513 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2514 unsigned BestIdx = 0; 2515 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2516 int BestGenerality = -1; 2517 2518 // Loop over the options, keeping track of the most general one. 2519 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2520 TargetLowering::ConstraintType CType = 2521 TLI.getConstraintType(OpInfo.Codes[i]); 2522 2523 // If this is an 'other' constraint, see if the operand is valid for it. 2524 // For example, on X86 we might have an 'rI' constraint. If the operand 2525 // is an integer in the range [0..31] we want to use I (saving a load 2526 // of a register), otherwise we must use 'r'. 2527 if (CType == TargetLowering::C_Other && Op.getNode()) { 2528 assert(OpInfo.Codes[i].size() == 1 && 2529 "Unhandled multi-letter 'other' constraint"); 2530 std::vector<SDValue> ResultOps; 2531 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2532 ResultOps, *DAG); 2533 if (!ResultOps.empty()) { 2534 BestType = CType; 2535 BestIdx = i; 2536 break; 2537 } 2538 } 2539 2540 // This constraint letter is more general than the previous one, use it. 2541 int Generality = getConstraintGenerality(CType); 2542 if (Generality > BestGenerality) { 2543 BestType = CType; 2544 BestIdx = i; 2545 BestGenerality = Generality; 2546 } 2547 } 2548 2549 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2550 OpInfo.ConstraintType = BestType; 2551} 2552 2553/// ComputeConstraintToUse - Determines the constraint code and constraint 2554/// type to use for the specific AsmOperandInfo, setting 2555/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2556void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2557 SDValue Op, 2558 bool hasMemory, 2559 SelectionDAG *DAG) const { 2560 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2561 2562 // Single-letter constraints ('r') are very common. 2563 if (OpInfo.Codes.size() == 1) { 2564 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2565 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2566 } else { 2567 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2568 } 2569 2570 // 'X' matches anything. 2571 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2572 // Labels and constants are handled elsewhere ('X' is the only thing 2573 // that matches labels). For Functions, the type here is the type of 2574 // the result, which is not what we want to look at; leave them alone. 2575 Value *v = OpInfo.CallOperandVal; 2576 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2577 OpInfo.CallOperandVal = v; 2578 return; 2579 } 2580 2581 // Otherwise, try to resolve it to something we know about by looking at 2582 // the actual operand type. 2583 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2584 OpInfo.ConstraintCode = Repl; 2585 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2586 } 2587 } 2588} 2589 2590//===----------------------------------------------------------------------===// 2591// Loop Strength Reduction hooks 2592//===----------------------------------------------------------------------===// 2593 2594/// isLegalAddressingMode - Return true if the addressing mode represented 2595/// by AM is legal for this target, for a load/store of the specified type. 2596bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2597 const Type *Ty) const { 2598 // The default implementation of this implements a conservative RISCy, r+r and 2599 // r+i addr mode. 2600 2601 // Allows a sign-extended 16-bit immediate field. 2602 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2603 return false; 2604 2605 // No global is ever allowed as a base. 2606 if (AM.BaseGV) 2607 return false; 2608 2609 // Only support r+r, 2610 switch (AM.Scale) { 2611 case 0: // "r+i" or just "i", depending on HasBaseReg. 2612 break; 2613 case 1: 2614 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2615 return false; 2616 // Otherwise we have r+r or r+i. 2617 break; 2618 case 2: 2619 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2620 return false; 2621 // Allow 2*r as r+r. 2622 break; 2623 } 2624 2625 return true; 2626} 2627 2628/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2629/// return a DAG expression to select that will generate the same value by 2630/// multiplying by a magic number. See: 2631/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2632SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2633 std::vector<SDNode*>* Created) const { 2634 EVT VT = N->getValueType(0); 2635 DebugLoc dl= N->getDebugLoc(); 2636 2637 // Check to see if we can do this. 2638 // FIXME: We should be more aggressive here. 2639 if (!isTypeLegal(VT)) 2640 return SDValue(); 2641 2642 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2643 APInt::ms magics = d.magic(); 2644 2645 // Multiply the numerator (operand 0) by the magic value 2646 // FIXME: We should support doing a MUL in a wider type 2647 SDValue Q; 2648 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2649 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2650 DAG.getConstant(magics.m, VT)); 2651 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2652 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2653 N->getOperand(0), 2654 DAG.getConstant(magics.m, VT)).getNode(), 1); 2655 else 2656 return SDValue(); // No mulhs or equvialent 2657 // If d > 0 and m < 0, add the numerator 2658 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2659 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2660 if (Created) 2661 Created->push_back(Q.getNode()); 2662 } 2663 // If d < 0 and m > 0, subtract the numerator. 2664 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2665 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2666 if (Created) 2667 Created->push_back(Q.getNode()); 2668 } 2669 // Shift right algebraic if shift value is nonzero 2670 if (magics.s > 0) { 2671 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2672 DAG.getConstant(magics.s, getShiftAmountTy())); 2673 if (Created) 2674 Created->push_back(Q.getNode()); 2675 } 2676 // Extract the sign bit and add it to the quotient 2677 SDValue T = 2678 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2679 getShiftAmountTy())); 2680 if (Created) 2681 Created->push_back(T.getNode()); 2682 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2683} 2684 2685/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2686/// return a DAG expression to select that will generate the same value by 2687/// multiplying by a magic number. See: 2688/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2689SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2690 std::vector<SDNode*>* Created) const { 2691 EVT VT = N->getValueType(0); 2692 DebugLoc dl = N->getDebugLoc(); 2693 2694 // Check to see if we can do this. 2695 // FIXME: We should be more aggressive here. 2696 if (!isTypeLegal(VT)) 2697 return SDValue(); 2698 2699 // FIXME: We should use a narrower constant when the upper 2700 // bits are known to be zero. 2701 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2702 APInt::mu magics = N1C->getAPIntValue().magicu(); 2703 2704 // Multiply the numerator (operand 0) by the magic value 2705 // FIXME: We should support doing a MUL in a wider type 2706 SDValue Q; 2707 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2708 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2709 DAG.getConstant(magics.m, VT)); 2710 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2711 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2712 N->getOperand(0), 2713 DAG.getConstant(magics.m, VT)).getNode(), 1); 2714 else 2715 return SDValue(); // No mulhu or equvialent 2716 if (Created) 2717 Created->push_back(Q.getNode()); 2718 2719 if (magics.a == 0) { 2720 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2721 "We shouldn't generate an undefined shift!"); 2722 return DAG.getNode(ISD::SRL, dl, VT, Q, 2723 DAG.getConstant(magics.s, getShiftAmountTy())); 2724 } else { 2725 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2726 if (Created) 2727 Created->push_back(NPQ.getNode()); 2728 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2729 DAG.getConstant(1, getShiftAmountTy())); 2730 if (Created) 2731 Created->push_back(NPQ.getNode()); 2732 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2733 if (Created) 2734 Created->push_back(NPQ.getNode()); 2735 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2736 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2737 } 2738} 2739