TargetLowering.cpp revision 205218
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Target/TargetSubtarget.h" 22#include "llvm/GlobalVariable.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 195 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 196 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 197 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 198 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 199 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 200 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 201 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 202 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 203 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 204 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 205 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 206 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 207 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 208 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 209 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 210 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 211 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 212 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 213 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 214 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 215 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 216 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 217 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 218 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 219 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 220 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 221 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 222 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 223 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 224 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 225 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 226 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 227 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 228 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 229 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 230 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 231 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 232 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 233 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 234 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 235 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 236 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 237 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 238 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 239 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 240 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 241 Names[RTLIB::OEQ_F32] = "__eqsf2"; 242 Names[RTLIB::OEQ_F64] = "__eqdf2"; 243 Names[RTLIB::UNE_F32] = "__nesf2"; 244 Names[RTLIB::UNE_F64] = "__nedf2"; 245 Names[RTLIB::OGE_F32] = "__gesf2"; 246 Names[RTLIB::OGE_F64] = "__gedf2"; 247 Names[RTLIB::OLT_F32] = "__ltsf2"; 248 Names[RTLIB::OLT_F64] = "__ltdf2"; 249 Names[RTLIB::OLE_F32] = "__lesf2"; 250 Names[RTLIB::OLE_F64] = "__ledf2"; 251 Names[RTLIB::OGT_F32] = "__gtsf2"; 252 Names[RTLIB::OGT_F64] = "__gtdf2"; 253 Names[RTLIB::UO_F32] = "__unordsf2"; 254 Names[RTLIB::UO_F64] = "__unorddf2"; 255 Names[RTLIB::O_F32] = "__unordsf2"; 256 Names[RTLIB::O_F64] = "__unorddf2"; 257 Names[RTLIB::MEMCPY] = "memcpy"; 258 Names[RTLIB::MEMMOVE] = "memmove"; 259 Names[RTLIB::MEMSET] = "memset"; 260 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 261} 262 263/// InitLibcallCallingConvs - Set default libcall CallingConvs. 264/// 265static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 266 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 267 CCs[i] = CallingConv::C; 268 } 269} 270 271/// getFPEXT - Return the FPEXT_*_* value for the given types, or 272/// UNKNOWN_LIBCALL if there is none. 273RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 274 if (OpVT == MVT::f32) { 275 if (RetVT == MVT::f64) 276 return FPEXT_F32_F64; 277 } 278 279 return UNKNOWN_LIBCALL; 280} 281 282/// getFPROUND - Return the FPROUND_*_* value for the given types, or 283/// UNKNOWN_LIBCALL if there is none. 284RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 285 if (RetVT == MVT::f32) { 286 if (OpVT == MVT::f64) 287 return FPROUND_F64_F32; 288 if (OpVT == MVT::f80) 289 return FPROUND_F80_F32; 290 if (OpVT == MVT::ppcf128) 291 return FPROUND_PPCF128_F32; 292 } else if (RetVT == MVT::f64) { 293 if (OpVT == MVT::f80) 294 return FPROUND_F80_F64; 295 if (OpVT == MVT::ppcf128) 296 return FPROUND_PPCF128_F64; 297 } 298 299 return UNKNOWN_LIBCALL; 300} 301 302/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 303/// UNKNOWN_LIBCALL if there is none. 304RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 305 if (OpVT == MVT::f32) { 306 if (RetVT == MVT::i8) 307 return FPTOSINT_F32_I8; 308 if (RetVT == MVT::i16) 309 return FPTOSINT_F32_I16; 310 if (RetVT == MVT::i32) 311 return FPTOSINT_F32_I32; 312 if (RetVT == MVT::i64) 313 return FPTOSINT_F32_I64; 314 if (RetVT == MVT::i128) 315 return FPTOSINT_F32_I128; 316 } else if (OpVT == MVT::f64) { 317 if (RetVT == MVT::i32) 318 return FPTOSINT_F64_I32; 319 if (RetVT == MVT::i64) 320 return FPTOSINT_F64_I64; 321 if (RetVT == MVT::i128) 322 return FPTOSINT_F64_I128; 323 } else if (OpVT == MVT::f80) { 324 if (RetVT == MVT::i32) 325 return FPTOSINT_F80_I32; 326 if (RetVT == MVT::i64) 327 return FPTOSINT_F80_I64; 328 if (RetVT == MVT::i128) 329 return FPTOSINT_F80_I128; 330 } else if (OpVT == MVT::ppcf128) { 331 if (RetVT == MVT::i32) 332 return FPTOSINT_PPCF128_I32; 333 if (RetVT == MVT::i64) 334 return FPTOSINT_PPCF128_I64; 335 if (RetVT == MVT::i128) 336 return FPTOSINT_PPCF128_I128; 337 } 338 return UNKNOWN_LIBCALL; 339} 340 341/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 342/// UNKNOWN_LIBCALL if there is none. 343RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 344 if (OpVT == MVT::f32) { 345 if (RetVT == MVT::i8) 346 return FPTOUINT_F32_I8; 347 if (RetVT == MVT::i16) 348 return FPTOUINT_F32_I16; 349 if (RetVT == MVT::i32) 350 return FPTOUINT_F32_I32; 351 if (RetVT == MVT::i64) 352 return FPTOUINT_F32_I64; 353 if (RetVT == MVT::i128) 354 return FPTOUINT_F32_I128; 355 } else if (OpVT == MVT::f64) { 356 if (RetVT == MVT::i32) 357 return FPTOUINT_F64_I32; 358 if (RetVT == MVT::i64) 359 return FPTOUINT_F64_I64; 360 if (RetVT == MVT::i128) 361 return FPTOUINT_F64_I128; 362 } else if (OpVT == MVT::f80) { 363 if (RetVT == MVT::i32) 364 return FPTOUINT_F80_I32; 365 if (RetVT == MVT::i64) 366 return FPTOUINT_F80_I64; 367 if (RetVT == MVT::i128) 368 return FPTOUINT_F80_I128; 369 } else if (OpVT == MVT::ppcf128) { 370 if (RetVT == MVT::i32) 371 return FPTOUINT_PPCF128_I32; 372 if (RetVT == MVT::i64) 373 return FPTOUINT_PPCF128_I64; 374 if (RetVT == MVT::i128) 375 return FPTOUINT_PPCF128_I128; 376 } 377 return UNKNOWN_LIBCALL; 378} 379 380/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 381/// UNKNOWN_LIBCALL if there is none. 382RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 383 if (OpVT == MVT::i32) { 384 if (RetVT == MVT::f32) 385 return SINTTOFP_I32_F32; 386 else if (RetVT == MVT::f64) 387 return SINTTOFP_I32_F64; 388 else if (RetVT == MVT::f80) 389 return SINTTOFP_I32_F80; 390 else if (RetVT == MVT::ppcf128) 391 return SINTTOFP_I32_PPCF128; 392 } else if (OpVT == MVT::i64) { 393 if (RetVT == MVT::f32) 394 return SINTTOFP_I64_F32; 395 else if (RetVT == MVT::f64) 396 return SINTTOFP_I64_F64; 397 else if (RetVT == MVT::f80) 398 return SINTTOFP_I64_F80; 399 else if (RetVT == MVT::ppcf128) 400 return SINTTOFP_I64_PPCF128; 401 } else if (OpVT == MVT::i128) { 402 if (RetVT == MVT::f32) 403 return SINTTOFP_I128_F32; 404 else if (RetVT == MVT::f64) 405 return SINTTOFP_I128_F64; 406 else if (RetVT == MVT::f80) 407 return SINTTOFP_I128_F80; 408 else if (RetVT == MVT::ppcf128) 409 return SINTTOFP_I128_PPCF128; 410 } 411 return UNKNOWN_LIBCALL; 412} 413 414/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 415/// UNKNOWN_LIBCALL if there is none. 416RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 417 if (OpVT == MVT::i32) { 418 if (RetVT == MVT::f32) 419 return UINTTOFP_I32_F32; 420 else if (RetVT == MVT::f64) 421 return UINTTOFP_I32_F64; 422 else if (RetVT == MVT::f80) 423 return UINTTOFP_I32_F80; 424 else if (RetVT == MVT::ppcf128) 425 return UINTTOFP_I32_PPCF128; 426 } else if (OpVT == MVT::i64) { 427 if (RetVT == MVT::f32) 428 return UINTTOFP_I64_F32; 429 else if (RetVT == MVT::f64) 430 return UINTTOFP_I64_F64; 431 else if (RetVT == MVT::f80) 432 return UINTTOFP_I64_F80; 433 else if (RetVT == MVT::ppcf128) 434 return UINTTOFP_I64_PPCF128; 435 } else if (OpVT == MVT::i128) { 436 if (RetVT == MVT::f32) 437 return UINTTOFP_I128_F32; 438 else if (RetVT == MVT::f64) 439 return UINTTOFP_I128_F64; 440 else if (RetVT == MVT::f80) 441 return UINTTOFP_I128_F80; 442 else if (RetVT == MVT::ppcf128) 443 return UINTTOFP_I128_PPCF128; 444 } 445 return UNKNOWN_LIBCALL; 446} 447 448/// InitCmpLibcallCCs - Set default comparison libcall CC. 449/// 450static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 451 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 452 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 453 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 454 CCs[RTLIB::UNE_F32] = ISD::SETNE; 455 CCs[RTLIB::UNE_F64] = ISD::SETNE; 456 CCs[RTLIB::OGE_F32] = ISD::SETGE; 457 CCs[RTLIB::OGE_F64] = ISD::SETGE; 458 CCs[RTLIB::OLT_F32] = ISD::SETLT; 459 CCs[RTLIB::OLT_F64] = ISD::SETLT; 460 CCs[RTLIB::OLE_F32] = ISD::SETLE; 461 CCs[RTLIB::OLE_F64] = ISD::SETLE; 462 CCs[RTLIB::OGT_F32] = ISD::SETGT; 463 CCs[RTLIB::OGT_F64] = ISD::SETGT; 464 CCs[RTLIB::UO_F32] = ISD::SETNE; 465 CCs[RTLIB::UO_F64] = ISD::SETNE; 466 CCs[RTLIB::O_F32] = ISD::SETEQ; 467 CCs[RTLIB::O_F64] = ISD::SETEQ; 468} 469 470/// NOTE: The constructor takes ownership of TLOF. 471TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) 472 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 473 // All operations default to being supported. 474 memset(OpActions, 0, sizeof(OpActions)); 475 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 476 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 477 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 478 memset(ConvertActions, 0, sizeof(ConvertActions)); 479 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 480 481 // Set default actions for various operations. 482 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 483 // Default all indexed load / store to expand. 484 for (unsigned IM = (unsigned)ISD::PRE_INC; 485 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 486 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 487 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 488 } 489 490 // These operations default to expand. 491 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 492 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 493 } 494 495 // Most targets ignore the @llvm.prefetch intrinsic. 496 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 497 498 // ConstantFP nodes default to expand. Targets can either change this to 499 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 500 // to optimize expansions for certain constants. 501 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 502 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 503 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 504 505 // These library functions default to expand. 506 setOperationAction(ISD::FLOG , MVT::f64, Expand); 507 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 508 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 509 setOperationAction(ISD::FEXP , MVT::f64, Expand); 510 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 511 setOperationAction(ISD::FLOG , MVT::f32, Expand); 512 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 513 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 514 setOperationAction(ISD::FEXP , MVT::f32, Expand); 515 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 516 517 // Default ISD::TRAP to expand (which turns it into abort). 518 setOperationAction(ISD::TRAP, MVT::Other, Expand); 519 520 IsLittleEndian = TD->isLittleEndian(); 521 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 522 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 523 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 524 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 525 benefitFromCodePlacementOpt = false; 526 UseUnderscoreSetJmp = false; 527 UseUnderscoreLongJmp = false; 528 SelectIsExpensive = false; 529 IntDivIsCheap = false; 530 Pow2DivIsCheap = false; 531 StackPointerRegisterToSaveRestore = 0; 532 ExceptionPointerRegister = 0; 533 ExceptionSelectorRegister = 0; 534 BooleanContents = UndefinedBooleanContent; 535 SchedPreferenceInfo = SchedulingForLatency; 536 JumpBufSize = 0; 537 JumpBufAlignment = 0; 538 IfCvtBlockSizeLimit = 2; 539 IfCvtDupBlockSizeLimit = 0; 540 PrefLoopAlignment = 0; 541 542 InitLibcallNames(LibcallRoutineNames); 543 InitCmpLibcallCCs(CmpLibcallCCs); 544 InitLibcallCallingConvs(LibcallCallingConvs); 545} 546 547TargetLowering::~TargetLowering() { 548 delete &TLOF; 549} 550 551/// canOpTrap - Returns true if the operation can trap for the value type. 552/// VT must be a legal type. 553bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 554 assert(isTypeLegal(VT)); 555 switch (Op) { 556 default: 557 return false; 558 case ISD::FDIV: 559 case ISD::FREM: 560 case ISD::SDIV: 561 case ISD::UDIV: 562 case ISD::SREM: 563 case ISD::UREM: 564 return true; 565 } 566} 567 568 569static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 570 unsigned &NumIntermediates, 571 EVT &RegisterVT, 572 TargetLowering* TLI) { 573 // Figure out the right, legal destination reg to copy into. 574 unsigned NumElts = VT.getVectorNumElements(); 575 MVT EltTy = VT.getVectorElementType(); 576 577 unsigned NumVectorRegs = 1; 578 579 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 580 // could break down into LHS/RHS like LegalizeDAG does. 581 if (!isPowerOf2_32(NumElts)) { 582 NumVectorRegs = NumElts; 583 NumElts = 1; 584 } 585 586 // Divide the input until we get to a supported size. This will always 587 // end with a scalar if the target doesn't support vectors. 588 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 589 NumElts >>= 1; 590 NumVectorRegs <<= 1; 591 } 592 593 NumIntermediates = NumVectorRegs; 594 595 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 596 if (!TLI->isTypeLegal(NewVT)) 597 NewVT = EltTy; 598 IntermediateVT = NewVT; 599 600 EVT DestVT = TLI->getRegisterType(NewVT); 601 RegisterVT = DestVT; 602 if (EVT(DestVT).bitsLT(NewVT)) { 603 // Value is expanded, e.g. i64 -> i16. 604 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 605 } else { 606 // Otherwise, promotion or legal types use the same number of registers as 607 // the vector decimated to the appropriate level. 608 return NumVectorRegs; 609 } 610 611 return 1; 612} 613 614/// computeRegisterProperties - Once all of the register classes are added, 615/// this allows us to compute derived properties we expose. 616void TargetLowering::computeRegisterProperties() { 617 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 618 "Too many value types for ValueTypeActions to hold!"); 619 620 // Everything defaults to needing one register. 621 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 622 NumRegistersForVT[i] = 1; 623 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 624 } 625 // ...except isVoid, which doesn't need any registers. 626 NumRegistersForVT[MVT::isVoid] = 0; 627 628 // Find the largest integer register class. 629 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 630 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 631 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 632 633 // Every integer value type larger than this largest register takes twice as 634 // many registers to represent as the previous ValueType. 635 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 636 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 637 if (!ExpandedVT.isInteger()) 638 break; 639 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 640 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 641 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 642 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 643 } 644 645 // Inspect all of the ValueType's smaller than the largest integer 646 // register to see which ones need promotion. 647 unsigned LegalIntReg = LargestIntReg; 648 for (unsigned IntReg = LargestIntReg - 1; 649 IntReg >= (unsigned)MVT::i1; --IntReg) { 650 EVT IVT = (MVT::SimpleValueType)IntReg; 651 if (isTypeLegal(IVT)) { 652 LegalIntReg = IntReg; 653 } else { 654 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 655 (MVT::SimpleValueType)LegalIntReg; 656 ValueTypeActions.setTypeAction(IVT, Promote); 657 } 658 } 659 660 // ppcf128 type is really two f64's. 661 if (!isTypeLegal(MVT::ppcf128)) { 662 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 663 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 664 TransformToType[MVT::ppcf128] = MVT::f64; 665 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 666 } 667 668 // Decide how to handle f64. If the target does not have native f64 support, 669 // expand it to i64 and we will be generating soft float library calls. 670 if (!isTypeLegal(MVT::f64)) { 671 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 672 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 673 TransformToType[MVT::f64] = MVT::i64; 674 ValueTypeActions.setTypeAction(MVT::f64, Expand); 675 } 676 677 // Decide how to handle f32. If the target does not have native support for 678 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 679 if (!isTypeLegal(MVT::f32)) { 680 if (isTypeLegal(MVT::f64)) { 681 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 682 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 683 TransformToType[MVT::f32] = MVT::f64; 684 ValueTypeActions.setTypeAction(MVT::f32, Promote); 685 } else { 686 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 687 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 688 TransformToType[MVT::f32] = MVT::i32; 689 ValueTypeActions.setTypeAction(MVT::f32, Expand); 690 } 691 } 692 693 // Loop over all of the vector value types to see which need transformations. 694 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 695 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 696 MVT VT = (MVT::SimpleValueType)i; 697 if (!isTypeLegal(VT)) { 698 MVT IntermediateVT; 699 EVT RegisterVT; 700 unsigned NumIntermediates; 701 NumRegistersForVT[i] = 702 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 703 RegisterVT, this); 704 RegisterTypeForVT[i] = RegisterVT; 705 706 // Determine if there is a legal wider type. 707 bool IsLegalWiderType = false; 708 EVT EltVT = VT.getVectorElementType(); 709 unsigned NElts = VT.getVectorNumElements(); 710 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 711 EVT SVT = (MVT::SimpleValueType)nVT; 712 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 713 SVT.getVectorNumElements() > NElts && NElts != 1) { 714 TransformToType[i] = SVT; 715 ValueTypeActions.setTypeAction(VT, Promote); 716 IsLegalWiderType = true; 717 break; 718 } 719 } 720 if (!IsLegalWiderType) { 721 EVT NVT = VT.getPow2VectorType(); 722 if (NVT == VT) { 723 // Type is already a power of 2. The default action is to split. 724 TransformToType[i] = MVT::Other; 725 ValueTypeActions.setTypeAction(VT, Expand); 726 } else { 727 TransformToType[i] = NVT; 728 ValueTypeActions.setTypeAction(VT, Promote); 729 } 730 } 731 } 732 } 733} 734 735const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 736 return NULL; 737} 738 739 740MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 741 return PointerTy.SimpleTy; 742} 743 744MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 745 return MVT::i32; // return the default value 746} 747 748/// getVectorTypeBreakdown - Vector types are broken down into some number of 749/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 750/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 751/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 752/// 753/// This method returns the number of registers needed, and the VT for each 754/// register. It also returns the VT and quantity of the intermediate values 755/// before they are promoted/expanded. 756/// 757unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 758 EVT &IntermediateVT, 759 unsigned &NumIntermediates, 760 EVT &RegisterVT) const { 761 // Figure out the right, legal destination reg to copy into. 762 unsigned NumElts = VT.getVectorNumElements(); 763 EVT EltTy = VT.getVectorElementType(); 764 765 unsigned NumVectorRegs = 1; 766 767 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 768 // could break down into LHS/RHS like LegalizeDAG does. 769 if (!isPowerOf2_32(NumElts)) { 770 NumVectorRegs = NumElts; 771 NumElts = 1; 772 } 773 774 // Divide the input until we get to a supported size. This will always 775 // end with a scalar if the target doesn't support vectors. 776 while (NumElts > 1 && !isTypeLegal( 777 EVT::getVectorVT(Context, EltTy, NumElts))) { 778 NumElts >>= 1; 779 NumVectorRegs <<= 1; 780 } 781 782 NumIntermediates = NumVectorRegs; 783 784 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 785 if (!isTypeLegal(NewVT)) 786 NewVT = EltTy; 787 IntermediateVT = NewVT; 788 789 EVT DestVT = getRegisterType(Context, NewVT); 790 RegisterVT = DestVT; 791 if (DestVT.bitsLT(NewVT)) { 792 // Value is expanded, e.g. i64 -> i16. 793 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 794 } else { 795 // Otherwise, promotion or legal types use the same number of registers as 796 // the vector decimated to the appropriate level. 797 return NumVectorRegs; 798 } 799 800 return 1; 801} 802 803/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 804/// function arguments in the caller parameter area. This is the actual 805/// alignment, not its logarithm. 806unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 807 return TD->getCallFrameTypeAlignment(Ty); 808} 809 810/// getJumpTableEncoding - Return the entry encoding for a jump table in the 811/// current function. The returned value is a member of the 812/// MachineJumpTableInfo::JTEntryKind enum. 813unsigned TargetLowering::getJumpTableEncoding() const { 814 // In non-pic modes, just use the address of a block. 815 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 816 return MachineJumpTableInfo::EK_BlockAddress; 817 818 // In PIC mode, if the target supports a GPRel32 directive, use it. 819 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 820 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 821 822 // Otherwise, use a label difference. 823 return MachineJumpTableInfo::EK_LabelDifference32; 824} 825 826SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 827 SelectionDAG &DAG) const { 828 // If our PIC model is GP relative, use the global offset table as the base. 829 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 830 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 831 return Table; 832} 833 834/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 835/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 836/// MCExpr. 837const MCExpr * 838TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 839 unsigned JTI,MCContext &Ctx) const{ 840 // The normal PIC reloc base is the label at the start of the jump table. 841 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 842} 843 844bool 845TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 846 // Assume that everything is safe in static mode. 847 if (getTargetMachine().getRelocationModel() == Reloc::Static) 848 return true; 849 850 // In dynamic-no-pic mode, assume that known defined values are safe. 851 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 852 GA && 853 !GA->getGlobal()->isDeclaration() && 854 !GA->getGlobal()->isWeakForLinker()) 855 return true; 856 857 // Otherwise assume nothing is safe. 858 return false; 859} 860 861//===----------------------------------------------------------------------===// 862// Optimization Methods 863//===----------------------------------------------------------------------===// 864 865/// ShrinkDemandedConstant - Check to see if the specified operand of the 866/// specified instruction is a constant integer. If so, check to see if there 867/// are any bits set in the constant that are not demanded. If so, shrink the 868/// constant and return true. 869bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 870 const APInt &Demanded) { 871 DebugLoc dl = Op.getDebugLoc(); 872 873 // FIXME: ISD::SELECT, ISD::SELECT_CC 874 switch (Op.getOpcode()) { 875 default: break; 876 case ISD::XOR: 877 case ISD::AND: 878 case ISD::OR: { 879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 880 if (!C) return false; 881 882 if (Op.getOpcode() == ISD::XOR && 883 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 884 return false; 885 886 // if we can expand it to have all bits set, do it 887 if (C->getAPIntValue().intersects(~Demanded)) { 888 EVT VT = Op.getValueType(); 889 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 890 DAG.getConstant(Demanded & 891 C->getAPIntValue(), 892 VT)); 893 return CombineTo(Op, New); 894 } 895 896 break; 897 } 898 } 899 900 return false; 901} 902 903/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 904/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 905/// cast, but it could be generalized for targets with other types of 906/// implicit widening casts. 907bool 908TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 909 unsigned BitWidth, 910 const APInt &Demanded, 911 DebugLoc dl) { 912 assert(Op.getNumOperands() == 2 && 913 "ShrinkDemandedOp only supports binary operators!"); 914 assert(Op.getNode()->getNumValues() == 1 && 915 "ShrinkDemandedOp only supports nodes with one result!"); 916 917 // Don't do this if the node has another user, which may require the 918 // full value. 919 if (!Op.getNode()->hasOneUse()) 920 return false; 921 922 // Search for the smallest integer type with free casts to and from 923 // Op's type. For expedience, just check power-of-2 integer types. 924 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 925 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 926 if (!isPowerOf2_32(SmallVTBits)) 927 SmallVTBits = NextPowerOf2(SmallVTBits); 928 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 929 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 930 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 931 TLI.isZExtFree(SmallVT, Op.getValueType())) { 932 // We found a type with free casts. 933 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 934 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 935 Op.getNode()->getOperand(0)), 936 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 937 Op.getNode()->getOperand(1))); 938 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 939 return CombineTo(Op, Z); 940 } 941 } 942 return false; 943} 944 945/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 946/// DemandedMask bits of the result of Op are ever used downstream. If we can 947/// use this information to simplify Op, create a new simplified DAG node and 948/// return true, returning the original and new nodes in Old and New. Otherwise, 949/// analyze the expression and return a mask of KnownOne and KnownZero bits for 950/// the expression (used to simplify the caller). The KnownZero/One bits may 951/// only be accurate for those bits in the DemandedMask. 952bool TargetLowering::SimplifyDemandedBits(SDValue Op, 953 const APInt &DemandedMask, 954 APInt &KnownZero, 955 APInt &KnownOne, 956 TargetLoweringOpt &TLO, 957 unsigned Depth) const { 958 unsigned BitWidth = DemandedMask.getBitWidth(); 959 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 960 "Mask size mismatches value type size!"); 961 APInt NewMask = DemandedMask; 962 DebugLoc dl = Op.getDebugLoc(); 963 964 // Don't know anything. 965 KnownZero = KnownOne = APInt(BitWidth, 0); 966 967 // Other users may use these bits. 968 if (!Op.getNode()->hasOneUse()) { 969 if (Depth != 0) { 970 // If not at the root, Just compute the KnownZero/KnownOne bits to 971 // simplify things downstream. 972 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 973 return false; 974 } 975 // If this is the root being simplified, allow it to have multiple uses, 976 // just set the NewMask to all bits. 977 NewMask = APInt::getAllOnesValue(BitWidth); 978 } else if (DemandedMask == 0) { 979 // Not demanding any bits from Op. 980 if (Op.getOpcode() != ISD::UNDEF) 981 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 982 return false; 983 } else if (Depth == 6) { // Limit search depth. 984 return false; 985 } 986 987 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 988 switch (Op.getOpcode()) { 989 case ISD::Constant: 990 // We know all of the bits for a constant! 991 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 992 KnownZero = ~KnownOne & NewMask; 993 return false; // Don't fall through, will infinitely loop. 994 case ISD::AND: 995 // If the RHS is a constant, check to see if the LHS would be zero without 996 // using the bits from the RHS. Below, we use knowledge about the RHS to 997 // simplify the LHS, here we're using information from the LHS to simplify 998 // the RHS. 999 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1000 APInt LHSZero, LHSOne; 1001 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1002 LHSZero, LHSOne, Depth+1); 1003 // If the LHS already has zeros where RHSC does, this and is dead. 1004 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1005 return TLO.CombineTo(Op, Op.getOperand(0)); 1006 // If any of the set bits in the RHS are known zero on the LHS, shrink 1007 // the constant. 1008 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1009 return true; 1010 } 1011 1012 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1013 KnownOne, TLO, Depth+1)) 1014 return true; 1015 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1016 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1017 KnownZero2, KnownOne2, TLO, Depth+1)) 1018 return true; 1019 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1020 1021 // If all of the demanded bits are known one on one side, return the other. 1022 // These bits cannot contribute to the result of the 'and'. 1023 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1024 return TLO.CombineTo(Op, Op.getOperand(0)); 1025 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1026 return TLO.CombineTo(Op, Op.getOperand(1)); 1027 // If all of the demanded bits in the inputs are known zeros, return zero. 1028 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1029 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1030 // If the RHS is a constant, see if we can simplify it. 1031 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1032 return true; 1033 // If the operation can be done in a smaller type, do so. 1034 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1035 return true; 1036 1037 // Output known-1 bits are only known if set in both the LHS & RHS. 1038 KnownOne &= KnownOne2; 1039 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1040 KnownZero |= KnownZero2; 1041 break; 1042 case ISD::OR: 1043 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1044 KnownOne, TLO, Depth+1)) 1045 return true; 1046 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1047 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1048 KnownZero2, KnownOne2, TLO, Depth+1)) 1049 return true; 1050 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1051 1052 // If all of the demanded bits are known zero on one side, return the other. 1053 // These bits cannot contribute to the result of the 'or'. 1054 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1055 return TLO.CombineTo(Op, Op.getOperand(0)); 1056 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1057 return TLO.CombineTo(Op, Op.getOperand(1)); 1058 // If all of the potentially set bits on one side are known to be set on 1059 // the other side, just use the 'other' side. 1060 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1061 return TLO.CombineTo(Op, Op.getOperand(0)); 1062 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1063 return TLO.CombineTo(Op, Op.getOperand(1)); 1064 // If the RHS is a constant, see if we can simplify it. 1065 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1066 return true; 1067 // If the operation can be done in a smaller type, do so. 1068 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1069 return true; 1070 1071 // Output known-0 bits are only known if clear in both the LHS & RHS. 1072 KnownZero &= KnownZero2; 1073 // Output known-1 are known to be set if set in either the LHS | RHS. 1074 KnownOne |= KnownOne2; 1075 break; 1076 case ISD::XOR: 1077 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1078 KnownOne, TLO, Depth+1)) 1079 return true; 1080 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1081 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1082 KnownOne2, TLO, Depth+1)) 1083 return true; 1084 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1085 1086 // If all of the demanded bits are known zero on one side, return the other. 1087 // These bits cannot contribute to the result of the 'xor'. 1088 if ((KnownZero & NewMask) == NewMask) 1089 return TLO.CombineTo(Op, Op.getOperand(0)); 1090 if ((KnownZero2 & NewMask) == NewMask) 1091 return TLO.CombineTo(Op, Op.getOperand(1)); 1092 // If the operation can be done in a smaller type, do so. 1093 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1094 return true; 1095 1096 // If all of the unknown bits are known to be zero on one side or the other 1097 // (but not both) turn this into an *inclusive* or. 1098 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1099 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1100 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1101 Op.getOperand(0), 1102 Op.getOperand(1))); 1103 1104 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1105 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1106 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1107 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1108 1109 // If all of the demanded bits on one side are known, and all of the set 1110 // bits on that side are also known to be set on the other side, turn this 1111 // into an AND, as we know the bits will be cleared. 1112 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1113 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1114 if ((KnownOne & KnownOne2) == KnownOne) { 1115 EVT VT = Op.getValueType(); 1116 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1117 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1118 Op.getOperand(0), ANDC)); 1119 } 1120 } 1121 1122 // If the RHS is a constant, see if we can simplify it. 1123 // for XOR, we prefer to force bits to 1 if they will make a -1. 1124 // if we can't force bits, try to shrink constant 1125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1126 APInt Expanded = C->getAPIntValue() | (~NewMask); 1127 // if we can expand it to have all bits set, do it 1128 if (Expanded.isAllOnesValue()) { 1129 if (Expanded != C->getAPIntValue()) { 1130 EVT VT = Op.getValueType(); 1131 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1132 TLO.DAG.getConstant(Expanded, VT)); 1133 return TLO.CombineTo(Op, New); 1134 } 1135 // if it already has all the bits set, nothing to change 1136 // but don't shrink either! 1137 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1138 return true; 1139 } 1140 } 1141 1142 KnownZero = KnownZeroOut; 1143 KnownOne = KnownOneOut; 1144 break; 1145 case ISD::SELECT: 1146 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1147 KnownOne, TLO, Depth+1)) 1148 return true; 1149 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1150 KnownOne2, TLO, Depth+1)) 1151 return true; 1152 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1153 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1154 1155 // If the operands are constants, see if we can simplify them. 1156 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1157 return true; 1158 1159 // Only known if known in both the LHS and RHS. 1160 KnownOne &= KnownOne2; 1161 KnownZero &= KnownZero2; 1162 break; 1163 case ISD::SELECT_CC: 1164 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1165 KnownOne, TLO, Depth+1)) 1166 return true; 1167 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1168 KnownOne2, TLO, Depth+1)) 1169 return true; 1170 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1171 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1172 1173 // If the operands are constants, see if we can simplify them. 1174 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1175 return true; 1176 1177 // Only known if known in both the LHS and RHS. 1178 KnownOne &= KnownOne2; 1179 KnownZero &= KnownZero2; 1180 break; 1181 case ISD::SHL: 1182 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1183 unsigned ShAmt = SA->getZExtValue(); 1184 SDValue InOp = Op.getOperand(0); 1185 1186 // If the shift count is an invalid immediate, don't do anything. 1187 if (ShAmt >= BitWidth) 1188 break; 1189 1190 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1191 // single shift. We can do this if the bottom bits (which are shifted 1192 // out) are never demanded. 1193 if (InOp.getOpcode() == ISD::SRL && 1194 isa<ConstantSDNode>(InOp.getOperand(1))) { 1195 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1196 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1197 unsigned Opc = ISD::SHL; 1198 int Diff = ShAmt-C1; 1199 if (Diff < 0) { 1200 Diff = -Diff; 1201 Opc = ISD::SRL; 1202 } 1203 1204 SDValue NewSA = 1205 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1206 EVT VT = Op.getValueType(); 1207 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1208 InOp.getOperand(0), NewSA)); 1209 } 1210 } 1211 1212 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1213 KnownZero, KnownOne, TLO, Depth+1)) 1214 return true; 1215 KnownZero <<= SA->getZExtValue(); 1216 KnownOne <<= SA->getZExtValue(); 1217 // low bits known zero. 1218 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1219 } 1220 break; 1221 case ISD::SRL: 1222 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1223 EVT VT = Op.getValueType(); 1224 unsigned ShAmt = SA->getZExtValue(); 1225 unsigned VTSize = VT.getSizeInBits(); 1226 SDValue InOp = Op.getOperand(0); 1227 1228 // If the shift count is an invalid immediate, don't do anything. 1229 if (ShAmt >= BitWidth) 1230 break; 1231 1232 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1233 // single shift. We can do this if the top bits (which are shifted out) 1234 // are never demanded. 1235 if (InOp.getOpcode() == ISD::SHL && 1236 isa<ConstantSDNode>(InOp.getOperand(1))) { 1237 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1238 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1239 unsigned Opc = ISD::SRL; 1240 int Diff = ShAmt-C1; 1241 if (Diff < 0) { 1242 Diff = -Diff; 1243 Opc = ISD::SHL; 1244 } 1245 1246 SDValue NewSA = 1247 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1248 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1249 InOp.getOperand(0), NewSA)); 1250 } 1251 } 1252 1253 // Compute the new bits that are at the top now. 1254 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1255 KnownZero, KnownOne, TLO, Depth+1)) 1256 return true; 1257 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1258 KnownZero = KnownZero.lshr(ShAmt); 1259 KnownOne = KnownOne.lshr(ShAmt); 1260 1261 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1262 KnownZero |= HighBits; // High bits known zero. 1263 } 1264 break; 1265 case ISD::SRA: 1266 // If this is an arithmetic shift right and only the low-bit is set, we can 1267 // always convert this into a logical shr, even if the shift amount is 1268 // variable. The low bit of the shift cannot be an input sign bit unless 1269 // the shift amount is >= the size of the datatype, which is undefined. 1270 if (DemandedMask == 1) 1271 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1272 Op.getOperand(0), Op.getOperand(1))); 1273 1274 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1275 EVT VT = Op.getValueType(); 1276 unsigned ShAmt = SA->getZExtValue(); 1277 1278 // If the shift count is an invalid immediate, don't do anything. 1279 if (ShAmt >= BitWidth) 1280 break; 1281 1282 APInt InDemandedMask = (NewMask << ShAmt); 1283 1284 // If any of the demanded bits are produced by the sign extension, we also 1285 // demand the input sign bit. 1286 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1287 if (HighBits.intersects(NewMask)) 1288 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1289 1290 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1291 KnownZero, KnownOne, TLO, Depth+1)) 1292 return true; 1293 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1294 KnownZero = KnownZero.lshr(ShAmt); 1295 KnownOne = KnownOne.lshr(ShAmt); 1296 1297 // Handle the sign bit, adjusted to where it is now in the mask. 1298 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1299 1300 // If the input sign bit is known to be zero, or if none of the top bits 1301 // are demanded, turn this into an unsigned shift right. 1302 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1303 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1304 Op.getOperand(0), 1305 Op.getOperand(1))); 1306 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1307 KnownOne |= HighBits; 1308 } 1309 } 1310 break; 1311 case ISD::SIGN_EXTEND_INREG: { 1312 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1313 1314 // Sign extension. Compute the demanded bits in the result that are not 1315 // present in the input. 1316 APInt NewBits = 1317 APInt::getHighBitsSet(BitWidth, 1318 BitWidth - EVT.getScalarType().getSizeInBits()) & 1319 NewMask; 1320 1321 // If none of the extended bits are demanded, eliminate the sextinreg. 1322 if (NewBits == 0) 1323 return TLO.CombineTo(Op, Op.getOperand(0)); 1324 1325 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1326 InSignBit.zext(BitWidth); 1327 APInt InputDemandedBits = 1328 APInt::getLowBitsSet(BitWidth, 1329 EVT.getScalarType().getSizeInBits()) & 1330 NewMask; 1331 1332 // Since the sign extended bits are demanded, we know that the sign 1333 // bit is demanded. 1334 InputDemandedBits |= InSignBit; 1335 1336 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1337 KnownZero, KnownOne, TLO, Depth+1)) 1338 return true; 1339 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1340 1341 // If the sign bit of the input is known set or clear, then we know the 1342 // top bits of the result. 1343 1344 // If the input sign bit is known zero, convert this into a zero extension. 1345 if (KnownZero.intersects(InSignBit)) 1346 return TLO.CombineTo(Op, 1347 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1348 1349 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1350 KnownOne |= NewBits; 1351 KnownZero &= ~NewBits; 1352 } else { // Input sign bit unknown 1353 KnownZero &= ~NewBits; 1354 KnownOne &= ~NewBits; 1355 } 1356 break; 1357 } 1358 case ISD::ZERO_EXTEND: { 1359 unsigned OperandBitWidth = 1360 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1361 APInt InMask = NewMask; 1362 InMask.trunc(OperandBitWidth); 1363 1364 // If none of the top bits are demanded, convert this into an any_extend. 1365 APInt NewBits = 1366 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1367 if (!NewBits.intersects(NewMask)) 1368 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1369 Op.getValueType(), 1370 Op.getOperand(0))); 1371 1372 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1373 KnownZero, KnownOne, TLO, Depth+1)) 1374 return true; 1375 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1376 KnownZero.zext(BitWidth); 1377 KnownOne.zext(BitWidth); 1378 KnownZero |= NewBits; 1379 break; 1380 } 1381 case ISD::SIGN_EXTEND: { 1382 EVT InVT = Op.getOperand(0).getValueType(); 1383 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1384 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1385 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1386 APInt NewBits = ~InMask & NewMask; 1387 1388 // If none of the top bits are demanded, convert this into an any_extend. 1389 if (NewBits == 0) 1390 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1391 Op.getValueType(), 1392 Op.getOperand(0))); 1393 1394 // Since some of the sign extended bits are demanded, we know that the sign 1395 // bit is demanded. 1396 APInt InDemandedBits = InMask & NewMask; 1397 InDemandedBits |= InSignBit; 1398 InDemandedBits.trunc(InBits); 1399 1400 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1401 KnownOne, TLO, Depth+1)) 1402 return true; 1403 KnownZero.zext(BitWidth); 1404 KnownOne.zext(BitWidth); 1405 1406 // If the sign bit is known zero, convert this to a zero extend. 1407 if (KnownZero.intersects(InSignBit)) 1408 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1409 Op.getValueType(), 1410 Op.getOperand(0))); 1411 1412 // If the sign bit is known one, the top bits match. 1413 if (KnownOne.intersects(InSignBit)) { 1414 KnownOne |= NewBits; 1415 KnownZero &= ~NewBits; 1416 } else { // Otherwise, top bits aren't known. 1417 KnownOne &= ~NewBits; 1418 KnownZero &= ~NewBits; 1419 } 1420 break; 1421 } 1422 case ISD::ANY_EXTEND: { 1423 unsigned OperandBitWidth = 1424 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1425 APInt InMask = NewMask; 1426 InMask.trunc(OperandBitWidth); 1427 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1428 KnownZero, KnownOne, TLO, Depth+1)) 1429 return true; 1430 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1431 KnownZero.zext(BitWidth); 1432 KnownOne.zext(BitWidth); 1433 break; 1434 } 1435 case ISD::TRUNCATE: { 1436 // Simplify the input, using demanded bit information, and compute the known 1437 // zero/one bits live out. 1438 unsigned OperandBitWidth = 1439 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1440 APInt TruncMask = NewMask; 1441 TruncMask.zext(OperandBitWidth); 1442 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1443 KnownZero, KnownOne, TLO, Depth+1)) 1444 return true; 1445 KnownZero.trunc(BitWidth); 1446 KnownOne.trunc(BitWidth); 1447 1448 // If the input is only used by this truncate, see if we can shrink it based 1449 // on the known demanded bits. 1450 if (Op.getOperand(0).getNode()->hasOneUse()) { 1451 SDValue In = Op.getOperand(0); 1452 switch (In.getOpcode()) { 1453 default: break; 1454 case ISD::SRL: 1455 // Shrink SRL by a constant if none of the high bits shifted in are 1456 // demanded. 1457 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1458 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1459 OperandBitWidth - BitWidth); 1460 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1461 HighBits.trunc(BitWidth); 1462 1463 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1464 // None of the shifted in bits are needed. Add a truncate of the 1465 // shift input, then shift it. 1466 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1467 Op.getValueType(), 1468 In.getOperand(0)); 1469 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1470 Op.getValueType(), 1471 NewTrunc, 1472 In.getOperand(1))); 1473 } 1474 } 1475 break; 1476 } 1477 } 1478 1479 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1480 break; 1481 } 1482 case ISD::AssertZext: { 1483 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1484 APInt InMask = APInt::getLowBitsSet(BitWidth, 1485 VT.getSizeInBits()); 1486 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1487 KnownZero, KnownOne, TLO, Depth+1)) 1488 return true; 1489 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1490 KnownZero |= ~InMask & NewMask; 1491 break; 1492 } 1493 case ISD::BIT_CONVERT: 1494#if 0 1495 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1496 // is demanded, turn this into a FGETSIGN. 1497 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1498 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1499 !MVT::isVector(Op.getOperand(0).getValueType())) { 1500 // Only do this xform if FGETSIGN is valid or if before legalize. 1501 if (!TLO.AfterLegalize || 1502 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1503 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1504 // place. We expect the SHL to be eliminated by other optimizations. 1505 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1506 Op.getOperand(0)); 1507 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1508 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1509 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1510 Sign, ShAmt)); 1511 } 1512 } 1513#endif 1514 break; 1515 case ISD::ADD: 1516 case ISD::MUL: 1517 case ISD::SUB: { 1518 // Add, Sub, and Mul don't demand any bits in positions beyond that 1519 // of the highest bit demanded of them. 1520 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1521 BitWidth - NewMask.countLeadingZeros()); 1522 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1523 KnownOne2, TLO, Depth+1)) 1524 return true; 1525 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1526 KnownOne2, TLO, Depth+1)) 1527 return true; 1528 // See if the operation should be performed at a smaller bit width. 1529 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1530 return true; 1531 } 1532 // FALL THROUGH 1533 default: 1534 // Just use ComputeMaskedBits to compute output bits. 1535 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1536 break; 1537 } 1538 1539 // If we know the value of all of the demanded bits, return this as a 1540 // constant. 1541 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1542 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1543 1544 return false; 1545} 1546 1547/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1548/// in Mask are known to be either zero or one and return them in the 1549/// KnownZero/KnownOne bitsets. 1550void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1551 const APInt &Mask, 1552 APInt &KnownZero, 1553 APInt &KnownOne, 1554 const SelectionDAG &DAG, 1555 unsigned Depth) const { 1556 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1557 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1558 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1559 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1560 "Should use MaskedValueIsZero if you don't know whether Op" 1561 " is a target node!"); 1562 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1563} 1564 1565/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1566/// targets that want to expose additional information about sign bits to the 1567/// DAG Combiner. 1568unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1569 unsigned Depth) const { 1570 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1571 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1572 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1573 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1574 "Should use ComputeNumSignBits if you don't know whether Op" 1575 " is a target node!"); 1576 return 1; 1577} 1578 1579/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1580/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1581/// determine which bit is set. 1582/// 1583static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1584 // A left-shift of a constant one will have exactly one bit set, because 1585 // shifting the bit off the end is undefined. 1586 if (Val.getOpcode() == ISD::SHL) 1587 if (ConstantSDNode *C = 1588 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1589 if (C->getAPIntValue() == 1) 1590 return true; 1591 1592 // Similarly, a right-shift of a constant sign-bit will have exactly 1593 // one bit set. 1594 if (Val.getOpcode() == ISD::SRL) 1595 if (ConstantSDNode *C = 1596 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1597 if (C->getAPIntValue().isSignBit()) 1598 return true; 1599 1600 // More could be done here, though the above checks are enough 1601 // to handle some common cases. 1602 1603 // Fall back to ComputeMaskedBits to catch other known cases. 1604 EVT OpVT = Val.getValueType(); 1605 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1606 APInt Mask = APInt::getAllOnesValue(BitWidth); 1607 APInt KnownZero, KnownOne; 1608 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1609 return (KnownZero.countPopulation() == BitWidth - 1) && 1610 (KnownOne.countPopulation() == 1); 1611} 1612 1613/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1614/// and cc. If it is unable to simplify it, return a null SDValue. 1615SDValue 1616TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1617 ISD::CondCode Cond, bool foldBooleans, 1618 DAGCombinerInfo &DCI, DebugLoc dl) const { 1619 SelectionDAG &DAG = DCI.DAG; 1620 LLVMContext &Context = *DAG.getContext(); 1621 1622 // These setcc operations always fold. 1623 switch (Cond) { 1624 default: break; 1625 case ISD::SETFALSE: 1626 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1627 case ISD::SETTRUE: 1628 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1629 } 1630 1631 if (isa<ConstantSDNode>(N0.getNode())) { 1632 // Ensure that the constant occurs on the RHS, and fold constant 1633 // comparisons. 1634 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1635 } 1636 1637 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1638 const APInt &C1 = N1C->getAPIntValue(); 1639 1640 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1641 // equality comparison, then we're just comparing whether X itself is 1642 // zero. 1643 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1644 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1645 N0.getOperand(1).getOpcode() == ISD::Constant) { 1646 const APInt &ShAmt 1647 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1648 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1649 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1650 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1651 // (srl (ctlz x), 5) == 0 -> X != 0 1652 // (srl (ctlz x), 5) != 1 -> X != 0 1653 Cond = ISD::SETNE; 1654 } else { 1655 // (srl (ctlz x), 5) != 0 -> X == 0 1656 // (srl (ctlz x), 5) == 1 -> X == 0 1657 Cond = ISD::SETEQ; 1658 } 1659 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1660 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1661 Zero, Cond); 1662 } 1663 } 1664 1665 // If the LHS is '(and load, const)', the RHS is 0, 1666 // the test is for equality or unsigned, and all 1 bits of the const are 1667 // in the same partial word, see if we can shorten the load. 1668 if (DCI.isBeforeLegalize() && 1669 N0.getOpcode() == ISD::AND && C1 == 0 && 1670 N0.getNode()->hasOneUse() && 1671 isa<LoadSDNode>(N0.getOperand(0)) && 1672 N0.getOperand(0).getNode()->hasOneUse() && 1673 isa<ConstantSDNode>(N0.getOperand(1))) { 1674 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1675 APInt bestMask; 1676 unsigned bestWidth = 0, bestOffset = 0; 1677 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1678 unsigned origWidth = N0.getValueType().getSizeInBits(); 1679 unsigned maskWidth = origWidth; 1680 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1681 // 8 bits, but have to be careful... 1682 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1683 origWidth = Lod->getMemoryVT().getSizeInBits(); 1684 const APInt &Mask = 1685 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1686 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1687 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1688 for (unsigned offset=0; offset<origWidth/width; offset++) { 1689 if ((newMask & Mask) == Mask) { 1690 if (!TD->isLittleEndian()) 1691 bestOffset = (origWidth/width - offset - 1) * (width/8); 1692 else 1693 bestOffset = (uint64_t)offset * (width/8); 1694 bestMask = Mask.lshr(offset * (width/8) * 8); 1695 bestWidth = width; 1696 break; 1697 } 1698 newMask = newMask << width; 1699 } 1700 } 1701 } 1702 if (bestWidth) { 1703 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1704 if (newVT.isRound()) { 1705 EVT PtrType = Lod->getOperand(1).getValueType(); 1706 SDValue Ptr = Lod->getBasePtr(); 1707 if (bestOffset != 0) 1708 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1709 DAG.getConstant(bestOffset, PtrType)); 1710 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1711 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1712 Lod->getSrcValue(), 1713 Lod->getSrcValueOffset() + bestOffset, 1714 false, false, NewAlign); 1715 return DAG.getSetCC(dl, VT, 1716 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1717 DAG.getConstant(bestMask.trunc(bestWidth), 1718 newVT)), 1719 DAG.getConstant(0LL, newVT), Cond); 1720 } 1721 } 1722 } 1723 1724 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1725 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1726 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1727 1728 // If the comparison constant has bits in the upper part, the 1729 // zero-extended value could never match. 1730 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1731 C1.getBitWidth() - InSize))) { 1732 switch (Cond) { 1733 case ISD::SETUGT: 1734 case ISD::SETUGE: 1735 case ISD::SETEQ: return DAG.getConstant(0, VT); 1736 case ISD::SETULT: 1737 case ISD::SETULE: 1738 case ISD::SETNE: return DAG.getConstant(1, VT); 1739 case ISD::SETGT: 1740 case ISD::SETGE: 1741 // True if the sign bit of C1 is set. 1742 return DAG.getConstant(C1.isNegative(), VT); 1743 case ISD::SETLT: 1744 case ISD::SETLE: 1745 // True if the sign bit of C1 isn't set. 1746 return DAG.getConstant(C1.isNonNegative(), VT); 1747 default: 1748 break; 1749 } 1750 } 1751 1752 // Otherwise, we can perform the comparison with the low bits. 1753 switch (Cond) { 1754 case ISD::SETEQ: 1755 case ISD::SETNE: 1756 case ISD::SETUGT: 1757 case ISD::SETUGE: 1758 case ISD::SETULT: 1759 case ISD::SETULE: { 1760 EVT newVT = N0.getOperand(0).getValueType(); 1761 if (DCI.isBeforeLegalizeOps() || 1762 (isOperationLegal(ISD::SETCC, newVT) && 1763 getCondCodeAction(Cond, newVT)==Legal)) 1764 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1765 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1766 Cond); 1767 break; 1768 } 1769 default: 1770 break; // todo, be more careful with signed comparisons 1771 } 1772 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1773 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1774 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1775 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1776 EVT ExtDstTy = N0.getValueType(); 1777 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1778 1779 // If the extended part has any inconsistent bits, it cannot ever 1780 // compare equal. In other words, they have to be all ones or all 1781 // zeros. 1782 APInt ExtBits = 1783 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1784 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1785 return DAG.getConstant(Cond == ISD::SETNE, VT); 1786 1787 SDValue ZextOp; 1788 EVT Op0Ty = N0.getOperand(0).getValueType(); 1789 if (Op0Ty == ExtSrcTy) { 1790 ZextOp = N0.getOperand(0); 1791 } else { 1792 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1793 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1794 DAG.getConstant(Imm, Op0Ty)); 1795 } 1796 if (!DCI.isCalledByLegalizer()) 1797 DCI.AddToWorklist(ZextOp.getNode()); 1798 // Otherwise, make this a use of a zext. 1799 return DAG.getSetCC(dl, VT, ZextOp, 1800 DAG.getConstant(C1 & APInt::getLowBitsSet( 1801 ExtDstTyBits, 1802 ExtSrcTyBits), 1803 ExtDstTy), 1804 Cond); 1805 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1806 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1807 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1808 if (N0.getOpcode() == ISD::SETCC && 1809 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1810 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1811 if (TrueWhenTrue) 1812 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1813 // Invert the condition. 1814 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1815 CC = ISD::getSetCCInverse(CC, 1816 N0.getOperand(0).getValueType().isInteger()); 1817 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1818 } 1819 1820 if ((N0.getOpcode() == ISD::XOR || 1821 (N0.getOpcode() == ISD::AND && 1822 N0.getOperand(0).getOpcode() == ISD::XOR && 1823 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1824 isa<ConstantSDNode>(N0.getOperand(1)) && 1825 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1826 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1827 // can only do this if the top bits are known zero. 1828 unsigned BitWidth = N0.getValueSizeInBits(); 1829 if (DAG.MaskedValueIsZero(N0, 1830 APInt::getHighBitsSet(BitWidth, 1831 BitWidth-1))) { 1832 // Okay, get the un-inverted input value. 1833 SDValue Val; 1834 if (N0.getOpcode() == ISD::XOR) 1835 Val = N0.getOperand(0); 1836 else { 1837 assert(N0.getOpcode() == ISD::AND && 1838 N0.getOperand(0).getOpcode() == ISD::XOR); 1839 // ((X^1)&1)^1 -> X & 1 1840 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1841 N0.getOperand(0).getOperand(0), 1842 N0.getOperand(1)); 1843 } 1844 1845 return DAG.getSetCC(dl, VT, Val, N1, 1846 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1847 } 1848 } else if (N1C->getAPIntValue() == 1 && 1849 (VT == MVT::i1 || 1850 getBooleanContents() == ZeroOrOneBooleanContent)) { 1851 SDValue Op0 = N0; 1852 if (Op0.getOpcode() == ISD::TRUNCATE) 1853 Op0 = Op0.getOperand(0); 1854 1855 if ((Op0.getOpcode() == ISD::XOR) && 1856 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1857 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1858 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1859 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1860 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1861 Cond); 1862 } else if (Op0.getOpcode() == ISD::AND && 1863 isa<ConstantSDNode>(Op0.getOperand(1)) && 1864 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1865 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1866 if (Op0.getValueType() != VT) 1867 Op0 = DAG.getNode(ISD::AND, dl, VT, 1868 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1869 DAG.getConstant(1, VT)); 1870 return DAG.getSetCC(dl, VT, Op0, 1871 DAG.getConstant(0, Op0.getValueType()), 1872 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1873 } 1874 } 1875 } 1876 1877 APInt MinVal, MaxVal; 1878 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1879 if (ISD::isSignedIntSetCC(Cond)) { 1880 MinVal = APInt::getSignedMinValue(OperandBitSize); 1881 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1882 } else { 1883 MinVal = APInt::getMinValue(OperandBitSize); 1884 MaxVal = APInt::getMaxValue(OperandBitSize); 1885 } 1886 1887 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1888 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1889 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1890 // X >= C0 --> X > (C0-1) 1891 return DAG.getSetCC(dl, VT, N0, 1892 DAG.getConstant(C1-1, N1.getValueType()), 1893 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1894 } 1895 1896 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1897 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1898 // X <= C0 --> X < (C0+1) 1899 return DAG.getSetCC(dl, VT, N0, 1900 DAG.getConstant(C1+1, N1.getValueType()), 1901 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1902 } 1903 1904 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1905 return DAG.getConstant(0, VT); // X < MIN --> false 1906 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1907 return DAG.getConstant(1, VT); // X >= MIN --> true 1908 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1909 return DAG.getConstant(0, VT); // X > MAX --> false 1910 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1911 return DAG.getConstant(1, VT); // X <= MAX --> true 1912 1913 // Canonicalize setgt X, Min --> setne X, Min 1914 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1915 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1916 // Canonicalize setlt X, Max --> setne X, Max 1917 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1918 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1919 1920 // If we have setult X, 1, turn it into seteq X, 0 1921 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1922 return DAG.getSetCC(dl, VT, N0, 1923 DAG.getConstant(MinVal, N0.getValueType()), 1924 ISD::SETEQ); 1925 // If we have setugt X, Max-1, turn it into seteq X, Max 1926 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1927 return DAG.getSetCC(dl, VT, N0, 1928 DAG.getConstant(MaxVal, N0.getValueType()), 1929 ISD::SETEQ); 1930 1931 // If we have "setcc X, C0", check to see if we can shrink the immediate 1932 // by changing cc. 1933 1934 // SETUGT X, SINTMAX -> SETLT X, 0 1935 if (Cond == ISD::SETUGT && 1936 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1937 return DAG.getSetCC(dl, VT, N0, 1938 DAG.getConstant(0, N1.getValueType()), 1939 ISD::SETLT); 1940 1941 // SETULT X, SINTMIN -> SETGT X, -1 1942 if (Cond == ISD::SETULT && 1943 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1944 SDValue ConstMinusOne = 1945 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1946 N1.getValueType()); 1947 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1948 } 1949 1950 // Fold bit comparisons when we can. 1951 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1952 (VT == N0.getValueType() || 1953 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1954 N0.getOpcode() == ISD::AND) 1955 if (ConstantSDNode *AndRHS = 1956 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1957 EVT ShiftTy = DCI.isBeforeLegalize() ? 1958 getPointerTy() : getShiftAmountTy(); 1959 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1960 // Perform the xform if the AND RHS is a single bit. 1961 if (AndRHS->getAPIntValue().isPowerOf2()) { 1962 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1963 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1964 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1965 } 1966 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1967 // (X & 8) == 8 --> (X & 8) >> 3 1968 // Perform the xform if C1 is a single bit. 1969 if (C1.isPowerOf2()) { 1970 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1971 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1972 DAG.getConstant(C1.logBase2(), ShiftTy))); 1973 } 1974 } 1975 } 1976 } 1977 1978 if (isa<ConstantFPSDNode>(N0.getNode())) { 1979 // Constant fold or commute setcc. 1980 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1981 if (O.getNode()) return O; 1982 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1983 // If the RHS of an FP comparison is a constant, simplify it away in 1984 // some cases. 1985 if (CFP->getValueAPF().isNaN()) { 1986 // If an operand is known to be a nan, we can fold it. 1987 switch (ISD::getUnorderedFlavor(Cond)) { 1988 default: llvm_unreachable("Unknown flavor!"); 1989 case 0: // Known false. 1990 return DAG.getConstant(0, VT); 1991 case 1: // Known true. 1992 return DAG.getConstant(1, VT); 1993 case 2: // Undefined. 1994 return DAG.getUNDEF(VT); 1995 } 1996 } 1997 1998 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1999 // constant if knowing that the operand is non-nan is enough. We prefer to 2000 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2001 // materialize 0.0. 2002 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2003 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2004 2005 // If the condition is not legal, see if we can find an equivalent one 2006 // which is legal. 2007 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2008 // If the comparison was an awkward floating-point == or != and one of 2009 // the comparison operands is infinity or negative infinity, convert the 2010 // condition to a less-awkward <= or >=. 2011 if (CFP->getValueAPF().isInfinity()) { 2012 if (CFP->getValueAPF().isNegative()) { 2013 if (Cond == ISD::SETOEQ && 2014 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2015 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2016 if (Cond == ISD::SETUEQ && 2017 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2018 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2019 if (Cond == ISD::SETUNE && 2020 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2021 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2022 if (Cond == ISD::SETONE && 2023 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2024 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2025 } else { 2026 if (Cond == ISD::SETOEQ && 2027 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2028 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2029 if (Cond == ISD::SETUEQ && 2030 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2031 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2032 if (Cond == ISD::SETUNE && 2033 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2034 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2035 if (Cond == ISD::SETONE && 2036 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2037 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2038 } 2039 } 2040 } 2041 } 2042 2043 if (N0 == N1) { 2044 // We can always fold X == X for integer setcc's. 2045 if (N0.getValueType().isInteger()) 2046 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2047 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2048 if (UOF == 2) // FP operators that are undefined on NaNs. 2049 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2050 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2051 return DAG.getConstant(UOF, VT); 2052 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2053 // if it is not already. 2054 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2055 if (NewCond != Cond) 2056 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2057 } 2058 2059 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2060 N0.getValueType().isInteger()) { 2061 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2062 N0.getOpcode() == ISD::XOR) { 2063 // Simplify (X+Y) == (X+Z) --> Y == Z 2064 if (N0.getOpcode() == N1.getOpcode()) { 2065 if (N0.getOperand(0) == N1.getOperand(0)) 2066 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2067 if (N0.getOperand(1) == N1.getOperand(1)) 2068 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2069 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2070 // If X op Y == Y op X, try other combinations. 2071 if (N0.getOperand(0) == N1.getOperand(1)) 2072 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2073 Cond); 2074 if (N0.getOperand(1) == N1.getOperand(0)) 2075 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2076 Cond); 2077 } 2078 } 2079 2080 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2081 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2082 // Turn (X+C1) == C2 --> X == C2-C1 2083 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2084 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2085 DAG.getConstant(RHSC->getAPIntValue()- 2086 LHSR->getAPIntValue(), 2087 N0.getValueType()), Cond); 2088 } 2089 2090 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2091 if (N0.getOpcode() == ISD::XOR) 2092 // If we know that all of the inverted bits are zero, don't bother 2093 // performing the inversion. 2094 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2095 return 2096 DAG.getSetCC(dl, VT, N0.getOperand(0), 2097 DAG.getConstant(LHSR->getAPIntValue() ^ 2098 RHSC->getAPIntValue(), 2099 N0.getValueType()), 2100 Cond); 2101 } 2102 2103 // Turn (C1-X) == C2 --> X == C1-C2 2104 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2105 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2106 return 2107 DAG.getSetCC(dl, VT, N0.getOperand(1), 2108 DAG.getConstant(SUBC->getAPIntValue() - 2109 RHSC->getAPIntValue(), 2110 N0.getValueType()), 2111 Cond); 2112 } 2113 } 2114 } 2115 2116 // Simplify (X+Z) == X --> Z == 0 2117 if (N0.getOperand(0) == N1) 2118 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2119 DAG.getConstant(0, N0.getValueType()), Cond); 2120 if (N0.getOperand(1) == N1) { 2121 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2122 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2123 DAG.getConstant(0, N0.getValueType()), Cond); 2124 else if (N0.getNode()->hasOneUse()) { 2125 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2126 // (Z-X) == X --> Z == X<<1 2127 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2128 N1, 2129 DAG.getConstant(1, getShiftAmountTy())); 2130 if (!DCI.isCalledByLegalizer()) 2131 DCI.AddToWorklist(SH.getNode()); 2132 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2133 } 2134 } 2135 } 2136 2137 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2138 N1.getOpcode() == ISD::XOR) { 2139 // Simplify X == (X+Z) --> Z == 0 2140 if (N1.getOperand(0) == N0) { 2141 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2142 DAG.getConstant(0, N1.getValueType()), Cond); 2143 } else if (N1.getOperand(1) == N0) { 2144 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2145 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2146 DAG.getConstant(0, N1.getValueType()), Cond); 2147 } else if (N1.getNode()->hasOneUse()) { 2148 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2149 // X == (Z-X) --> X<<1 == Z 2150 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2151 DAG.getConstant(1, getShiftAmountTy())); 2152 if (!DCI.isCalledByLegalizer()) 2153 DCI.AddToWorklist(SH.getNode()); 2154 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2155 } 2156 } 2157 } 2158 2159 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2160 // Note that where y is variable and is known to have at most 2161 // one bit set (for example, if it is z&1) we cannot do this; 2162 // the expressions are not equivalent when y==0. 2163 if (N0.getOpcode() == ISD::AND) 2164 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2165 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2166 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2167 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2168 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2169 } 2170 } 2171 if (N1.getOpcode() == ISD::AND) 2172 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2173 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2174 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2175 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2176 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2177 } 2178 } 2179 } 2180 2181 // Fold away ALL boolean setcc's. 2182 SDValue Temp; 2183 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2184 switch (Cond) { 2185 default: llvm_unreachable("Unknown integer setcc!"); 2186 case ISD::SETEQ: // X == Y -> ~(X^Y) 2187 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2188 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2189 if (!DCI.isCalledByLegalizer()) 2190 DCI.AddToWorklist(Temp.getNode()); 2191 break; 2192 case ISD::SETNE: // X != Y --> (X^Y) 2193 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2194 break; 2195 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2196 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2197 Temp = DAG.getNOT(dl, N0, MVT::i1); 2198 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2199 if (!DCI.isCalledByLegalizer()) 2200 DCI.AddToWorklist(Temp.getNode()); 2201 break; 2202 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2203 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2204 Temp = DAG.getNOT(dl, N1, MVT::i1); 2205 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2206 if (!DCI.isCalledByLegalizer()) 2207 DCI.AddToWorklist(Temp.getNode()); 2208 break; 2209 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2210 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2211 Temp = DAG.getNOT(dl, N0, MVT::i1); 2212 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2213 if (!DCI.isCalledByLegalizer()) 2214 DCI.AddToWorklist(Temp.getNode()); 2215 break; 2216 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2217 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2218 Temp = DAG.getNOT(dl, N1, MVT::i1); 2219 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2220 break; 2221 } 2222 if (VT != MVT::i1) { 2223 if (!DCI.isCalledByLegalizer()) 2224 DCI.AddToWorklist(N0.getNode()); 2225 // FIXME: If running after legalize, we probably can't do this. 2226 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2227 } 2228 return N0; 2229 } 2230 2231 // Could not fold it. 2232 return SDValue(); 2233} 2234 2235/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2236/// node is a GlobalAddress + offset. 2237bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2238 int64_t &Offset) const { 2239 if (isa<GlobalAddressSDNode>(N)) { 2240 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2241 GA = GASD->getGlobal(); 2242 Offset += GASD->getOffset(); 2243 return true; 2244 } 2245 2246 if (N->getOpcode() == ISD::ADD) { 2247 SDValue N1 = N->getOperand(0); 2248 SDValue N2 = N->getOperand(1); 2249 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2250 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2251 if (V) { 2252 Offset += V->getSExtValue(); 2253 return true; 2254 } 2255 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2256 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2257 if (V) { 2258 Offset += V->getSExtValue(); 2259 return true; 2260 } 2261 } 2262 } 2263 return false; 2264} 2265 2266 2267SDValue TargetLowering:: 2268PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2269 // Default implementation: no optimization. 2270 return SDValue(); 2271} 2272 2273//===----------------------------------------------------------------------===// 2274// Inline Assembler Implementation Methods 2275//===----------------------------------------------------------------------===// 2276 2277 2278TargetLowering::ConstraintType 2279TargetLowering::getConstraintType(const std::string &Constraint) const { 2280 // FIXME: lots more standard ones to handle. 2281 if (Constraint.size() == 1) { 2282 switch (Constraint[0]) { 2283 default: break; 2284 case 'r': return C_RegisterClass; 2285 case 'm': // memory 2286 case 'o': // offsetable 2287 case 'V': // not offsetable 2288 return C_Memory; 2289 case 'i': // Simple Integer or Relocatable Constant 2290 case 'n': // Simple Integer 2291 case 's': // Relocatable Constant 2292 case 'X': // Allow ANY value. 2293 case 'I': // Target registers. 2294 case 'J': 2295 case 'K': 2296 case 'L': 2297 case 'M': 2298 case 'N': 2299 case 'O': 2300 case 'P': 2301 return C_Other; 2302 } 2303 } 2304 2305 if (Constraint.size() > 1 && Constraint[0] == '{' && 2306 Constraint[Constraint.size()-1] == '}') 2307 return C_Register; 2308 return C_Unknown; 2309} 2310 2311/// LowerXConstraint - try to replace an X constraint, which matches anything, 2312/// with another that has more specific requirements based on the type of the 2313/// corresponding operand. 2314const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2315 if (ConstraintVT.isInteger()) 2316 return "r"; 2317 if (ConstraintVT.isFloatingPoint()) 2318 return "f"; // works for many targets 2319 return 0; 2320} 2321 2322/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2323/// vector. If it is invalid, don't add anything to Ops. 2324void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2325 char ConstraintLetter, 2326 bool hasMemory, 2327 std::vector<SDValue> &Ops, 2328 SelectionDAG &DAG) const { 2329 switch (ConstraintLetter) { 2330 default: break; 2331 case 'X': // Allows any operand; labels (basic block) use this. 2332 if (Op.getOpcode() == ISD::BasicBlock) { 2333 Ops.push_back(Op); 2334 return; 2335 } 2336 // fall through 2337 case 'i': // Simple Integer or Relocatable Constant 2338 case 'n': // Simple Integer 2339 case 's': { // Relocatable Constant 2340 // These operands are interested in values of the form (GV+C), where C may 2341 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2342 // is possible and fine if either GV or C are missing. 2343 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2344 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2345 2346 // If we have "(add GV, C)", pull out GV/C 2347 if (Op.getOpcode() == ISD::ADD) { 2348 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2349 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2350 if (C == 0 || GA == 0) { 2351 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2352 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2353 } 2354 if (C == 0 || GA == 0) 2355 C = 0, GA = 0; 2356 } 2357 2358 // If we find a valid operand, map to the TargetXXX version so that the 2359 // value itself doesn't get selected. 2360 if (GA) { // Either &GV or &GV+C 2361 if (ConstraintLetter != 'n') { 2362 int64_t Offs = GA->getOffset(); 2363 if (C) Offs += C->getZExtValue(); 2364 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2365 Op.getValueType(), Offs)); 2366 return; 2367 } 2368 } 2369 if (C) { // just C, no GV. 2370 // Simple constants are not allowed for 's'. 2371 if (ConstraintLetter != 's') { 2372 // gcc prints these as sign extended. Sign extend value to 64 bits 2373 // now; without this it would get ZExt'd later in 2374 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2375 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2376 MVT::i64)); 2377 return; 2378 } 2379 } 2380 break; 2381 } 2382 } 2383} 2384 2385std::vector<unsigned> TargetLowering:: 2386getRegClassForInlineAsmConstraint(const std::string &Constraint, 2387 EVT VT) const { 2388 return std::vector<unsigned>(); 2389} 2390 2391 2392std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2393getRegForInlineAsmConstraint(const std::string &Constraint, 2394 EVT VT) const { 2395 if (Constraint[0] != '{') 2396 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2397 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2398 2399 // Remove the braces from around the name. 2400 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2401 2402 // Figure out which register class contains this reg. 2403 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2404 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2405 E = RI->regclass_end(); RCI != E; ++RCI) { 2406 const TargetRegisterClass *RC = *RCI; 2407 2408 // If none of the value types for this register class are valid, we 2409 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2410 bool isLegal = false; 2411 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2412 I != E; ++I) { 2413 if (isTypeLegal(*I)) { 2414 isLegal = true; 2415 break; 2416 } 2417 } 2418 2419 if (!isLegal) continue; 2420 2421 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2422 I != E; ++I) { 2423 if (RegName.equals_lower(RI->getName(*I))) 2424 return std::make_pair(*I, RC); 2425 } 2426 } 2427 2428 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2429} 2430 2431//===----------------------------------------------------------------------===// 2432// Constraint Selection. 2433 2434/// isMatchingInputConstraint - Return true of this is an input operand that is 2435/// a matching constraint like "4". 2436bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2437 assert(!ConstraintCode.empty() && "No known constraint!"); 2438 return isdigit(ConstraintCode[0]); 2439} 2440 2441/// getMatchedOperand - If this is an input matching constraint, this method 2442/// returns the output operand it matches. 2443unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2444 assert(!ConstraintCode.empty() && "No known constraint!"); 2445 return atoi(ConstraintCode.c_str()); 2446} 2447 2448 2449/// getConstraintGenerality - Return an integer indicating how general CT 2450/// is. 2451static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2452 switch (CT) { 2453 default: llvm_unreachable("Unknown constraint type!"); 2454 case TargetLowering::C_Other: 2455 case TargetLowering::C_Unknown: 2456 return 0; 2457 case TargetLowering::C_Register: 2458 return 1; 2459 case TargetLowering::C_RegisterClass: 2460 return 2; 2461 case TargetLowering::C_Memory: 2462 return 3; 2463 } 2464} 2465 2466/// ChooseConstraint - If there are multiple different constraints that we 2467/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2468/// This is somewhat tricky: constraints fall into four classes: 2469/// Other -> immediates and magic values 2470/// Register -> one specific register 2471/// RegisterClass -> a group of regs 2472/// Memory -> memory 2473/// Ideally, we would pick the most specific constraint possible: if we have 2474/// something that fits into a register, we would pick it. The problem here 2475/// is that if we have something that could either be in a register or in 2476/// memory that use of the register could cause selection of *other* 2477/// operands to fail: they might only succeed if we pick memory. Because of 2478/// this the heuristic we use is: 2479/// 2480/// 1) If there is an 'other' constraint, and if the operand is valid for 2481/// that constraint, use it. This makes us take advantage of 'i' 2482/// constraints when available. 2483/// 2) Otherwise, pick the most general constraint present. This prefers 2484/// 'm' over 'r', for example. 2485/// 2486static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2487 bool hasMemory, const TargetLowering &TLI, 2488 SDValue Op, SelectionDAG *DAG) { 2489 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2490 unsigned BestIdx = 0; 2491 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2492 int BestGenerality = -1; 2493 2494 // Loop over the options, keeping track of the most general one. 2495 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2496 TargetLowering::ConstraintType CType = 2497 TLI.getConstraintType(OpInfo.Codes[i]); 2498 2499 // If this is an 'other' constraint, see if the operand is valid for it. 2500 // For example, on X86 we might have an 'rI' constraint. If the operand 2501 // is an integer in the range [0..31] we want to use I (saving a load 2502 // of a register), otherwise we must use 'r'. 2503 if (CType == TargetLowering::C_Other && Op.getNode()) { 2504 assert(OpInfo.Codes[i].size() == 1 && 2505 "Unhandled multi-letter 'other' constraint"); 2506 std::vector<SDValue> ResultOps; 2507 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2508 ResultOps, *DAG); 2509 if (!ResultOps.empty()) { 2510 BestType = CType; 2511 BestIdx = i; 2512 break; 2513 } 2514 } 2515 2516 // This constraint letter is more general than the previous one, use it. 2517 int Generality = getConstraintGenerality(CType); 2518 if (Generality > BestGenerality) { 2519 BestType = CType; 2520 BestIdx = i; 2521 BestGenerality = Generality; 2522 } 2523 } 2524 2525 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2526 OpInfo.ConstraintType = BestType; 2527} 2528 2529/// ComputeConstraintToUse - Determines the constraint code and constraint 2530/// type to use for the specific AsmOperandInfo, setting 2531/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2532void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2533 SDValue Op, 2534 bool hasMemory, 2535 SelectionDAG *DAG) const { 2536 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2537 2538 // Single-letter constraints ('r') are very common. 2539 if (OpInfo.Codes.size() == 1) { 2540 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2541 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2542 } else { 2543 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2544 } 2545 2546 // 'X' matches anything. 2547 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2548 // Labels and constants are handled elsewhere ('X' is the only thing 2549 // that matches labels). For Functions, the type here is the type of 2550 // the result, which is not what we want to look at; leave them alone. 2551 Value *v = OpInfo.CallOperandVal; 2552 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2553 OpInfo.CallOperandVal = v; 2554 return; 2555 } 2556 2557 // Otherwise, try to resolve it to something we know about by looking at 2558 // the actual operand type. 2559 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2560 OpInfo.ConstraintCode = Repl; 2561 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2562 } 2563 } 2564} 2565 2566//===----------------------------------------------------------------------===// 2567// Loop Strength Reduction hooks 2568//===----------------------------------------------------------------------===// 2569 2570/// isLegalAddressingMode - Return true if the addressing mode represented 2571/// by AM is legal for this target, for a load/store of the specified type. 2572bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2573 const Type *Ty) const { 2574 // The default implementation of this implements a conservative RISCy, r+r and 2575 // r+i addr mode. 2576 2577 // Allows a sign-extended 16-bit immediate field. 2578 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2579 return false; 2580 2581 // No global is ever allowed as a base. 2582 if (AM.BaseGV) 2583 return false; 2584 2585 // Only support r+r, 2586 switch (AM.Scale) { 2587 case 0: // "r+i" or just "i", depending on HasBaseReg. 2588 break; 2589 case 1: 2590 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2591 return false; 2592 // Otherwise we have r+r or r+i. 2593 break; 2594 case 2: 2595 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2596 return false; 2597 // Allow 2*r as r+r. 2598 break; 2599 } 2600 2601 return true; 2602} 2603 2604/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2605/// return a DAG expression to select that will generate the same value by 2606/// multiplying by a magic number. See: 2607/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2608SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2609 std::vector<SDNode*>* Created) const { 2610 EVT VT = N->getValueType(0); 2611 DebugLoc dl= N->getDebugLoc(); 2612 2613 // Check to see if we can do this. 2614 // FIXME: We should be more aggressive here. 2615 if (!isTypeLegal(VT)) 2616 return SDValue(); 2617 2618 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2619 APInt::ms magics = d.magic(); 2620 2621 // Multiply the numerator (operand 0) by the magic value 2622 // FIXME: We should support doing a MUL in a wider type 2623 SDValue Q; 2624 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2625 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2626 DAG.getConstant(magics.m, VT)); 2627 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2628 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2629 N->getOperand(0), 2630 DAG.getConstant(magics.m, VT)).getNode(), 1); 2631 else 2632 return SDValue(); // No mulhs or equvialent 2633 // If d > 0 and m < 0, add the numerator 2634 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2635 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2636 if (Created) 2637 Created->push_back(Q.getNode()); 2638 } 2639 // If d < 0 and m > 0, subtract the numerator. 2640 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2641 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2642 if (Created) 2643 Created->push_back(Q.getNode()); 2644 } 2645 // Shift right algebraic if shift value is nonzero 2646 if (magics.s > 0) { 2647 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2648 DAG.getConstant(magics.s, getShiftAmountTy())); 2649 if (Created) 2650 Created->push_back(Q.getNode()); 2651 } 2652 // Extract the sign bit and add it to the quotient 2653 SDValue T = 2654 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2655 getShiftAmountTy())); 2656 if (Created) 2657 Created->push_back(T.getNode()); 2658 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2659} 2660 2661/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2662/// return a DAG expression to select that will generate the same value by 2663/// multiplying by a magic number. See: 2664/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2665SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2666 std::vector<SDNode*>* Created) const { 2667 EVT VT = N->getValueType(0); 2668 DebugLoc dl = N->getDebugLoc(); 2669 2670 // Check to see if we can do this. 2671 // FIXME: We should be more aggressive here. 2672 if (!isTypeLegal(VT)) 2673 return SDValue(); 2674 2675 // FIXME: We should use a narrower constant when the upper 2676 // bits are known to be zero. 2677 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2678 APInt::mu magics = N1C->getAPIntValue().magicu(); 2679 2680 // Multiply the numerator (operand 0) by the magic value 2681 // FIXME: We should support doing a MUL in a wider type 2682 SDValue Q; 2683 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2684 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2685 DAG.getConstant(magics.m, VT)); 2686 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2687 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2688 N->getOperand(0), 2689 DAG.getConstant(magics.m, VT)).getNode(), 1); 2690 else 2691 return SDValue(); // No mulhu or equvialent 2692 if (Created) 2693 Created->push_back(Q.getNode()); 2694 2695 if (magics.a == 0) { 2696 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2697 "We shouldn't generate an undefined shift!"); 2698 return DAG.getNode(ISD::SRL, dl, VT, Q, 2699 DAG.getConstant(magics.s, getShiftAmountTy())); 2700 } else { 2701 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2702 if (Created) 2703 Created->push_back(NPQ.getNode()); 2704 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2705 DAG.getConstant(1, getShiftAmountTy())); 2706 if (Created) 2707 Created->push_back(NPQ.getNode()); 2708 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2709 if (Created) 2710 Created->push_back(NPQ.getNode()); 2711 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2712 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2713 } 2714} 2715