TargetLowering.cpp revision 201360 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/Target/TargetData.h"
17#include "llvm/Target/TargetLoweringObjectFile.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetRegisterInfo.h"
20#include "llvm/Target/TargetSubtarget.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28using namespace llvm;
29
30namespace llvm {
31TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
32  bool isLocal = GV->hasLocalLinkage();
33  bool isDeclaration = GV->isDeclaration();
34  // FIXME: what should we do for protected and internal visibility?
35  // For variables, is internal different from hidden?
36  bool isHidden = GV->hasHiddenVisibility();
37
38  if (reloc == Reloc::PIC_) {
39    if (isLocal || isHidden)
40      return TLSModel::LocalDynamic;
41    else
42      return TLSModel::GeneralDynamic;
43  } else {
44    if (!isDeclaration || isHidden)
45      return TLSModel::LocalExec;
46    else
47      return TLSModel::InitialExec;
48  }
49}
50}
51
52/// InitLibcallNames - Set default libcall names.
53///
54static void InitLibcallNames(const char **Names) {
55  Names[RTLIB::SHL_I16] = "__ashlhi3";
56  Names[RTLIB::SHL_I32] = "__ashlsi3";
57  Names[RTLIB::SHL_I64] = "__ashldi3";
58  Names[RTLIB::SHL_I128] = "__ashlti3";
59  Names[RTLIB::SRL_I16] = "__lshrhi3";
60  Names[RTLIB::SRL_I32] = "__lshrsi3";
61  Names[RTLIB::SRL_I64] = "__lshrdi3";
62  Names[RTLIB::SRL_I128] = "__lshrti3";
63  Names[RTLIB::SRA_I16] = "__ashrhi3";
64  Names[RTLIB::SRA_I32] = "__ashrsi3";
65  Names[RTLIB::SRA_I64] = "__ashrdi3";
66  Names[RTLIB::SRA_I128] = "__ashrti3";
67  Names[RTLIB::MUL_I8] = "__mulqi3";
68  Names[RTLIB::MUL_I16] = "__mulhi3";
69  Names[RTLIB::MUL_I32] = "__mulsi3";
70  Names[RTLIB::MUL_I64] = "__muldi3";
71  Names[RTLIB::MUL_I128] = "__multi3";
72  Names[RTLIB::SDIV_I8] = "__divqi3";
73  Names[RTLIB::SDIV_I16] = "__divhi3";
74  Names[RTLIB::SDIV_I32] = "__divsi3";
75  Names[RTLIB::SDIV_I64] = "__divdi3";
76  Names[RTLIB::SDIV_I128] = "__divti3";
77  Names[RTLIB::UDIV_I8] = "__udivqi3";
78  Names[RTLIB::UDIV_I16] = "__udivhi3";
79  Names[RTLIB::UDIV_I32] = "__udivsi3";
80  Names[RTLIB::UDIV_I64] = "__udivdi3";
81  Names[RTLIB::UDIV_I128] = "__udivti3";
82  Names[RTLIB::SREM_I8] = "__modqi3";
83  Names[RTLIB::SREM_I16] = "__modhi3";
84  Names[RTLIB::SREM_I32] = "__modsi3";
85  Names[RTLIB::SREM_I64] = "__moddi3";
86  Names[RTLIB::SREM_I128] = "__modti3";
87  Names[RTLIB::UREM_I8] = "__umodqi3";
88  Names[RTLIB::UREM_I16] = "__umodhi3";
89  Names[RTLIB::UREM_I32] = "__umodsi3";
90  Names[RTLIB::UREM_I64] = "__umoddi3";
91  Names[RTLIB::UREM_I128] = "__umodti3";
92  Names[RTLIB::NEG_I32] = "__negsi2";
93  Names[RTLIB::NEG_I64] = "__negdi2";
94  Names[RTLIB::ADD_F32] = "__addsf3";
95  Names[RTLIB::ADD_F64] = "__adddf3";
96  Names[RTLIB::ADD_F80] = "__addxf3";
97  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98  Names[RTLIB::SUB_F32] = "__subsf3";
99  Names[RTLIB::SUB_F64] = "__subdf3";
100  Names[RTLIB::SUB_F80] = "__subxf3";
101  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102  Names[RTLIB::MUL_F32] = "__mulsf3";
103  Names[RTLIB::MUL_F64] = "__muldf3";
104  Names[RTLIB::MUL_F80] = "__mulxf3";
105  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106  Names[RTLIB::DIV_F32] = "__divsf3";
107  Names[RTLIB::DIV_F64] = "__divdf3";
108  Names[RTLIB::DIV_F80] = "__divxf3";
109  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110  Names[RTLIB::REM_F32] = "fmodf";
111  Names[RTLIB::REM_F64] = "fmod";
112  Names[RTLIB::REM_F80] = "fmodl";
113  Names[RTLIB::REM_PPCF128] = "fmodl";
114  Names[RTLIB::POWI_F32] = "__powisf2";
115  Names[RTLIB::POWI_F64] = "__powidf2";
116  Names[RTLIB::POWI_F80] = "__powixf2";
117  Names[RTLIB::POWI_PPCF128] = "__powitf2";
118  Names[RTLIB::SQRT_F32] = "sqrtf";
119  Names[RTLIB::SQRT_F64] = "sqrt";
120  Names[RTLIB::SQRT_F80] = "sqrtl";
121  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
122  Names[RTLIB::LOG_F32] = "logf";
123  Names[RTLIB::LOG_F64] = "log";
124  Names[RTLIB::LOG_F80] = "logl";
125  Names[RTLIB::LOG_PPCF128] = "logl";
126  Names[RTLIB::LOG2_F32] = "log2f";
127  Names[RTLIB::LOG2_F64] = "log2";
128  Names[RTLIB::LOG2_F80] = "log2l";
129  Names[RTLIB::LOG2_PPCF128] = "log2l";
130  Names[RTLIB::LOG10_F32] = "log10f";
131  Names[RTLIB::LOG10_F64] = "log10";
132  Names[RTLIB::LOG10_F80] = "log10l";
133  Names[RTLIB::LOG10_PPCF128] = "log10l";
134  Names[RTLIB::EXP_F32] = "expf";
135  Names[RTLIB::EXP_F64] = "exp";
136  Names[RTLIB::EXP_F80] = "expl";
137  Names[RTLIB::EXP_PPCF128] = "expl";
138  Names[RTLIB::EXP2_F32] = "exp2f";
139  Names[RTLIB::EXP2_F64] = "exp2";
140  Names[RTLIB::EXP2_F80] = "exp2l";
141  Names[RTLIB::EXP2_PPCF128] = "exp2l";
142  Names[RTLIB::SIN_F32] = "sinf";
143  Names[RTLIB::SIN_F64] = "sin";
144  Names[RTLIB::SIN_F80] = "sinl";
145  Names[RTLIB::SIN_PPCF128] = "sinl";
146  Names[RTLIB::COS_F32] = "cosf";
147  Names[RTLIB::COS_F64] = "cos";
148  Names[RTLIB::COS_F80] = "cosl";
149  Names[RTLIB::COS_PPCF128] = "cosl";
150  Names[RTLIB::POW_F32] = "powf";
151  Names[RTLIB::POW_F64] = "pow";
152  Names[RTLIB::POW_F80] = "powl";
153  Names[RTLIB::POW_PPCF128] = "powl";
154  Names[RTLIB::CEIL_F32] = "ceilf";
155  Names[RTLIB::CEIL_F64] = "ceil";
156  Names[RTLIB::CEIL_F80] = "ceill";
157  Names[RTLIB::CEIL_PPCF128] = "ceill";
158  Names[RTLIB::TRUNC_F32] = "truncf";
159  Names[RTLIB::TRUNC_F64] = "trunc";
160  Names[RTLIB::TRUNC_F80] = "truncl";
161  Names[RTLIB::TRUNC_PPCF128] = "truncl";
162  Names[RTLIB::RINT_F32] = "rintf";
163  Names[RTLIB::RINT_F64] = "rint";
164  Names[RTLIB::RINT_F80] = "rintl";
165  Names[RTLIB::RINT_PPCF128] = "rintl";
166  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
167  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
168  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
169  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
170  Names[RTLIB::FLOOR_F32] = "floorf";
171  Names[RTLIB::FLOOR_F64] = "floor";
172  Names[RTLIB::FLOOR_F80] = "floorl";
173  Names[RTLIB::FLOOR_PPCF128] = "floorl";
174  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
175  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
176  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
177  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
178  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
179  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
180  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
181  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
182  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
183  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
184  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
185  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
186  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
187  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
188  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
189  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
190  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
191  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
192  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
193  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
194  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
195  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
196  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
197  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
198  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
199  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
200  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
201  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
202  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
203  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
204  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
205  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
206  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
207  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
208  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
209  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
210  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
211  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
212  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
213  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
214  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
215  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
216  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
217  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
218  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
219  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
220  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
221  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
222  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
223  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
224  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
225  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
226  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
227  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
228  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
229  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
230  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
231  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
232  Names[RTLIB::OEQ_F32] = "__eqsf2";
233  Names[RTLIB::OEQ_F64] = "__eqdf2";
234  Names[RTLIB::UNE_F32] = "__nesf2";
235  Names[RTLIB::UNE_F64] = "__nedf2";
236  Names[RTLIB::OGE_F32] = "__gesf2";
237  Names[RTLIB::OGE_F64] = "__gedf2";
238  Names[RTLIB::OLT_F32] = "__ltsf2";
239  Names[RTLIB::OLT_F64] = "__ltdf2";
240  Names[RTLIB::OLE_F32] = "__lesf2";
241  Names[RTLIB::OLE_F64] = "__ledf2";
242  Names[RTLIB::OGT_F32] = "__gtsf2";
243  Names[RTLIB::OGT_F64] = "__gtdf2";
244  Names[RTLIB::UO_F32] = "__unordsf2";
245  Names[RTLIB::UO_F64] = "__unorddf2";
246  Names[RTLIB::O_F32] = "__unordsf2";
247  Names[RTLIB::O_F64] = "__unorddf2";
248  Names[RTLIB::MEMCPY] = "memcpy";
249  Names[RTLIB::MEMMOVE] = "memmove";
250  Names[RTLIB::MEMSET] = "memset";
251  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
252}
253
254/// InitLibcallCallingConvs - Set default libcall CallingConvs.
255///
256static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
257  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
258    CCs[i] = CallingConv::C;
259  }
260}
261
262/// getFPEXT - Return the FPEXT_*_* value for the given types, or
263/// UNKNOWN_LIBCALL if there is none.
264RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
265  if (OpVT == MVT::f32) {
266    if (RetVT == MVT::f64)
267      return FPEXT_F32_F64;
268  }
269  return UNKNOWN_LIBCALL;
270}
271
272/// getFPROUND - Return the FPROUND_*_* value for the given types, or
273/// UNKNOWN_LIBCALL if there is none.
274RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
275  if (RetVT == MVT::f32) {
276    if (OpVT == MVT::f64)
277      return FPROUND_F64_F32;
278    if (OpVT == MVT::f80)
279      return FPROUND_F80_F32;
280    if (OpVT == MVT::ppcf128)
281      return FPROUND_PPCF128_F32;
282  } else if (RetVT == MVT::f64) {
283    if (OpVT == MVT::f80)
284      return FPROUND_F80_F64;
285    if (OpVT == MVT::ppcf128)
286      return FPROUND_PPCF128_F64;
287  }
288  return UNKNOWN_LIBCALL;
289}
290
291/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
292/// UNKNOWN_LIBCALL if there is none.
293RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
294  if (OpVT == MVT::f32) {
295    if (RetVT == MVT::i8)
296      return FPTOSINT_F32_I8;
297    if (RetVT == MVT::i16)
298      return FPTOSINT_F32_I16;
299    if (RetVT == MVT::i32)
300      return FPTOSINT_F32_I32;
301    if (RetVT == MVT::i64)
302      return FPTOSINT_F32_I64;
303    if (RetVT == MVT::i128)
304      return FPTOSINT_F32_I128;
305  } else if (OpVT == MVT::f64) {
306    if (RetVT == MVT::i32)
307      return FPTOSINT_F64_I32;
308    if (RetVT == MVT::i64)
309      return FPTOSINT_F64_I64;
310    if (RetVT == MVT::i128)
311      return FPTOSINT_F64_I128;
312  } else if (OpVT == MVT::f80) {
313    if (RetVT == MVT::i32)
314      return FPTOSINT_F80_I32;
315    if (RetVT == MVT::i64)
316      return FPTOSINT_F80_I64;
317    if (RetVT == MVT::i128)
318      return FPTOSINT_F80_I128;
319  } else if (OpVT == MVT::ppcf128) {
320    if (RetVT == MVT::i32)
321      return FPTOSINT_PPCF128_I32;
322    if (RetVT == MVT::i64)
323      return FPTOSINT_PPCF128_I64;
324    if (RetVT == MVT::i128)
325      return FPTOSINT_PPCF128_I128;
326  }
327  return UNKNOWN_LIBCALL;
328}
329
330/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
331/// UNKNOWN_LIBCALL if there is none.
332RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
333  if (OpVT == MVT::f32) {
334    if (RetVT == MVT::i8)
335      return FPTOUINT_F32_I8;
336    if (RetVT == MVT::i16)
337      return FPTOUINT_F32_I16;
338    if (RetVT == MVT::i32)
339      return FPTOUINT_F32_I32;
340    if (RetVT == MVT::i64)
341      return FPTOUINT_F32_I64;
342    if (RetVT == MVT::i128)
343      return FPTOUINT_F32_I128;
344  } else if (OpVT == MVT::f64) {
345    if (RetVT == MVT::i32)
346      return FPTOUINT_F64_I32;
347    if (RetVT == MVT::i64)
348      return FPTOUINT_F64_I64;
349    if (RetVT == MVT::i128)
350      return FPTOUINT_F64_I128;
351  } else if (OpVT == MVT::f80) {
352    if (RetVT == MVT::i32)
353      return FPTOUINT_F80_I32;
354    if (RetVT == MVT::i64)
355      return FPTOUINT_F80_I64;
356    if (RetVT == MVT::i128)
357      return FPTOUINT_F80_I128;
358  } else if (OpVT == MVT::ppcf128) {
359    if (RetVT == MVT::i32)
360      return FPTOUINT_PPCF128_I32;
361    if (RetVT == MVT::i64)
362      return FPTOUINT_PPCF128_I64;
363    if (RetVT == MVT::i128)
364      return FPTOUINT_PPCF128_I128;
365  }
366  return UNKNOWN_LIBCALL;
367}
368
369/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
370/// UNKNOWN_LIBCALL if there is none.
371RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
372  if (OpVT == MVT::i32) {
373    if (RetVT == MVT::f32)
374      return SINTTOFP_I32_F32;
375    else if (RetVT == MVT::f64)
376      return SINTTOFP_I32_F64;
377    else if (RetVT == MVT::f80)
378      return SINTTOFP_I32_F80;
379    else if (RetVT == MVT::ppcf128)
380      return SINTTOFP_I32_PPCF128;
381  } else if (OpVT == MVT::i64) {
382    if (RetVT == MVT::f32)
383      return SINTTOFP_I64_F32;
384    else if (RetVT == MVT::f64)
385      return SINTTOFP_I64_F64;
386    else if (RetVT == MVT::f80)
387      return SINTTOFP_I64_F80;
388    else if (RetVT == MVT::ppcf128)
389      return SINTTOFP_I64_PPCF128;
390  } else if (OpVT == MVT::i128) {
391    if (RetVT == MVT::f32)
392      return SINTTOFP_I128_F32;
393    else if (RetVT == MVT::f64)
394      return SINTTOFP_I128_F64;
395    else if (RetVT == MVT::f80)
396      return SINTTOFP_I128_F80;
397    else if (RetVT == MVT::ppcf128)
398      return SINTTOFP_I128_PPCF128;
399  }
400  return UNKNOWN_LIBCALL;
401}
402
403/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
404/// UNKNOWN_LIBCALL if there is none.
405RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
406  if (OpVT == MVT::i32) {
407    if (RetVT == MVT::f32)
408      return UINTTOFP_I32_F32;
409    else if (RetVT == MVT::f64)
410      return UINTTOFP_I32_F64;
411    else if (RetVT == MVT::f80)
412      return UINTTOFP_I32_F80;
413    else if (RetVT == MVT::ppcf128)
414      return UINTTOFP_I32_PPCF128;
415  } else if (OpVT == MVT::i64) {
416    if (RetVT == MVT::f32)
417      return UINTTOFP_I64_F32;
418    else if (RetVT == MVT::f64)
419      return UINTTOFP_I64_F64;
420    else if (RetVT == MVT::f80)
421      return UINTTOFP_I64_F80;
422    else if (RetVT == MVT::ppcf128)
423      return UINTTOFP_I64_PPCF128;
424  } else if (OpVT == MVT::i128) {
425    if (RetVT == MVT::f32)
426      return UINTTOFP_I128_F32;
427    else if (RetVT == MVT::f64)
428      return UINTTOFP_I128_F64;
429    else if (RetVT == MVT::f80)
430      return UINTTOFP_I128_F80;
431    else if (RetVT == MVT::ppcf128)
432      return UINTTOFP_I128_PPCF128;
433  }
434  return UNKNOWN_LIBCALL;
435}
436
437/// InitCmpLibcallCCs - Set default comparison libcall CC.
438///
439static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
440  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
441  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
442  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
443  CCs[RTLIB::UNE_F32] = ISD::SETNE;
444  CCs[RTLIB::UNE_F64] = ISD::SETNE;
445  CCs[RTLIB::OGE_F32] = ISD::SETGE;
446  CCs[RTLIB::OGE_F64] = ISD::SETGE;
447  CCs[RTLIB::OLT_F32] = ISD::SETLT;
448  CCs[RTLIB::OLT_F64] = ISD::SETLT;
449  CCs[RTLIB::OLE_F32] = ISD::SETLE;
450  CCs[RTLIB::OLE_F64] = ISD::SETLE;
451  CCs[RTLIB::OGT_F32] = ISD::SETGT;
452  CCs[RTLIB::OGT_F64] = ISD::SETGT;
453  CCs[RTLIB::UO_F32] = ISD::SETNE;
454  CCs[RTLIB::UO_F64] = ISD::SETNE;
455  CCs[RTLIB::O_F32] = ISD::SETEQ;
456  CCs[RTLIB::O_F64] = ISD::SETEQ;
457}
458
459/// NOTE: The constructor takes ownership of TLOF.
460TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
461  : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
462  // All operations default to being supported.
463  memset(OpActions, 0, sizeof(OpActions));
464  memset(LoadExtActions, 0, sizeof(LoadExtActions));
465  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
466  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
467  memset(ConvertActions, 0, sizeof(ConvertActions));
468  memset(CondCodeActions, 0, sizeof(CondCodeActions));
469
470  // Set default actions for various operations.
471  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
472    // Default all indexed load / store to expand.
473    for (unsigned IM = (unsigned)ISD::PRE_INC;
474         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
475      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
476      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
477    }
478
479    // These operations default to expand.
480    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
481    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
482  }
483
484  // Most targets ignore the @llvm.prefetch intrinsic.
485  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
486
487  // ConstantFP nodes default to expand.  Targets can either change this to
488  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
489  // to optimize expansions for certain constants.
490  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
491  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
492  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
493
494  // These library functions default to expand.
495  setOperationAction(ISD::FLOG , MVT::f64, Expand);
496  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
497  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
498  setOperationAction(ISD::FEXP , MVT::f64, Expand);
499  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
500  setOperationAction(ISD::FLOG , MVT::f32, Expand);
501  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
502  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
503  setOperationAction(ISD::FEXP , MVT::f32, Expand);
504  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
505
506  // Default ISD::TRAP to expand (which turns it into abort).
507  setOperationAction(ISD::TRAP, MVT::Other, Expand);
508
509  IsLittleEndian = TD->isLittleEndian();
510  UsesGlobalOffsetTable = false;
511  ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
512  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
513  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
514  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
515  benefitFromCodePlacementOpt = false;
516  UseUnderscoreSetJmp = false;
517  UseUnderscoreLongJmp = false;
518  SelectIsExpensive = false;
519  IntDivIsCheap = false;
520  Pow2DivIsCheap = false;
521  StackPointerRegisterToSaveRestore = 0;
522  ExceptionPointerRegister = 0;
523  ExceptionSelectorRegister = 0;
524  BooleanContents = UndefinedBooleanContent;
525  SchedPreferenceInfo = SchedulingForLatency;
526  JumpBufSize = 0;
527  JumpBufAlignment = 0;
528  IfCvtBlockSizeLimit = 2;
529  IfCvtDupBlockSizeLimit = 0;
530  PrefLoopAlignment = 0;
531
532  InitLibcallNames(LibcallRoutineNames);
533  InitCmpLibcallCCs(CmpLibcallCCs);
534  InitLibcallCallingConvs(LibcallCallingConvs);
535}
536
537TargetLowering::~TargetLowering() {
538  delete &TLOF;
539}
540
541static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
542                                       unsigned &NumIntermediates,
543                                       EVT &RegisterVT,
544                                       TargetLowering* TLI) {
545  // Figure out the right, legal destination reg to copy into.
546  unsigned NumElts = VT.getVectorNumElements();
547  MVT EltTy = VT.getVectorElementType();
548
549  unsigned NumVectorRegs = 1;
550
551  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
552  // could break down into LHS/RHS like LegalizeDAG does.
553  if (!isPowerOf2_32(NumElts)) {
554    NumVectorRegs = NumElts;
555    NumElts = 1;
556  }
557
558  // Divide the input until we get to a supported size.  This will always
559  // end with a scalar if the target doesn't support vectors.
560  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
561    NumElts >>= 1;
562    NumVectorRegs <<= 1;
563  }
564
565  NumIntermediates = NumVectorRegs;
566
567  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
568  if (!TLI->isTypeLegal(NewVT))
569    NewVT = EltTy;
570  IntermediateVT = NewVT;
571
572  EVT DestVT = TLI->getRegisterType(NewVT);
573  RegisterVT = DestVT;
574  if (EVT(DestVT).bitsLT(NewVT)) {
575    // Value is expanded, e.g. i64 -> i16.
576    return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
577  } else {
578    // Otherwise, promotion or legal types use the same number of registers as
579    // the vector decimated to the appropriate level.
580    return NumVectorRegs;
581  }
582
583  return 1;
584}
585
586/// computeRegisterProperties - Once all of the register classes are added,
587/// this allows us to compute derived properties we expose.
588void TargetLowering::computeRegisterProperties() {
589  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
590         "Too many value types for ValueTypeActions to hold!");
591
592  // Everything defaults to needing one register.
593  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
594    NumRegistersForVT[i] = 1;
595    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
596  }
597  // ...except isVoid, which doesn't need any registers.
598  NumRegistersForVT[MVT::isVoid] = 0;
599
600  // Find the largest integer register class.
601  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
602  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
603    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
604
605  // Every integer value type larger than this largest register takes twice as
606  // many registers to represent as the previous ValueType.
607  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
608    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
609    if (!ExpandedVT.isInteger())
610      break;
611    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
612    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
613    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
614    ValueTypeActions.setTypeAction(ExpandedVT, Expand);
615  }
616
617  // Inspect all of the ValueType's smaller than the largest integer
618  // register to see which ones need promotion.
619  unsigned LegalIntReg = LargestIntReg;
620  for (unsigned IntReg = LargestIntReg - 1;
621       IntReg >= (unsigned)MVT::i1; --IntReg) {
622    EVT IVT = (MVT::SimpleValueType)IntReg;
623    if (isTypeLegal(IVT)) {
624      LegalIntReg = IntReg;
625    } else {
626      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
627        (MVT::SimpleValueType)LegalIntReg;
628      ValueTypeActions.setTypeAction(IVT, Promote);
629    }
630  }
631
632  // ppcf128 type is really two f64's.
633  if (!isTypeLegal(MVT::ppcf128)) {
634    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
635    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
636    TransformToType[MVT::ppcf128] = MVT::f64;
637    ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
638  }
639
640  // Decide how to handle f64. If the target does not have native f64 support,
641  // expand it to i64 and we will be generating soft float library calls.
642  if (!isTypeLegal(MVT::f64)) {
643    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
644    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
645    TransformToType[MVT::f64] = MVT::i64;
646    ValueTypeActions.setTypeAction(MVT::f64, Expand);
647  }
648
649  // Decide how to handle f32. If the target does not have native support for
650  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
651  if (!isTypeLegal(MVT::f32)) {
652    if (isTypeLegal(MVT::f64)) {
653      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
654      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
655      TransformToType[MVT::f32] = MVT::f64;
656      ValueTypeActions.setTypeAction(MVT::f32, Promote);
657    } else {
658      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
659      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
660      TransformToType[MVT::f32] = MVT::i32;
661      ValueTypeActions.setTypeAction(MVT::f32, Expand);
662    }
663  }
664
665  // Loop over all of the vector value types to see which need transformations.
666  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
667       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
668    MVT VT = (MVT::SimpleValueType)i;
669    if (!isTypeLegal(VT)) {
670      MVT IntermediateVT;
671      EVT RegisterVT;
672      unsigned NumIntermediates;
673      NumRegistersForVT[i] =
674        getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
675                                  RegisterVT, this);
676      RegisterTypeForVT[i] = RegisterVT;
677
678      // Determine if there is a legal wider type.
679      bool IsLegalWiderType = false;
680      EVT EltVT = VT.getVectorElementType();
681      unsigned NElts = VT.getVectorNumElements();
682      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
683        EVT SVT = (MVT::SimpleValueType)nVT;
684        if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
685            SVT.getVectorNumElements() > NElts) {
686          TransformToType[i] = SVT;
687          ValueTypeActions.setTypeAction(VT, Promote);
688          IsLegalWiderType = true;
689          break;
690        }
691      }
692      if (!IsLegalWiderType) {
693        EVT NVT = VT.getPow2VectorType();
694        if (NVT == VT) {
695          // Type is already a power of 2.  The default action is to split.
696          TransformToType[i] = MVT::Other;
697          ValueTypeActions.setTypeAction(VT, Expand);
698        } else {
699          TransformToType[i] = NVT;
700          ValueTypeActions.setTypeAction(VT, Promote);
701        }
702      }
703    }
704  }
705}
706
707const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
708  return NULL;
709}
710
711
712MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
713  return PointerTy.SimpleTy;
714}
715
716MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
717  return MVT::i32; // return the default value
718}
719
720/// getVectorTypeBreakdown - Vector types are broken down into some number of
721/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
722/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
723/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
724///
725/// This method returns the number of registers needed, and the VT for each
726/// register.  It also returns the VT and quantity of the intermediate values
727/// before they are promoted/expanded.
728///
729unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
730                                                EVT &IntermediateVT,
731                                                unsigned &NumIntermediates,
732                                                EVT &RegisterVT) const {
733  // Figure out the right, legal destination reg to copy into.
734  unsigned NumElts = VT.getVectorNumElements();
735  EVT EltTy = VT.getVectorElementType();
736
737  unsigned NumVectorRegs = 1;
738
739  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
740  // could break down into LHS/RHS like LegalizeDAG does.
741  if (!isPowerOf2_32(NumElts)) {
742    NumVectorRegs = NumElts;
743    NumElts = 1;
744  }
745
746  // Divide the input until we get to a supported size.  This will always
747  // end with a scalar if the target doesn't support vectors.
748  while (NumElts > 1 && !isTypeLegal(
749                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
750    NumElts >>= 1;
751    NumVectorRegs <<= 1;
752  }
753
754  NumIntermediates = NumVectorRegs;
755
756  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
757  if (!isTypeLegal(NewVT))
758    NewVT = EltTy;
759  IntermediateVT = NewVT;
760
761  EVT DestVT = getRegisterType(Context, NewVT);
762  RegisterVT = DestVT;
763  if (DestVT.bitsLT(NewVT)) {
764    // Value is expanded, e.g. i64 -> i16.
765    return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
766  } else {
767    // Otherwise, promotion or legal types use the same number of registers as
768    // the vector decimated to the appropriate level.
769    return NumVectorRegs;
770  }
771
772  return 1;
773}
774
775/// getWidenVectorType: given a vector type, returns the type to widen to
776/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
777/// If there is no vector type that we want to widen to, returns MVT::Other
778/// When and where to widen is target dependent based on the cost of
779/// scalarizing vs using the wider vector type.
780EVT TargetLowering::getWidenVectorType(EVT VT) const {
781  assert(VT.isVector());
782  if (isTypeLegal(VT))
783    return VT;
784
785  // Default is not to widen until moved to LegalizeTypes
786  return MVT::Other;
787}
788
789/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
790/// function arguments in the caller parameter area.  This is the actual
791/// alignment, not its logarithm.
792unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
793  return TD->getCallFrameTypeAlignment(Ty);
794}
795
796SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
797                                                 SelectionDAG &DAG) const {
798  if (usesGlobalOffsetTable())
799    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
800  return Table;
801}
802
803bool
804TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
805  // Assume that everything is safe in static mode.
806  if (getTargetMachine().getRelocationModel() == Reloc::Static)
807    return true;
808
809  // In dynamic-no-pic mode, assume that known defined values are safe.
810  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
811      GA &&
812      !GA->getGlobal()->isDeclaration() &&
813      !GA->getGlobal()->isWeakForLinker())
814    return true;
815
816  // Otherwise assume nothing is safe.
817  return false;
818}
819
820//===----------------------------------------------------------------------===//
821//  Optimization Methods
822//===----------------------------------------------------------------------===//
823
824/// ShrinkDemandedConstant - Check to see if the specified operand of the
825/// specified instruction is a constant integer.  If so, check to see if there
826/// are any bits set in the constant that are not demanded.  If so, shrink the
827/// constant and return true.
828bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
829                                                        const APInt &Demanded) {
830  DebugLoc dl = Op.getDebugLoc();
831
832  // FIXME: ISD::SELECT, ISD::SELECT_CC
833  switch (Op.getOpcode()) {
834  default: break;
835  case ISD::XOR:
836  case ISD::AND:
837  case ISD::OR: {
838    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
839    if (!C) return false;
840
841    if (Op.getOpcode() == ISD::XOR &&
842        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
843      return false;
844
845    // if we can expand it to have all bits set, do it
846    if (C->getAPIntValue().intersects(~Demanded)) {
847      EVT VT = Op.getValueType();
848      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
849                                DAG.getConstant(Demanded &
850                                                C->getAPIntValue(),
851                                                VT));
852      return CombineTo(Op, New);
853    }
854
855    break;
856  }
857  }
858
859  return false;
860}
861
862/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
863/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
864/// cast, but it could be generalized for targets with other types of
865/// implicit widening casts.
866bool
867TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
868                                                    unsigned BitWidth,
869                                                    const APInt &Demanded,
870                                                    DebugLoc dl) {
871  assert(Op.getNumOperands() == 2 &&
872         "ShrinkDemandedOp only supports binary operators!");
873  assert(Op.getNode()->getNumValues() == 1 &&
874         "ShrinkDemandedOp only supports nodes with one result!");
875
876  // Don't do this if the node has another user, which may require the
877  // full value.
878  if (!Op.getNode()->hasOneUse())
879    return false;
880
881  // Search for the smallest integer type with free casts to and from
882  // Op's type. For expedience, just check power-of-2 integer types.
883  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
884  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
885  if (!isPowerOf2_32(SmallVTBits))
886    SmallVTBits = NextPowerOf2(SmallVTBits);
887  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
888    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
889    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
890        TLI.isZExtFree(SmallVT, Op.getValueType())) {
891      // We found a type with free casts.
892      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
893                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
894                                          Op.getNode()->getOperand(0)),
895                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
896                                          Op.getNode()->getOperand(1)));
897      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
898      return CombineTo(Op, Z);
899    }
900  }
901  return false;
902}
903
904/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
905/// DemandedMask bits of the result of Op are ever used downstream.  If we can
906/// use this information to simplify Op, create a new simplified DAG node and
907/// return true, returning the original and new nodes in Old and New. Otherwise,
908/// analyze the expression and return a mask of KnownOne and KnownZero bits for
909/// the expression (used to simplify the caller).  The KnownZero/One bits may
910/// only be accurate for those bits in the DemandedMask.
911bool TargetLowering::SimplifyDemandedBits(SDValue Op,
912                                          const APInt &DemandedMask,
913                                          APInt &KnownZero,
914                                          APInt &KnownOne,
915                                          TargetLoweringOpt &TLO,
916                                          unsigned Depth) const {
917  unsigned BitWidth = DemandedMask.getBitWidth();
918  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
919         "Mask size mismatches value type size!");
920  APInt NewMask = DemandedMask;
921  DebugLoc dl = Op.getDebugLoc();
922
923  // Don't know anything.
924  KnownZero = KnownOne = APInt(BitWidth, 0);
925
926  // Other users may use these bits.
927  if (!Op.getNode()->hasOneUse()) {
928    if (Depth != 0) {
929      // If not at the root, Just compute the KnownZero/KnownOne bits to
930      // simplify things downstream.
931      TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
932      return false;
933    }
934    // If this is the root being simplified, allow it to have multiple uses,
935    // just set the NewMask to all bits.
936    NewMask = APInt::getAllOnesValue(BitWidth);
937  } else if (DemandedMask == 0) {
938    // Not demanding any bits from Op.
939    if (Op.getOpcode() != ISD::UNDEF)
940      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
941    return false;
942  } else if (Depth == 6) {        // Limit search depth.
943    return false;
944  }
945
946  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
947  switch (Op.getOpcode()) {
948  case ISD::Constant:
949    // We know all of the bits for a constant!
950    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
951    KnownZero = ~KnownOne & NewMask;
952    return false;   // Don't fall through, will infinitely loop.
953  case ISD::AND:
954    // If the RHS is a constant, check to see if the LHS would be zero without
955    // using the bits from the RHS.  Below, we use knowledge about the RHS to
956    // simplify the LHS, here we're using information from the LHS to simplify
957    // the RHS.
958    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
959      APInt LHSZero, LHSOne;
960      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
961                                LHSZero, LHSOne, Depth+1);
962      // If the LHS already has zeros where RHSC does, this and is dead.
963      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
964        return TLO.CombineTo(Op, Op.getOperand(0));
965      // If any of the set bits in the RHS are known zero on the LHS, shrink
966      // the constant.
967      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
968        return true;
969    }
970
971    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
972                             KnownOne, TLO, Depth+1))
973      return true;
974    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
975    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
976                             KnownZero2, KnownOne2, TLO, Depth+1))
977      return true;
978    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
979
980    // If all of the demanded bits are known one on one side, return the other.
981    // These bits cannot contribute to the result of the 'and'.
982    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
983      return TLO.CombineTo(Op, Op.getOperand(0));
984    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
985      return TLO.CombineTo(Op, Op.getOperand(1));
986    // If all of the demanded bits in the inputs are known zeros, return zero.
987    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
988      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
989    // If the RHS is a constant, see if we can simplify it.
990    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
991      return true;
992    // If the operation can be done in a smaller type, do so.
993    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
994      return true;
995
996    // Output known-1 bits are only known if set in both the LHS & RHS.
997    KnownOne &= KnownOne2;
998    // Output known-0 are known to be clear if zero in either the LHS | RHS.
999    KnownZero |= KnownZero2;
1000    break;
1001  case ISD::OR:
1002    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1003                             KnownOne, TLO, Depth+1))
1004      return true;
1005    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1006    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1007                             KnownZero2, KnownOne2, TLO, Depth+1))
1008      return true;
1009    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1010
1011    // If all of the demanded bits are known zero on one side, return the other.
1012    // These bits cannot contribute to the result of the 'or'.
1013    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1014      return TLO.CombineTo(Op, Op.getOperand(0));
1015    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1016      return TLO.CombineTo(Op, Op.getOperand(1));
1017    // If all of the potentially set bits on one side are known to be set on
1018    // the other side, just use the 'other' side.
1019    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1020      return TLO.CombineTo(Op, Op.getOperand(0));
1021    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1022      return TLO.CombineTo(Op, Op.getOperand(1));
1023    // If the RHS is a constant, see if we can simplify it.
1024    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1025      return true;
1026    // If the operation can be done in a smaller type, do so.
1027    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1028      return true;
1029
1030    // Output known-0 bits are only known if clear in both the LHS & RHS.
1031    KnownZero &= KnownZero2;
1032    // Output known-1 are known to be set if set in either the LHS | RHS.
1033    KnownOne |= KnownOne2;
1034    break;
1035  case ISD::XOR:
1036    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1037                             KnownOne, TLO, Depth+1))
1038      return true;
1039    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1040    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1041                             KnownOne2, TLO, Depth+1))
1042      return true;
1043    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1044
1045    // If all of the demanded bits are known zero on one side, return the other.
1046    // These bits cannot contribute to the result of the 'xor'.
1047    if ((KnownZero & NewMask) == NewMask)
1048      return TLO.CombineTo(Op, Op.getOperand(0));
1049    if ((KnownZero2 & NewMask) == NewMask)
1050      return TLO.CombineTo(Op, Op.getOperand(1));
1051    // If the operation can be done in a smaller type, do so.
1052    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1053      return true;
1054
1055    // If all of the unknown bits are known to be zero on one side or the other
1056    // (but not both) turn this into an *inclusive* or.
1057    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1058    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1059      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1060                                               Op.getOperand(0),
1061                                               Op.getOperand(1)));
1062
1063    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1064    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1065    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1066    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1067
1068    // If all of the demanded bits on one side are known, and all of the set
1069    // bits on that side are also known to be set on the other side, turn this
1070    // into an AND, as we know the bits will be cleared.
1071    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1072    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1073      if ((KnownOne & KnownOne2) == KnownOne) {
1074        EVT VT = Op.getValueType();
1075        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1076        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1077                                                 Op.getOperand(0), ANDC));
1078      }
1079    }
1080
1081    // If the RHS is a constant, see if we can simplify it.
1082    // for XOR, we prefer to force bits to 1 if they will make a -1.
1083    // if we can't force bits, try to shrink constant
1084    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1085      APInt Expanded = C->getAPIntValue() | (~NewMask);
1086      // if we can expand it to have all bits set, do it
1087      if (Expanded.isAllOnesValue()) {
1088        if (Expanded != C->getAPIntValue()) {
1089          EVT VT = Op.getValueType();
1090          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1091                                          TLO.DAG.getConstant(Expanded, VT));
1092          return TLO.CombineTo(Op, New);
1093        }
1094        // if it already has all the bits set, nothing to change
1095        // but don't shrink either!
1096      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1097        return true;
1098      }
1099    }
1100
1101    KnownZero = KnownZeroOut;
1102    KnownOne  = KnownOneOut;
1103    break;
1104  case ISD::SELECT:
1105    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1106                             KnownOne, TLO, Depth+1))
1107      return true;
1108    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1109                             KnownOne2, TLO, Depth+1))
1110      return true;
1111    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1112    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1113
1114    // If the operands are constants, see if we can simplify them.
1115    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1116      return true;
1117
1118    // Only known if known in both the LHS and RHS.
1119    KnownOne &= KnownOne2;
1120    KnownZero &= KnownZero2;
1121    break;
1122  case ISD::SELECT_CC:
1123    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1124                             KnownOne, TLO, Depth+1))
1125      return true;
1126    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1127                             KnownOne2, TLO, Depth+1))
1128      return true;
1129    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1130    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1131
1132    // If the operands are constants, see if we can simplify them.
1133    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1134      return true;
1135
1136    // Only known if known in both the LHS and RHS.
1137    KnownOne &= KnownOne2;
1138    KnownZero &= KnownZero2;
1139    break;
1140  case ISD::SHL:
1141    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1142      unsigned ShAmt = SA->getZExtValue();
1143      SDValue InOp = Op.getOperand(0);
1144
1145      // If the shift count is an invalid immediate, don't do anything.
1146      if (ShAmt >= BitWidth)
1147        break;
1148
1149      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1150      // single shift.  We can do this if the bottom bits (which are shifted
1151      // out) are never demanded.
1152      if (InOp.getOpcode() == ISD::SRL &&
1153          isa<ConstantSDNode>(InOp.getOperand(1))) {
1154        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1155          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1156          unsigned Opc = ISD::SHL;
1157          int Diff = ShAmt-C1;
1158          if (Diff < 0) {
1159            Diff = -Diff;
1160            Opc = ISD::SRL;
1161          }
1162
1163          SDValue NewSA =
1164            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1165          EVT VT = Op.getValueType();
1166          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1167                                                   InOp.getOperand(0), NewSA));
1168        }
1169      }
1170
1171      if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1172                               KnownZero, KnownOne, TLO, Depth+1))
1173        return true;
1174      KnownZero <<= SA->getZExtValue();
1175      KnownOne  <<= SA->getZExtValue();
1176      // low bits known zero.
1177      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1178    }
1179    break;
1180  case ISD::SRL:
1181    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1182      EVT VT = Op.getValueType();
1183      unsigned ShAmt = SA->getZExtValue();
1184      unsigned VTSize = VT.getSizeInBits();
1185      SDValue InOp = Op.getOperand(0);
1186
1187      // If the shift count is an invalid immediate, don't do anything.
1188      if (ShAmt >= BitWidth)
1189        break;
1190
1191      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1192      // single shift.  We can do this if the top bits (which are shifted out)
1193      // are never demanded.
1194      if (InOp.getOpcode() == ISD::SHL &&
1195          isa<ConstantSDNode>(InOp.getOperand(1))) {
1196        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1197          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1198          unsigned Opc = ISD::SRL;
1199          int Diff = ShAmt-C1;
1200          if (Diff < 0) {
1201            Diff = -Diff;
1202            Opc = ISD::SHL;
1203          }
1204
1205          SDValue NewSA =
1206            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1207          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1208                                                   InOp.getOperand(0), NewSA));
1209        }
1210      }
1211
1212      // Compute the new bits that are at the top now.
1213      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1214                               KnownZero, KnownOne, TLO, Depth+1))
1215        return true;
1216      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1217      KnownZero = KnownZero.lshr(ShAmt);
1218      KnownOne  = KnownOne.lshr(ShAmt);
1219
1220      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1221      KnownZero |= HighBits;  // High bits known zero.
1222    }
1223    break;
1224  case ISD::SRA:
1225    // If this is an arithmetic shift right and only the low-bit is set, we can
1226    // always convert this into a logical shr, even if the shift amount is
1227    // variable.  The low bit of the shift cannot be an input sign bit unless
1228    // the shift amount is >= the size of the datatype, which is undefined.
1229    if (DemandedMask == 1)
1230      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1231                                               Op.getOperand(0), Op.getOperand(1)));
1232
1233    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1234      EVT VT = Op.getValueType();
1235      unsigned ShAmt = SA->getZExtValue();
1236
1237      // If the shift count is an invalid immediate, don't do anything.
1238      if (ShAmt >= BitWidth)
1239        break;
1240
1241      APInt InDemandedMask = (NewMask << ShAmt);
1242
1243      // If any of the demanded bits are produced by the sign extension, we also
1244      // demand the input sign bit.
1245      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1246      if (HighBits.intersects(NewMask))
1247        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1248
1249      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1250                               KnownZero, KnownOne, TLO, Depth+1))
1251        return true;
1252      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1253      KnownZero = KnownZero.lshr(ShAmt);
1254      KnownOne  = KnownOne.lshr(ShAmt);
1255
1256      // Handle the sign bit, adjusted to where it is now in the mask.
1257      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1258
1259      // If the input sign bit is known to be zero, or if none of the top bits
1260      // are demanded, turn this into an unsigned shift right.
1261      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1262        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1263                                                 Op.getOperand(0),
1264                                                 Op.getOperand(1)));
1265      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1266        KnownOne |= HighBits;
1267      }
1268    }
1269    break;
1270  case ISD::SIGN_EXTEND_INREG: {
1271    EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1272
1273    // Sign extension.  Compute the demanded bits in the result that are not
1274    // present in the input.
1275    APInt NewBits = APInt::getHighBitsSet(BitWidth,
1276                                          BitWidth - EVT.getSizeInBits()) &
1277                    NewMask;
1278
1279    // If none of the extended bits are demanded, eliminate the sextinreg.
1280    if (NewBits == 0)
1281      return TLO.CombineTo(Op, Op.getOperand(0));
1282
1283    APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1284    InSignBit.zext(BitWidth);
1285    APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1286                                                   EVT.getSizeInBits()) &
1287                              NewMask;
1288
1289    // Since the sign extended bits are demanded, we know that the sign
1290    // bit is demanded.
1291    InputDemandedBits |= InSignBit;
1292
1293    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1294                             KnownZero, KnownOne, TLO, Depth+1))
1295      return true;
1296    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1297
1298    // If the sign bit of the input is known set or clear, then we know the
1299    // top bits of the result.
1300
1301    // If the input sign bit is known zero, convert this into a zero extension.
1302    if (KnownZero.intersects(InSignBit))
1303      return TLO.CombineTo(Op,
1304                           TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1305
1306    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1307      KnownOne |= NewBits;
1308      KnownZero &= ~NewBits;
1309    } else {                       // Input sign bit unknown
1310      KnownZero &= ~NewBits;
1311      KnownOne &= ~NewBits;
1312    }
1313    break;
1314  }
1315  case ISD::ZERO_EXTEND: {
1316    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1317    APInt InMask = NewMask;
1318    InMask.trunc(OperandBitWidth);
1319
1320    // If none of the top bits are demanded, convert this into an any_extend.
1321    APInt NewBits =
1322      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1323    if (!NewBits.intersects(NewMask))
1324      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1325                                               Op.getValueType(),
1326                                               Op.getOperand(0)));
1327
1328    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1329                             KnownZero, KnownOne, TLO, Depth+1))
1330      return true;
1331    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1332    KnownZero.zext(BitWidth);
1333    KnownOne.zext(BitWidth);
1334    KnownZero |= NewBits;
1335    break;
1336  }
1337  case ISD::SIGN_EXTEND: {
1338    EVT InVT = Op.getOperand(0).getValueType();
1339    unsigned InBits = InVT.getSizeInBits();
1340    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1341    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1342    APInt NewBits   = ~InMask & NewMask;
1343
1344    // If none of the top bits are demanded, convert this into an any_extend.
1345    if (NewBits == 0)
1346      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1347                                              Op.getValueType(),
1348                                              Op.getOperand(0)));
1349
1350    // Since some of the sign extended bits are demanded, we know that the sign
1351    // bit is demanded.
1352    APInt InDemandedBits = InMask & NewMask;
1353    InDemandedBits |= InSignBit;
1354    InDemandedBits.trunc(InBits);
1355
1356    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1357                             KnownOne, TLO, Depth+1))
1358      return true;
1359    KnownZero.zext(BitWidth);
1360    KnownOne.zext(BitWidth);
1361
1362    // If the sign bit is known zero, convert this to a zero extend.
1363    if (KnownZero.intersects(InSignBit))
1364      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1365                                               Op.getValueType(),
1366                                               Op.getOperand(0)));
1367
1368    // If the sign bit is known one, the top bits match.
1369    if (KnownOne.intersects(InSignBit)) {
1370      KnownOne  |= NewBits;
1371      KnownZero &= ~NewBits;
1372    } else {   // Otherwise, top bits aren't known.
1373      KnownOne  &= ~NewBits;
1374      KnownZero &= ~NewBits;
1375    }
1376    break;
1377  }
1378  case ISD::ANY_EXTEND: {
1379    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1380    APInt InMask = NewMask;
1381    InMask.trunc(OperandBitWidth);
1382    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1383                             KnownZero, KnownOne, TLO, Depth+1))
1384      return true;
1385    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1386    KnownZero.zext(BitWidth);
1387    KnownOne.zext(BitWidth);
1388    break;
1389  }
1390  case ISD::TRUNCATE: {
1391    // Simplify the input, using demanded bit information, and compute the known
1392    // zero/one bits live out.
1393    APInt TruncMask = NewMask;
1394    TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1395    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1396                             KnownZero, KnownOne, TLO, Depth+1))
1397      return true;
1398    KnownZero.trunc(BitWidth);
1399    KnownOne.trunc(BitWidth);
1400
1401    // If the input is only used by this truncate, see if we can shrink it based
1402    // on the known demanded bits.
1403    if (Op.getOperand(0).getNode()->hasOneUse()) {
1404      SDValue In = Op.getOperand(0);
1405      unsigned InBitWidth = In.getValueSizeInBits();
1406      switch (In.getOpcode()) {
1407      default: break;
1408      case ISD::SRL:
1409        // Shrink SRL by a constant if none of the high bits shifted in are
1410        // demanded.
1411        if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1412          APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1413                                                 InBitWidth - BitWidth);
1414          HighBits = HighBits.lshr(ShAmt->getZExtValue());
1415          HighBits.trunc(BitWidth);
1416
1417          if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1418            // None of the shifted in bits are needed.  Add a truncate of the
1419            // shift input, then shift it.
1420            SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1421                                                 Op.getValueType(),
1422                                                 In.getOperand(0));
1423            return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1424                                                     Op.getValueType(),
1425                                                     NewTrunc,
1426                                                     In.getOperand(1)));
1427          }
1428        }
1429        break;
1430      }
1431    }
1432
1433    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1434    break;
1435  }
1436  case ISD::AssertZext: {
1437    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1438    APInt InMask = APInt::getLowBitsSet(BitWidth,
1439                                        VT.getSizeInBits());
1440    if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1441                             KnownZero, KnownOne, TLO, Depth+1))
1442      return true;
1443    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1444    KnownZero |= ~InMask & NewMask;
1445    break;
1446  }
1447  case ISD::BIT_CONVERT:
1448#if 0
1449    // If this is an FP->Int bitcast and if the sign bit is the only thing that
1450    // is demanded, turn this into a FGETSIGN.
1451    if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1452        MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1453        !MVT::isVector(Op.getOperand(0).getValueType())) {
1454      // Only do this xform if FGETSIGN is valid or if before legalize.
1455      if (!TLO.AfterLegalize ||
1456          isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1457        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1458        // place.  We expect the SHL to be eliminated by other optimizations.
1459        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1460                                         Op.getOperand(0));
1461        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1462        SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1463        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1464                                                 Sign, ShAmt));
1465      }
1466    }
1467#endif
1468    break;
1469  case ISD::ADD:
1470  case ISD::MUL:
1471  case ISD::SUB: {
1472    // Add, Sub, and Mul don't demand any bits in positions beyond that
1473    // of the highest bit demanded of them.
1474    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1475                                        BitWidth - NewMask.countLeadingZeros());
1476    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1477                             KnownOne2, TLO, Depth+1))
1478      return true;
1479    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1480                             KnownOne2, TLO, Depth+1))
1481      return true;
1482    // See if the operation should be performed at a smaller bit width.
1483    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1484      return true;
1485  }
1486  // FALL THROUGH
1487  default:
1488    // Just use ComputeMaskedBits to compute output bits.
1489    TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1490    break;
1491  }
1492
1493  // If we know the value of all of the demanded bits, return this as a
1494  // constant.
1495  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1496    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1497
1498  return false;
1499}
1500
1501/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1502/// in Mask are known to be either zero or one and return them in the
1503/// KnownZero/KnownOne bitsets.
1504void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1505                                                    const APInt &Mask,
1506                                                    APInt &KnownZero,
1507                                                    APInt &KnownOne,
1508                                                    const SelectionDAG &DAG,
1509                                                    unsigned Depth) const {
1510  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1511          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1512          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1513          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1514         "Should use MaskedValueIsZero if you don't know whether Op"
1515         " is a target node!");
1516  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1517}
1518
1519/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1520/// targets that want to expose additional information about sign bits to the
1521/// DAG Combiner.
1522unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1523                                                         unsigned Depth) const {
1524  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1525          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1526          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1527          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1528         "Should use ComputeNumSignBits if you don't know whether Op"
1529         " is a target node!");
1530  return 1;
1531}
1532
1533/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1534/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1535/// determine which bit is set.
1536///
1537static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1538  // A left-shift of a constant one will have exactly one bit set, because
1539  // shifting the bit off the end is undefined.
1540  if (Val.getOpcode() == ISD::SHL)
1541    if (ConstantSDNode *C =
1542         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1543      if (C->getAPIntValue() == 1)
1544        return true;
1545
1546  // Similarly, a right-shift of a constant sign-bit will have exactly
1547  // one bit set.
1548  if (Val.getOpcode() == ISD::SRL)
1549    if (ConstantSDNode *C =
1550         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1551      if (C->getAPIntValue().isSignBit())
1552        return true;
1553
1554  // More could be done here, though the above checks are enough
1555  // to handle some common cases.
1556
1557  // Fall back to ComputeMaskedBits to catch other known cases.
1558  EVT OpVT = Val.getValueType();
1559  unsigned BitWidth = OpVT.getSizeInBits();
1560  APInt Mask = APInt::getAllOnesValue(BitWidth);
1561  APInt KnownZero, KnownOne;
1562  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1563  return (KnownZero.countPopulation() == BitWidth - 1) &&
1564         (KnownOne.countPopulation() == 1);
1565}
1566
1567/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1568/// and cc. If it is unable to simplify it, return a null SDValue.
1569SDValue
1570TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1571                              ISD::CondCode Cond, bool foldBooleans,
1572                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1573  SelectionDAG &DAG = DCI.DAG;
1574  LLVMContext &Context = *DAG.getContext();
1575
1576  // These setcc operations always fold.
1577  switch (Cond) {
1578  default: break;
1579  case ISD::SETFALSE:
1580  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1581  case ISD::SETTRUE:
1582  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1583  }
1584
1585  if (isa<ConstantSDNode>(N0.getNode())) {
1586    // Ensure that the constant occurs on the RHS, and fold constant
1587    // comparisons.
1588    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1589  }
1590
1591  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1592    const APInt &C1 = N1C->getAPIntValue();
1593
1594    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1595    // equality comparison, then we're just comparing whether X itself is
1596    // zero.
1597    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1598        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1599        N0.getOperand(1).getOpcode() == ISD::Constant) {
1600      unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1601      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1602          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1603        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1604          // (srl (ctlz x), 5) == 0  -> X != 0
1605          // (srl (ctlz x), 5) != 1  -> X != 0
1606          Cond = ISD::SETNE;
1607        } else {
1608          // (srl (ctlz x), 5) != 0  -> X == 0
1609          // (srl (ctlz x), 5) == 1  -> X == 0
1610          Cond = ISD::SETEQ;
1611        }
1612        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1613        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1614                            Zero, Cond);
1615      }
1616    }
1617
1618    // If the LHS is '(and load, const)', the RHS is 0,
1619    // the test is for equality or unsigned, and all 1 bits of the const are
1620    // in the same partial word, see if we can shorten the load.
1621    if (DCI.isBeforeLegalize() &&
1622        N0.getOpcode() == ISD::AND && C1 == 0 &&
1623        N0.getNode()->hasOneUse() &&
1624        isa<LoadSDNode>(N0.getOperand(0)) &&
1625        N0.getOperand(0).getNode()->hasOneUse() &&
1626        isa<ConstantSDNode>(N0.getOperand(1))) {
1627      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1628      uint64_t bestMask = 0;
1629      unsigned bestWidth = 0, bestOffset = 0;
1630      if (!Lod->isVolatile() && Lod->isUnindexed() &&
1631          // FIXME: This uses getZExtValue() below so it only works on i64 and
1632          // below.
1633          N0.getValueType().getSizeInBits() <= 64) {
1634        unsigned origWidth = N0.getValueType().getSizeInBits();
1635        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1636        // 8 bits, but have to be careful...
1637        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1638          origWidth = Lod->getMemoryVT().getSizeInBits();
1639        uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1640        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1641          uint64_t newMask = (1ULL << width) - 1;
1642          for (unsigned offset=0; offset<origWidth/width; offset++) {
1643            if ((newMask & Mask) == Mask) {
1644              if (!TD->isLittleEndian())
1645                bestOffset = (origWidth/width - offset - 1) * (width/8);
1646              else
1647                bestOffset = (uint64_t)offset * (width/8);
1648              bestMask = Mask >> (offset * (width/8) * 8);
1649              bestWidth = width;
1650              break;
1651            }
1652            newMask = newMask << width;
1653          }
1654        }
1655      }
1656      if (bestWidth) {
1657        EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1658        if (newVT.isRound()) {
1659          EVT PtrType = Lod->getOperand(1).getValueType();
1660          SDValue Ptr = Lod->getBasePtr();
1661          if (bestOffset != 0)
1662            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1663                              DAG.getConstant(bestOffset, PtrType));
1664          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1665          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1666                                        Lod->getSrcValue(),
1667                                        Lod->getSrcValueOffset() + bestOffset,
1668                                        false, NewAlign);
1669          return DAG.getSetCC(dl, VT,
1670                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1671                                          DAG.getConstant(bestMask, newVT)),
1672                              DAG.getConstant(0LL, newVT), Cond);
1673        }
1674      }
1675    }
1676
1677    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1678    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1679      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1680
1681      // If the comparison constant has bits in the upper part, the
1682      // zero-extended value could never match.
1683      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1684                                              C1.getBitWidth() - InSize))) {
1685        switch (Cond) {
1686        case ISD::SETUGT:
1687        case ISD::SETUGE:
1688        case ISD::SETEQ: return DAG.getConstant(0, VT);
1689        case ISD::SETULT:
1690        case ISD::SETULE:
1691        case ISD::SETNE: return DAG.getConstant(1, VT);
1692        case ISD::SETGT:
1693        case ISD::SETGE:
1694          // True if the sign bit of C1 is set.
1695          return DAG.getConstant(C1.isNegative(), VT);
1696        case ISD::SETLT:
1697        case ISD::SETLE:
1698          // True if the sign bit of C1 isn't set.
1699          return DAG.getConstant(C1.isNonNegative(), VT);
1700        default:
1701          break;
1702        }
1703      }
1704
1705      // Otherwise, we can perform the comparison with the low bits.
1706      switch (Cond) {
1707      case ISD::SETEQ:
1708      case ISD::SETNE:
1709      case ISD::SETUGT:
1710      case ISD::SETUGE:
1711      case ISD::SETULT:
1712      case ISD::SETULE: {
1713        EVT newVT = N0.getOperand(0).getValueType();
1714        if (DCI.isBeforeLegalizeOps() ||
1715            (isOperationLegal(ISD::SETCC, newVT) &&
1716              getCondCodeAction(Cond, newVT)==Legal))
1717          return DAG.getSetCC(dl, VT, N0.getOperand(0),
1718                              DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1719                              Cond);
1720        break;
1721      }
1722      default:
1723        break;   // todo, be more careful with signed comparisons
1724      }
1725    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1726                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1727      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1728      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1729      EVT ExtDstTy = N0.getValueType();
1730      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1731
1732      // If the extended part has any inconsistent bits, it cannot ever
1733      // compare equal.  In other words, they have to be all ones or all
1734      // zeros.
1735      APInt ExtBits =
1736        APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1737      if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1738        return DAG.getConstant(Cond == ISD::SETNE, VT);
1739
1740      SDValue ZextOp;
1741      EVT Op0Ty = N0.getOperand(0).getValueType();
1742      if (Op0Ty == ExtSrcTy) {
1743        ZextOp = N0.getOperand(0);
1744      } else {
1745        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1746        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1747                              DAG.getConstant(Imm, Op0Ty));
1748      }
1749      if (!DCI.isCalledByLegalizer())
1750        DCI.AddToWorklist(ZextOp.getNode());
1751      // Otherwise, make this a use of a zext.
1752      return DAG.getSetCC(dl, VT, ZextOp,
1753                          DAG.getConstant(C1 & APInt::getLowBitsSet(
1754                                                              ExtDstTyBits,
1755                                                              ExtSrcTyBits),
1756                                          ExtDstTy),
1757                          Cond);
1758    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1759                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1760
1761      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
1762      if (N0.getOpcode() == ISD::SETCC) {
1763        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1764        if (TrueWhenTrue)
1765          return N0;
1766
1767        // Invert the condition.
1768        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1769        CC = ISD::getSetCCInverse(CC,
1770                                  N0.getOperand(0).getValueType().isInteger());
1771        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1772      }
1773
1774      if ((N0.getOpcode() == ISD::XOR ||
1775            (N0.getOpcode() == ISD::AND &&
1776            N0.getOperand(0).getOpcode() == ISD::XOR &&
1777            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1778          isa<ConstantSDNode>(N0.getOperand(1)) &&
1779          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1780        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
1781        // can only do this if the top bits are known zero.
1782        unsigned BitWidth = N0.getValueSizeInBits();
1783        if (DAG.MaskedValueIsZero(N0,
1784                                  APInt::getHighBitsSet(BitWidth,
1785                                                        BitWidth-1))) {
1786          // Okay, get the un-inverted input value.
1787          SDValue Val;
1788          if (N0.getOpcode() == ISD::XOR)
1789            Val = N0.getOperand(0);
1790          else {
1791            assert(N0.getOpcode() == ISD::AND &&
1792                    N0.getOperand(0).getOpcode() == ISD::XOR);
1793            // ((X^1)&1)^1 -> X & 1
1794            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1795                              N0.getOperand(0).getOperand(0),
1796                              N0.getOperand(1));
1797          }
1798          return DAG.getSetCC(dl, VT, Val, N1,
1799                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1800        }
1801      }
1802    }
1803
1804    APInt MinVal, MaxVal;
1805    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1806    if (ISD::isSignedIntSetCC(Cond)) {
1807      MinVal = APInt::getSignedMinValue(OperandBitSize);
1808      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1809    } else {
1810      MinVal = APInt::getMinValue(OperandBitSize);
1811      MaxVal = APInt::getMaxValue(OperandBitSize);
1812    }
1813
1814    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1815    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1816      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
1817      // X >= C0 --> X > (C0-1)
1818      return DAG.getSetCC(dl, VT, N0,
1819                          DAG.getConstant(C1-1, N1.getValueType()),
1820                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1821    }
1822
1823    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1824      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
1825      // X <= C0 --> X < (C0+1)
1826      return DAG.getSetCC(dl, VT, N0,
1827                          DAG.getConstant(C1+1, N1.getValueType()),
1828                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1829    }
1830
1831    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1832      return DAG.getConstant(0, VT);      // X < MIN --> false
1833    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1834      return DAG.getConstant(1, VT);      // X >= MIN --> true
1835    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1836      return DAG.getConstant(0, VT);      // X > MAX --> false
1837    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1838      return DAG.getConstant(1, VT);      // X <= MAX --> true
1839
1840    // Canonicalize setgt X, Min --> setne X, Min
1841    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1842      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1843    // Canonicalize setlt X, Max --> setne X, Max
1844    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1845      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1846
1847    // If we have setult X, 1, turn it into seteq X, 0
1848    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1849      return DAG.getSetCC(dl, VT, N0,
1850                          DAG.getConstant(MinVal, N0.getValueType()),
1851                          ISD::SETEQ);
1852    // If we have setugt X, Max-1, turn it into seteq X, Max
1853    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1854      return DAG.getSetCC(dl, VT, N0,
1855                          DAG.getConstant(MaxVal, N0.getValueType()),
1856                          ISD::SETEQ);
1857
1858    // If we have "setcc X, C0", check to see if we can shrink the immediate
1859    // by changing cc.
1860
1861    // SETUGT X, SINTMAX  -> SETLT X, 0
1862    if (Cond == ISD::SETUGT &&
1863        C1 == APInt::getSignedMaxValue(OperandBitSize))
1864      return DAG.getSetCC(dl, VT, N0,
1865                          DAG.getConstant(0, N1.getValueType()),
1866                          ISD::SETLT);
1867
1868    // SETULT X, SINTMIN  -> SETGT X, -1
1869    if (Cond == ISD::SETULT &&
1870        C1 == APInt::getSignedMinValue(OperandBitSize)) {
1871      SDValue ConstMinusOne =
1872          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1873                          N1.getValueType());
1874      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1875    }
1876
1877    // Fold bit comparisons when we can.
1878    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1879        VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1880      if (ConstantSDNode *AndRHS =
1881                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1882        EVT ShiftTy = DCI.isBeforeLegalize() ?
1883          getPointerTy() : getShiftAmountTy();
1884        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
1885          // Perform the xform if the AND RHS is a single bit.
1886          if (isPowerOf2_64(AndRHS->getZExtValue())) {
1887            return DAG.getNode(ISD::SRL, dl, VT, N0,
1888                                DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1889                                                ShiftTy));
1890          }
1891        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1892          // (X & 8) == 8  -->  (X & 8) >> 3
1893          // Perform the xform if C1 is a single bit.
1894          if (C1.isPowerOf2()) {
1895            return DAG.getNode(ISD::SRL, dl, VT, N0,
1896                                DAG.getConstant(C1.logBase2(), ShiftTy));
1897          }
1898        }
1899      }
1900  }
1901
1902  if (isa<ConstantFPSDNode>(N0.getNode())) {
1903    // Constant fold or commute setcc.
1904    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1905    if (O.getNode()) return O;
1906  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1907    // If the RHS of an FP comparison is a constant, simplify it away in
1908    // some cases.
1909    if (CFP->getValueAPF().isNaN()) {
1910      // If an operand is known to be a nan, we can fold it.
1911      switch (ISD::getUnorderedFlavor(Cond)) {
1912      default: llvm_unreachable("Unknown flavor!");
1913      case 0:  // Known false.
1914        return DAG.getConstant(0, VT);
1915      case 1:  // Known true.
1916        return DAG.getConstant(1, VT);
1917      case 2:  // Undefined.
1918        return DAG.getUNDEF(VT);
1919      }
1920    }
1921
1922    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
1923    // constant if knowing that the operand is non-nan is enough.  We prefer to
1924    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1925    // materialize 0.0.
1926    if (Cond == ISD::SETO || Cond == ISD::SETUO)
1927      return DAG.getSetCC(dl, VT, N0, N0, Cond);
1928
1929    // If the condition is not legal, see if we can find an equivalent one
1930    // which is legal.
1931    if (!isCondCodeLegal(Cond, N0.getValueType())) {
1932      // If the comparison was an awkward floating-point == or != and one of
1933      // the comparison operands is infinity or negative infinity, convert the
1934      // condition to a less-awkward <= or >=.
1935      if (CFP->getValueAPF().isInfinity()) {
1936        if (CFP->getValueAPF().isNegative()) {
1937          if (Cond == ISD::SETOEQ &&
1938              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1939            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1940          if (Cond == ISD::SETUEQ &&
1941              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1942            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1943          if (Cond == ISD::SETUNE &&
1944              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1945            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1946          if (Cond == ISD::SETONE &&
1947              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1948            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1949        } else {
1950          if (Cond == ISD::SETOEQ &&
1951              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1952            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1953          if (Cond == ISD::SETUEQ &&
1954              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1955            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1956          if (Cond == ISD::SETUNE &&
1957              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1958            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1959          if (Cond == ISD::SETONE &&
1960              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1961            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1962        }
1963      }
1964    }
1965  }
1966
1967  if (N0 == N1) {
1968    // We can always fold X == X for integer setcc's.
1969    if (N0.getValueType().isInteger())
1970      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1971    unsigned UOF = ISD::getUnorderedFlavor(Cond);
1972    if (UOF == 2)   // FP operators that are undefined on NaNs.
1973      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1974    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1975      return DAG.getConstant(UOF, VT);
1976    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
1977    // if it is not already.
1978    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1979    if (NewCond != Cond)
1980      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1981  }
1982
1983  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1984      N0.getValueType().isInteger()) {
1985    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1986        N0.getOpcode() == ISD::XOR) {
1987      // Simplify (X+Y) == (X+Z) -->  Y == Z
1988      if (N0.getOpcode() == N1.getOpcode()) {
1989        if (N0.getOperand(0) == N1.getOperand(0))
1990          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1991        if (N0.getOperand(1) == N1.getOperand(1))
1992          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1993        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1994          // If X op Y == Y op X, try other combinations.
1995          if (N0.getOperand(0) == N1.getOperand(1))
1996            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1997                                Cond);
1998          if (N0.getOperand(1) == N1.getOperand(0))
1999            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2000                                Cond);
2001        }
2002      }
2003
2004      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2005        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2006          // Turn (X+C1) == C2 --> X == C2-C1
2007          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2008            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2009                                DAG.getConstant(RHSC->getAPIntValue()-
2010                                                LHSR->getAPIntValue(),
2011                                N0.getValueType()), Cond);
2012          }
2013
2014          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2015          if (N0.getOpcode() == ISD::XOR)
2016            // If we know that all of the inverted bits are zero, don't bother
2017            // performing the inversion.
2018            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2019              return
2020                DAG.getSetCC(dl, VT, N0.getOperand(0),
2021                             DAG.getConstant(LHSR->getAPIntValue() ^
2022                                               RHSC->getAPIntValue(),
2023                                             N0.getValueType()),
2024                             Cond);
2025        }
2026
2027        // Turn (C1-X) == C2 --> X == C1-C2
2028        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2029          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2030            return
2031              DAG.getSetCC(dl, VT, N0.getOperand(1),
2032                           DAG.getConstant(SUBC->getAPIntValue() -
2033                                             RHSC->getAPIntValue(),
2034                                           N0.getValueType()),
2035                           Cond);
2036          }
2037        }
2038      }
2039
2040      // Simplify (X+Z) == X -->  Z == 0
2041      if (N0.getOperand(0) == N1)
2042        return DAG.getSetCC(dl, VT, N0.getOperand(1),
2043                        DAG.getConstant(0, N0.getValueType()), Cond);
2044      if (N0.getOperand(1) == N1) {
2045        if (DAG.isCommutativeBinOp(N0.getOpcode()))
2046          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2047                          DAG.getConstant(0, N0.getValueType()), Cond);
2048        else if (N0.getNode()->hasOneUse()) {
2049          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2050          // (Z-X) == X  --> Z == X<<1
2051          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2052                                     N1,
2053                                     DAG.getConstant(1, getShiftAmountTy()));
2054          if (!DCI.isCalledByLegalizer())
2055            DCI.AddToWorklist(SH.getNode());
2056          return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2057        }
2058      }
2059    }
2060
2061    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2062        N1.getOpcode() == ISD::XOR) {
2063      // Simplify  X == (X+Z) -->  Z == 0
2064      if (N1.getOperand(0) == N0) {
2065        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2066                        DAG.getConstant(0, N1.getValueType()), Cond);
2067      } else if (N1.getOperand(1) == N0) {
2068        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2069          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2070                          DAG.getConstant(0, N1.getValueType()), Cond);
2071        } else if (N1.getNode()->hasOneUse()) {
2072          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2073          // X == (Z-X)  --> X<<1 == Z
2074          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2075                                     DAG.getConstant(1, getShiftAmountTy()));
2076          if (!DCI.isCalledByLegalizer())
2077            DCI.AddToWorklist(SH.getNode());
2078          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2079        }
2080      }
2081    }
2082
2083    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2084    // Note that where y is variable and is known to have at most
2085    // one bit set (for example, if it is z&1) we cannot do this;
2086    // the expressions are not equivalent when y==0.
2087    if (N0.getOpcode() == ISD::AND)
2088      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2089        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2090          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2091          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2092          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2093        }
2094      }
2095    if (N1.getOpcode() == ISD::AND)
2096      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2097        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2098          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2099          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2100          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2101        }
2102      }
2103  }
2104
2105  // Fold away ALL boolean setcc's.
2106  SDValue Temp;
2107  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2108    switch (Cond) {
2109    default: llvm_unreachable("Unknown integer setcc!");
2110    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2111      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2112      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2113      if (!DCI.isCalledByLegalizer())
2114        DCI.AddToWorklist(Temp.getNode());
2115      break;
2116    case ISD::SETNE:  // X != Y   -->  (X^Y)
2117      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2118      break;
2119    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2120    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2121      Temp = DAG.getNOT(dl, N0, MVT::i1);
2122      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2123      if (!DCI.isCalledByLegalizer())
2124        DCI.AddToWorklist(Temp.getNode());
2125      break;
2126    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2127    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2128      Temp = DAG.getNOT(dl, N1, MVT::i1);
2129      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2130      if (!DCI.isCalledByLegalizer())
2131        DCI.AddToWorklist(Temp.getNode());
2132      break;
2133    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2134    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2135      Temp = DAG.getNOT(dl, N0, MVT::i1);
2136      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2137      if (!DCI.isCalledByLegalizer())
2138        DCI.AddToWorklist(Temp.getNode());
2139      break;
2140    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2141    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2142      Temp = DAG.getNOT(dl, N1, MVT::i1);
2143      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2144      break;
2145    }
2146    if (VT != MVT::i1) {
2147      if (!DCI.isCalledByLegalizer())
2148        DCI.AddToWorklist(N0.getNode());
2149      // FIXME: If running after legalize, we probably can't do this.
2150      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2151    }
2152    return N0;
2153  }
2154
2155  // Could not fold it.
2156  return SDValue();
2157}
2158
2159/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2160/// node is a GlobalAddress + offset.
2161bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2162                                    int64_t &Offset) const {
2163  if (isa<GlobalAddressSDNode>(N)) {
2164    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2165    GA = GASD->getGlobal();
2166    Offset += GASD->getOffset();
2167    return true;
2168  }
2169
2170  if (N->getOpcode() == ISD::ADD) {
2171    SDValue N1 = N->getOperand(0);
2172    SDValue N2 = N->getOperand(1);
2173    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2174      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2175      if (V) {
2176        Offset += V->getSExtValue();
2177        return true;
2178      }
2179    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2180      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2181      if (V) {
2182        Offset += V->getSExtValue();
2183        return true;
2184      }
2185    }
2186  }
2187  return false;
2188}
2189
2190
2191SDValue TargetLowering::
2192PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2193  // Default implementation: no optimization.
2194  return SDValue();
2195}
2196
2197//===----------------------------------------------------------------------===//
2198//  Inline Assembler Implementation Methods
2199//===----------------------------------------------------------------------===//
2200
2201
2202TargetLowering::ConstraintType
2203TargetLowering::getConstraintType(const std::string &Constraint) const {
2204  // FIXME: lots more standard ones to handle.
2205  if (Constraint.size() == 1) {
2206    switch (Constraint[0]) {
2207    default: break;
2208    case 'r': return C_RegisterClass;
2209    case 'm':    // memory
2210    case 'o':    // offsetable
2211    case 'V':    // not offsetable
2212      return C_Memory;
2213    case 'i':    // Simple Integer or Relocatable Constant
2214    case 'n':    // Simple Integer
2215    case 's':    // Relocatable Constant
2216    case 'X':    // Allow ANY value.
2217    case 'I':    // Target registers.
2218    case 'J':
2219    case 'K':
2220    case 'L':
2221    case 'M':
2222    case 'N':
2223    case 'O':
2224    case 'P':
2225      return C_Other;
2226    }
2227  }
2228
2229  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2230      Constraint[Constraint.size()-1] == '}')
2231    return C_Register;
2232  return C_Unknown;
2233}
2234
2235/// LowerXConstraint - try to replace an X constraint, which matches anything,
2236/// with another that has more specific requirements based on the type of the
2237/// corresponding operand.
2238const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2239  if (ConstraintVT.isInteger())
2240    return "r";
2241  if (ConstraintVT.isFloatingPoint())
2242    return "f";      // works for many targets
2243  return 0;
2244}
2245
2246/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2247/// vector.  If it is invalid, don't add anything to Ops.
2248void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2249                                                  char ConstraintLetter,
2250                                                  bool hasMemory,
2251                                                  std::vector<SDValue> &Ops,
2252                                                  SelectionDAG &DAG) const {
2253  switch (ConstraintLetter) {
2254  default: break;
2255  case 'X':     // Allows any operand; labels (basic block) use this.
2256    if (Op.getOpcode() == ISD::BasicBlock) {
2257      Ops.push_back(Op);
2258      return;
2259    }
2260    // fall through
2261  case 'i':    // Simple Integer or Relocatable Constant
2262  case 'n':    // Simple Integer
2263  case 's': {  // Relocatable Constant
2264    // These operands are interested in values of the form (GV+C), where C may
2265    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2266    // is possible and fine if either GV or C are missing.
2267    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2268    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2269
2270    // If we have "(add GV, C)", pull out GV/C
2271    if (Op.getOpcode() == ISD::ADD) {
2272      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2273      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2274      if (C == 0 || GA == 0) {
2275        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2276        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2277      }
2278      if (C == 0 || GA == 0)
2279        C = 0, GA = 0;
2280    }
2281
2282    // If we find a valid operand, map to the TargetXXX version so that the
2283    // value itself doesn't get selected.
2284    if (GA) {   // Either &GV   or   &GV+C
2285      if (ConstraintLetter != 'n') {
2286        int64_t Offs = GA->getOffset();
2287        if (C) Offs += C->getZExtValue();
2288        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2289                                                 Op.getValueType(), Offs));
2290        return;
2291      }
2292    }
2293    if (C) {   // just C, no GV.
2294      // Simple constants are not allowed for 's'.
2295      if (ConstraintLetter != 's') {
2296        // gcc prints these as sign extended.  Sign extend value to 64 bits
2297        // now; without this it would get ZExt'd later in
2298        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2299        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2300                                            MVT::i64));
2301        return;
2302      }
2303    }
2304    break;
2305  }
2306  }
2307}
2308
2309std::vector<unsigned> TargetLowering::
2310getRegClassForInlineAsmConstraint(const std::string &Constraint,
2311                                  EVT VT) const {
2312  return std::vector<unsigned>();
2313}
2314
2315
2316std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2317getRegForInlineAsmConstraint(const std::string &Constraint,
2318                             EVT VT) const {
2319  if (Constraint[0] != '{')
2320    return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2321  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2322
2323  // Remove the braces from around the name.
2324  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2325
2326  // Figure out which register class contains this reg.
2327  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2328  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2329       E = RI->regclass_end(); RCI != E; ++RCI) {
2330    const TargetRegisterClass *RC = *RCI;
2331
2332    // If none of the the value types for this register class are valid, we
2333    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2334    bool isLegal = false;
2335    for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2336         I != E; ++I) {
2337      if (isTypeLegal(*I)) {
2338        isLegal = true;
2339        break;
2340      }
2341    }
2342
2343    if (!isLegal) continue;
2344
2345    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2346         I != E; ++I) {
2347      if (RegName.equals_lower(RI->getName(*I)))
2348        return std::make_pair(*I, RC);
2349    }
2350  }
2351
2352  return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2353}
2354
2355//===----------------------------------------------------------------------===//
2356// Constraint Selection.
2357
2358/// isMatchingInputConstraint - Return true of this is an input operand that is
2359/// a matching constraint like "4".
2360bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2361  assert(!ConstraintCode.empty() && "No known constraint!");
2362  return isdigit(ConstraintCode[0]);
2363}
2364
2365/// getMatchedOperand - If this is an input matching constraint, this method
2366/// returns the output operand it matches.
2367unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2368  assert(!ConstraintCode.empty() && "No known constraint!");
2369  return atoi(ConstraintCode.c_str());
2370}
2371
2372
2373/// getConstraintGenerality - Return an integer indicating how general CT
2374/// is.
2375static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2376  switch (CT) {
2377  default: llvm_unreachable("Unknown constraint type!");
2378  case TargetLowering::C_Other:
2379  case TargetLowering::C_Unknown:
2380    return 0;
2381  case TargetLowering::C_Register:
2382    return 1;
2383  case TargetLowering::C_RegisterClass:
2384    return 2;
2385  case TargetLowering::C_Memory:
2386    return 3;
2387  }
2388}
2389
2390/// ChooseConstraint - If there are multiple different constraints that we
2391/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2392/// This is somewhat tricky: constraints fall into four classes:
2393///    Other         -> immediates and magic values
2394///    Register      -> one specific register
2395///    RegisterClass -> a group of regs
2396///    Memory        -> memory
2397/// Ideally, we would pick the most specific constraint possible: if we have
2398/// something that fits into a register, we would pick it.  The problem here
2399/// is that if we have something that could either be in a register or in
2400/// memory that use of the register could cause selection of *other*
2401/// operands to fail: they might only succeed if we pick memory.  Because of
2402/// this the heuristic we use is:
2403///
2404///  1) If there is an 'other' constraint, and if the operand is valid for
2405///     that constraint, use it.  This makes us take advantage of 'i'
2406///     constraints when available.
2407///  2) Otherwise, pick the most general constraint present.  This prefers
2408///     'm' over 'r', for example.
2409///
2410static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2411                             bool hasMemory,  const TargetLowering &TLI,
2412                             SDValue Op, SelectionDAG *DAG) {
2413  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2414  unsigned BestIdx = 0;
2415  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2416  int BestGenerality = -1;
2417
2418  // Loop over the options, keeping track of the most general one.
2419  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2420    TargetLowering::ConstraintType CType =
2421      TLI.getConstraintType(OpInfo.Codes[i]);
2422
2423    // If this is an 'other' constraint, see if the operand is valid for it.
2424    // For example, on X86 we might have an 'rI' constraint.  If the operand
2425    // is an integer in the range [0..31] we want to use I (saving a load
2426    // of a register), otherwise we must use 'r'.
2427    if (CType == TargetLowering::C_Other && Op.getNode()) {
2428      assert(OpInfo.Codes[i].size() == 1 &&
2429             "Unhandled multi-letter 'other' constraint");
2430      std::vector<SDValue> ResultOps;
2431      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2432                                       ResultOps, *DAG);
2433      if (!ResultOps.empty()) {
2434        BestType = CType;
2435        BestIdx = i;
2436        break;
2437      }
2438    }
2439
2440    // This constraint letter is more general than the previous one, use it.
2441    int Generality = getConstraintGenerality(CType);
2442    if (Generality > BestGenerality) {
2443      BestType = CType;
2444      BestIdx = i;
2445      BestGenerality = Generality;
2446    }
2447  }
2448
2449  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2450  OpInfo.ConstraintType = BestType;
2451}
2452
2453/// ComputeConstraintToUse - Determines the constraint code and constraint
2454/// type to use for the specific AsmOperandInfo, setting
2455/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2456void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2457                                            SDValue Op,
2458                                            bool hasMemory,
2459                                            SelectionDAG *DAG) const {
2460  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2461
2462  // Single-letter constraints ('r') are very common.
2463  if (OpInfo.Codes.size() == 1) {
2464    OpInfo.ConstraintCode = OpInfo.Codes[0];
2465    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2466  } else {
2467    ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2468  }
2469
2470  // 'X' matches anything.
2471  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2472    // Labels and constants are handled elsewhere ('X' is the only thing
2473    // that matches labels).  For Functions, the type here is the type of
2474    // the result, which is not what we want to look at; leave them alone.
2475    Value *v = OpInfo.CallOperandVal;
2476    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2477      OpInfo.CallOperandVal = v;
2478      return;
2479    }
2480
2481    // Otherwise, try to resolve it to something we know about by looking at
2482    // the actual operand type.
2483    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2484      OpInfo.ConstraintCode = Repl;
2485      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2486    }
2487  }
2488}
2489
2490//===----------------------------------------------------------------------===//
2491//  Loop Strength Reduction hooks
2492//===----------------------------------------------------------------------===//
2493
2494/// isLegalAddressingMode - Return true if the addressing mode represented
2495/// by AM is legal for this target, for a load/store of the specified type.
2496bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2497                                           const Type *Ty) const {
2498  // The default implementation of this implements a conservative RISCy, r+r and
2499  // r+i addr mode.
2500
2501  // Allows a sign-extended 16-bit immediate field.
2502  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2503    return false;
2504
2505  // No global is ever allowed as a base.
2506  if (AM.BaseGV)
2507    return false;
2508
2509  // Only support r+r,
2510  switch (AM.Scale) {
2511  case 0:  // "r+i" or just "i", depending on HasBaseReg.
2512    break;
2513  case 1:
2514    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
2515      return false;
2516    // Otherwise we have r+r or r+i.
2517    break;
2518  case 2:
2519    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
2520      return false;
2521    // Allow 2*r as r+r.
2522    break;
2523  }
2524
2525  return true;
2526}
2527
2528/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2529/// return a DAG expression to select that will generate the same value by
2530/// multiplying by a magic number.  See:
2531/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2532SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2533                                  std::vector<SDNode*>* Created) const {
2534  EVT VT = N->getValueType(0);
2535  DebugLoc dl= N->getDebugLoc();
2536
2537  // Check to see if we can do this.
2538  // FIXME: We should be more aggressive here.
2539  if (!isTypeLegal(VT))
2540    return SDValue();
2541
2542  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2543  APInt::ms magics = d.magic();
2544
2545  // Multiply the numerator (operand 0) by the magic value
2546  // FIXME: We should support doing a MUL in a wider type
2547  SDValue Q;
2548  if (isOperationLegalOrCustom(ISD::MULHS, VT))
2549    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2550                    DAG.getConstant(magics.m, VT));
2551  else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2552    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2553                              N->getOperand(0),
2554                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2555  else
2556    return SDValue();       // No mulhs or equvialent
2557  // If d > 0 and m < 0, add the numerator
2558  if (d.isStrictlyPositive() && magics.m.isNegative()) {
2559    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2560    if (Created)
2561      Created->push_back(Q.getNode());
2562  }
2563  // If d < 0 and m > 0, subtract the numerator.
2564  if (d.isNegative() && magics.m.isStrictlyPositive()) {
2565    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2566    if (Created)
2567      Created->push_back(Q.getNode());
2568  }
2569  // Shift right algebraic if shift value is nonzero
2570  if (magics.s > 0) {
2571    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2572                    DAG.getConstant(magics.s, getShiftAmountTy()));
2573    if (Created)
2574      Created->push_back(Q.getNode());
2575  }
2576  // Extract the sign bit and add it to the quotient
2577  SDValue T =
2578    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2579                                                 getShiftAmountTy()));
2580  if (Created)
2581    Created->push_back(T.getNode());
2582  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2583}
2584
2585/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2586/// return a DAG expression to select that will generate the same value by
2587/// multiplying by a magic number.  See:
2588/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2589SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2590                                  std::vector<SDNode*>* Created) const {
2591  EVT VT = N->getValueType(0);
2592  DebugLoc dl = N->getDebugLoc();
2593
2594  // Check to see if we can do this.
2595  // FIXME: We should be more aggressive here.
2596  if (!isTypeLegal(VT))
2597    return SDValue();
2598
2599  // FIXME: We should use a narrower constant when the upper
2600  // bits are known to be zero.
2601  ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2602  APInt::mu magics = N1C->getAPIntValue().magicu();
2603
2604  // Multiply the numerator (operand 0) by the magic value
2605  // FIXME: We should support doing a MUL in a wider type
2606  SDValue Q;
2607  if (isOperationLegalOrCustom(ISD::MULHU, VT))
2608    Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2609                    DAG.getConstant(magics.m, VT));
2610  else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2611    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2612                              N->getOperand(0),
2613                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2614  else
2615    return SDValue();       // No mulhu or equvialent
2616  if (Created)
2617    Created->push_back(Q.getNode());
2618
2619  if (magics.a == 0) {
2620    assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2621           "We shouldn't generate an undefined shift!");
2622    return DAG.getNode(ISD::SRL, dl, VT, Q,
2623                       DAG.getConstant(magics.s, getShiftAmountTy()));
2624  } else {
2625    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2626    if (Created)
2627      Created->push_back(NPQ.getNode());
2628    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2629                      DAG.getConstant(1, getShiftAmountTy()));
2630    if (Created)
2631      Created->push_back(NPQ.getNode());
2632    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2633    if (Created)
2634      Created->push_back(NPQ.getNode());
2635    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2636                       DAG.getConstant(magics.s-1, getShiftAmountTy()));
2637  }
2638}
2639