TargetLowering.cpp revision 193574
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29namespace llvm { 30TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 31 bool isLocal = GV->hasLocalLinkage(); 32 bool isDeclaration = GV->isDeclaration(); 33 // FIXME: what should we do for protected and internal visibility? 34 // For variables, is internal different from hidden? 35 bool isHidden = GV->hasHiddenVisibility(); 36 37 if (reloc == Reloc::PIC_) { 38 if (isLocal || isHidden) 39 return TLSModel::LocalDynamic; 40 else 41 return TLSModel::GeneralDynamic; 42 } else { 43 if (!isDeclaration || isHidden) 44 return TLSModel::LocalExec; 45 else 46 return TLSModel::InitialExec; 47 } 48} 49} 50 51/// InitLibcallNames - Set default libcall names. 52/// 53static void InitLibcallNames(const char **Names) { 54 Names[RTLIB::SHL_I16] = "__ashlhi3"; 55 Names[RTLIB::SHL_I32] = "__ashlsi3"; 56 Names[RTLIB::SHL_I64] = "__ashldi3"; 57 Names[RTLIB::SHL_I128] = "__ashlti3"; 58 Names[RTLIB::SRL_I16] = "__lshrhi3"; 59 Names[RTLIB::SRL_I32] = "__lshrsi3"; 60 Names[RTLIB::SRL_I64] = "__lshrdi3"; 61 Names[RTLIB::SRL_I128] = "__lshrti3"; 62 Names[RTLIB::SRA_I16] = "__ashrhi3"; 63 Names[RTLIB::SRA_I32] = "__ashrsi3"; 64 Names[RTLIB::SRA_I64] = "__ashrdi3"; 65 Names[RTLIB::SRA_I128] = "__ashrti3"; 66 Names[RTLIB::MUL_I16] = "__mulhi3"; 67 Names[RTLIB::MUL_I32] = "__mulsi3"; 68 Names[RTLIB::MUL_I64] = "__muldi3"; 69 Names[RTLIB::MUL_I128] = "__multi3"; 70 Names[RTLIB::SDIV_I16] = "__divhi3"; 71 Names[RTLIB::SDIV_I32] = "__divsi3"; 72 Names[RTLIB::SDIV_I64] = "__divdi3"; 73 Names[RTLIB::SDIV_I128] = "__divti3"; 74 Names[RTLIB::UDIV_I16] = "__udivhi3"; 75 Names[RTLIB::UDIV_I32] = "__udivsi3"; 76 Names[RTLIB::UDIV_I64] = "__udivdi3"; 77 Names[RTLIB::UDIV_I128] = "__udivti3"; 78 Names[RTLIB::SREM_I16] = "__modhi3"; 79 Names[RTLIB::SREM_I32] = "__modsi3"; 80 Names[RTLIB::SREM_I64] = "__moddi3"; 81 Names[RTLIB::SREM_I128] = "__modti3"; 82 Names[RTLIB::UREM_I16] = "__umodhi3"; 83 Names[RTLIB::UREM_I32] = "__umodsi3"; 84 Names[RTLIB::UREM_I64] = "__umoddi3"; 85 Names[RTLIB::UREM_I128] = "__umodti3"; 86 Names[RTLIB::NEG_I32] = "__negsi2"; 87 Names[RTLIB::NEG_I64] = "__negdi2"; 88 Names[RTLIB::ADD_F32] = "__addsf3"; 89 Names[RTLIB::ADD_F64] = "__adddf3"; 90 Names[RTLIB::ADD_F80] = "__addxf3"; 91 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 92 Names[RTLIB::SUB_F32] = "__subsf3"; 93 Names[RTLIB::SUB_F64] = "__subdf3"; 94 Names[RTLIB::SUB_F80] = "__subxf3"; 95 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 96 Names[RTLIB::MUL_F32] = "__mulsf3"; 97 Names[RTLIB::MUL_F64] = "__muldf3"; 98 Names[RTLIB::MUL_F80] = "__mulxf3"; 99 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 100 Names[RTLIB::DIV_F32] = "__divsf3"; 101 Names[RTLIB::DIV_F64] = "__divdf3"; 102 Names[RTLIB::DIV_F80] = "__divxf3"; 103 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 104 Names[RTLIB::REM_F32] = "fmodf"; 105 Names[RTLIB::REM_F64] = "fmod"; 106 Names[RTLIB::REM_F80] = "fmodl"; 107 Names[RTLIB::REM_PPCF128] = "fmodl"; 108 Names[RTLIB::POWI_F32] = "__powisf2"; 109 Names[RTLIB::POWI_F64] = "__powidf2"; 110 Names[RTLIB::POWI_F80] = "__powixf2"; 111 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 112 Names[RTLIB::SQRT_F32] = "sqrtf"; 113 Names[RTLIB::SQRT_F64] = "sqrt"; 114 Names[RTLIB::SQRT_F80] = "sqrtl"; 115 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 116 Names[RTLIB::LOG_F32] = "logf"; 117 Names[RTLIB::LOG_F64] = "log"; 118 Names[RTLIB::LOG_F80] = "logl"; 119 Names[RTLIB::LOG_PPCF128] = "logl"; 120 Names[RTLIB::LOG2_F32] = "log2f"; 121 Names[RTLIB::LOG2_F64] = "log2"; 122 Names[RTLIB::LOG2_F80] = "log2l"; 123 Names[RTLIB::LOG2_PPCF128] = "log2l"; 124 Names[RTLIB::LOG10_F32] = "log10f"; 125 Names[RTLIB::LOG10_F64] = "log10"; 126 Names[RTLIB::LOG10_F80] = "log10l"; 127 Names[RTLIB::LOG10_PPCF128] = "log10l"; 128 Names[RTLIB::EXP_F32] = "expf"; 129 Names[RTLIB::EXP_F64] = "exp"; 130 Names[RTLIB::EXP_F80] = "expl"; 131 Names[RTLIB::EXP_PPCF128] = "expl"; 132 Names[RTLIB::EXP2_F32] = "exp2f"; 133 Names[RTLIB::EXP2_F64] = "exp2"; 134 Names[RTLIB::EXP2_F80] = "exp2l"; 135 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 136 Names[RTLIB::SIN_F32] = "sinf"; 137 Names[RTLIB::SIN_F64] = "sin"; 138 Names[RTLIB::SIN_F80] = "sinl"; 139 Names[RTLIB::SIN_PPCF128] = "sinl"; 140 Names[RTLIB::COS_F32] = "cosf"; 141 Names[RTLIB::COS_F64] = "cos"; 142 Names[RTLIB::COS_F80] = "cosl"; 143 Names[RTLIB::COS_PPCF128] = "cosl"; 144 Names[RTLIB::POW_F32] = "powf"; 145 Names[RTLIB::POW_F64] = "pow"; 146 Names[RTLIB::POW_F80] = "powl"; 147 Names[RTLIB::POW_PPCF128] = "powl"; 148 Names[RTLIB::CEIL_F32] = "ceilf"; 149 Names[RTLIB::CEIL_F64] = "ceil"; 150 Names[RTLIB::CEIL_F80] = "ceill"; 151 Names[RTLIB::CEIL_PPCF128] = "ceill"; 152 Names[RTLIB::TRUNC_F32] = "truncf"; 153 Names[RTLIB::TRUNC_F64] = "trunc"; 154 Names[RTLIB::TRUNC_F80] = "truncl"; 155 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 156 Names[RTLIB::RINT_F32] = "rintf"; 157 Names[RTLIB::RINT_F64] = "rint"; 158 Names[RTLIB::RINT_F80] = "rintl"; 159 Names[RTLIB::RINT_PPCF128] = "rintl"; 160 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 161 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 162 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 163 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 164 Names[RTLIB::FLOOR_F32] = "floorf"; 165 Names[RTLIB::FLOOR_F64] = "floor"; 166 Names[RTLIB::FLOOR_F80] = "floorl"; 167 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 168 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 169 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 170 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 171 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 172 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 173 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 174 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 175 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 176 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 177 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 178 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 179 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 180 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 181 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 182 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 183 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 184 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 185 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 186 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 187 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 188 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 189 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 190 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 191 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 192 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 193 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 194 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 195 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 196 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 197 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 198 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 199 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 200 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 201 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 202 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 203 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 204 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 205 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 206 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 207 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 208 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 209 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 210 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 211 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 212 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 213 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 214 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 215 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 216 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 217 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 218 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 219 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 220 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 221 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 222 Names[RTLIB::OEQ_F32] = "__eqsf2"; 223 Names[RTLIB::OEQ_F64] = "__eqdf2"; 224 Names[RTLIB::UNE_F32] = "__nesf2"; 225 Names[RTLIB::UNE_F64] = "__nedf2"; 226 Names[RTLIB::OGE_F32] = "__gesf2"; 227 Names[RTLIB::OGE_F64] = "__gedf2"; 228 Names[RTLIB::OLT_F32] = "__ltsf2"; 229 Names[RTLIB::OLT_F64] = "__ltdf2"; 230 Names[RTLIB::OLE_F32] = "__lesf2"; 231 Names[RTLIB::OLE_F64] = "__ledf2"; 232 Names[RTLIB::OGT_F32] = "__gtsf2"; 233 Names[RTLIB::OGT_F64] = "__gtdf2"; 234 Names[RTLIB::UO_F32] = "__unordsf2"; 235 Names[RTLIB::UO_F64] = "__unorddf2"; 236 Names[RTLIB::O_F32] = "__unordsf2"; 237 Names[RTLIB::O_F64] = "__unorddf2"; 238 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 239} 240 241/// getFPEXT - Return the FPEXT_*_* value for the given types, or 242/// UNKNOWN_LIBCALL if there is none. 243RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 244 if (OpVT == MVT::f32) { 245 if (RetVT == MVT::f64) 246 return FPEXT_F32_F64; 247 } 248 return UNKNOWN_LIBCALL; 249} 250 251/// getFPROUND - Return the FPROUND_*_* value for the given types, or 252/// UNKNOWN_LIBCALL if there is none. 253RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 254 if (RetVT == MVT::f32) { 255 if (OpVT == MVT::f64) 256 return FPROUND_F64_F32; 257 if (OpVT == MVT::f80) 258 return FPROUND_F80_F32; 259 if (OpVT == MVT::ppcf128) 260 return FPROUND_PPCF128_F32; 261 } else if (RetVT == MVT::f64) { 262 if (OpVT == MVT::f80) 263 return FPROUND_F80_F64; 264 if (OpVT == MVT::ppcf128) 265 return FPROUND_PPCF128_F64; 266 } 267 return UNKNOWN_LIBCALL; 268} 269 270/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 271/// UNKNOWN_LIBCALL if there is none. 272RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 273 if (OpVT == MVT::f32) { 274 if (RetVT == MVT::i32) 275 return FPTOSINT_F32_I32; 276 if (RetVT == MVT::i64) 277 return FPTOSINT_F32_I64; 278 if (RetVT == MVT::i128) 279 return FPTOSINT_F32_I128; 280 } else if (OpVT == MVT::f64) { 281 if (RetVT == MVT::i32) 282 return FPTOSINT_F64_I32; 283 if (RetVT == MVT::i64) 284 return FPTOSINT_F64_I64; 285 if (RetVT == MVT::i128) 286 return FPTOSINT_F64_I128; 287 } else if (OpVT == MVT::f80) { 288 if (RetVT == MVT::i32) 289 return FPTOSINT_F80_I32; 290 if (RetVT == MVT::i64) 291 return FPTOSINT_F80_I64; 292 if (RetVT == MVT::i128) 293 return FPTOSINT_F80_I128; 294 } else if (OpVT == MVT::ppcf128) { 295 if (RetVT == MVT::i32) 296 return FPTOSINT_PPCF128_I32; 297 if (RetVT == MVT::i64) 298 return FPTOSINT_PPCF128_I64; 299 if (RetVT == MVT::i128) 300 return FPTOSINT_PPCF128_I128; 301 } 302 return UNKNOWN_LIBCALL; 303} 304 305/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 306/// UNKNOWN_LIBCALL if there is none. 307RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 308 if (OpVT == MVT::f32) { 309 if (RetVT == MVT::i32) 310 return FPTOUINT_F32_I32; 311 if (RetVT == MVT::i64) 312 return FPTOUINT_F32_I64; 313 if (RetVT == MVT::i128) 314 return FPTOUINT_F32_I128; 315 } else if (OpVT == MVT::f64) { 316 if (RetVT == MVT::i32) 317 return FPTOUINT_F64_I32; 318 if (RetVT == MVT::i64) 319 return FPTOUINT_F64_I64; 320 if (RetVT == MVT::i128) 321 return FPTOUINT_F64_I128; 322 } else if (OpVT == MVT::f80) { 323 if (RetVT == MVT::i32) 324 return FPTOUINT_F80_I32; 325 if (RetVT == MVT::i64) 326 return FPTOUINT_F80_I64; 327 if (RetVT == MVT::i128) 328 return FPTOUINT_F80_I128; 329 } else if (OpVT == MVT::ppcf128) { 330 if (RetVT == MVT::i32) 331 return FPTOUINT_PPCF128_I32; 332 if (RetVT == MVT::i64) 333 return FPTOUINT_PPCF128_I64; 334 if (RetVT == MVT::i128) 335 return FPTOUINT_PPCF128_I128; 336 } 337 return UNKNOWN_LIBCALL; 338} 339 340/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 341/// UNKNOWN_LIBCALL if there is none. 342RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 343 if (OpVT == MVT::i32) { 344 if (RetVT == MVT::f32) 345 return SINTTOFP_I32_F32; 346 else if (RetVT == MVT::f64) 347 return SINTTOFP_I32_F64; 348 else if (RetVT == MVT::f80) 349 return SINTTOFP_I32_F80; 350 else if (RetVT == MVT::ppcf128) 351 return SINTTOFP_I32_PPCF128; 352 } else if (OpVT == MVT::i64) { 353 if (RetVT == MVT::f32) 354 return SINTTOFP_I64_F32; 355 else if (RetVT == MVT::f64) 356 return SINTTOFP_I64_F64; 357 else if (RetVT == MVT::f80) 358 return SINTTOFP_I64_F80; 359 else if (RetVT == MVT::ppcf128) 360 return SINTTOFP_I64_PPCF128; 361 } else if (OpVT == MVT::i128) { 362 if (RetVT == MVT::f32) 363 return SINTTOFP_I128_F32; 364 else if (RetVT == MVT::f64) 365 return SINTTOFP_I128_F64; 366 else if (RetVT == MVT::f80) 367 return SINTTOFP_I128_F80; 368 else if (RetVT == MVT::ppcf128) 369 return SINTTOFP_I128_PPCF128; 370 } 371 return UNKNOWN_LIBCALL; 372} 373 374/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 375/// UNKNOWN_LIBCALL if there is none. 376RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 377 if (OpVT == MVT::i32) { 378 if (RetVT == MVT::f32) 379 return UINTTOFP_I32_F32; 380 else if (RetVT == MVT::f64) 381 return UINTTOFP_I32_F64; 382 else if (RetVT == MVT::f80) 383 return UINTTOFP_I32_F80; 384 else if (RetVT == MVT::ppcf128) 385 return UINTTOFP_I32_PPCF128; 386 } else if (OpVT == MVT::i64) { 387 if (RetVT == MVT::f32) 388 return UINTTOFP_I64_F32; 389 else if (RetVT == MVT::f64) 390 return UINTTOFP_I64_F64; 391 else if (RetVT == MVT::f80) 392 return UINTTOFP_I64_F80; 393 else if (RetVT == MVT::ppcf128) 394 return UINTTOFP_I64_PPCF128; 395 } else if (OpVT == MVT::i128) { 396 if (RetVT == MVT::f32) 397 return UINTTOFP_I128_F32; 398 else if (RetVT == MVT::f64) 399 return UINTTOFP_I128_F64; 400 else if (RetVT == MVT::f80) 401 return UINTTOFP_I128_F80; 402 else if (RetVT == MVT::ppcf128) 403 return UINTTOFP_I128_PPCF128; 404 } 405 return UNKNOWN_LIBCALL; 406} 407 408/// InitCmpLibcallCCs - Set default comparison libcall CC. 409/// 410static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 411 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 412 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 413 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 414 CCs[RTLIB::UNE_F32] = ISD::SETNE; 415 CCs[RTLIB::UNE_F64] = ISD::SETNE; 416 CCs[RTLIB::OGE_F32] = ISD::SETGE; 417 CCs[RTLIB::OGE_F64] = ISD::SETGE; 418 CCs[RTLIB::OLT_F32] = ISD::SETLT; 419 CCs[RTLIB::OLT_F64] = ISD::SETLT; 420 CCs[RTLIB::OLE_F32] = ISD::SETLE; 421 CCs[RTLIB::OLE_F64] = ISD::SETLE; 422 CCs[RTLIB::OGT_F32] = ISD::SETGT; 423 CCs[RTLIB::OGT_F64] = ISD::SETGT; 424 CCs[RTLIB::UO_F32] = ISD::SETNE; 425 CCs[RTLIB::UO_F64] = ISD::SETNE; 426 CCs[RTLIB::O_F32] = ISD::SETEQ; 427 CCs[RTLIB::O_F64] = ISD::SETEQ; 428} 429 430TargetLowering::TargetLowering(TargetMachine &tm) 431 : TM(tm), TD(TM.getTargetData()) { 432 // All operations default to being supported. 433 memset(OpActions, 0, sizeof(OpActions)); 434 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 435 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 436 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 437 memset(ConvertActions, 0, sizeof(ConvertActions)); 438 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 439 440 // Set default actions for various operations. 441 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 442 // Default all indexed load / store to expand. 443 for (unsigned IM = (unsigned)ISD::PRE_INC; 444 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 445 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 446 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 447 } 448 449 // These operations default to expand. 450 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 451 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 452 } 453 454 // Most targets ignore the @llvm.prefetch intrinsic. 455 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 456 457 // ConstantFP nodes default to expand. Targets can either change this to 458 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 459 // to optimize expansions for certain constants. 460 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 461 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 462 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 463 464 // These library functions default to expand. 465 setOperationAction(ISD::FLOG , MVT::f64, Expand); 466 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 467 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 468 setOperationAction(ISD::FEXP , MVT::f64, Expand); 469 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 470 setOperationAction(ISD::FLOG , MVT::f32, Expand); 471 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 472 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 473 setOperationAction(ISD::FEXP , MVT::f32, Expand); 474 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 475 476 // Default ISD::TRAP to expand (which turns it into abort). 477 setOperationAction(ISD::TRAP, MVT::Other, Expand); 478 479 IsLittleEndian = TD->isLittleEndian(); 480 UsesGlobalOffsetTable = false; 481 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 482 ShiftAmtHandling = Undefined; 483 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 484 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 485 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 486 allowUnalignedMemoryAccesses = false; 487 benefitFromCodePlacementOpt = false; 488 UseUnderscoreSetJmp = false; 489 UseUnderscoreLongJmp = false; 490 SelectIsExpensive = false; 491 IntDivIsCheap = false; 492 Pow2DivIsCheap = false; 493 StackPointerRegisterToSaveRestore = 0; 494 ExceptionPointerRegister = 0; 495 ExceptionSelectorRegister = 0; 496 BooleanContents = UndefinedBooleanContent; 497 SchedPreferenceInfo = SchedulingForLatency; 498 JumpBufSize = 0; 499 JumpBufAlignment = 0; 500 IfCvtBlockSizeLimit = 2; 501 IfCvtDupBlockSizeLimit = 0; 502 PrefLoopAlignment = 0; 503 504 InitLibcallNames(LibcallRoutineNames); 505 InitCmpLibcallCCs(CmpLibcallCCs); 506 507 // Tell Legalize whether the assembler supports DEBUG_LOC. 508 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 509 if (!TASM || !TASM->hasDotLocAndDotFile()) 510 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 511} 512 513TargetLowering::~TargetLowering() {} 514 515/// computeRegisterProperties - Once all of the register classes are added, 516/// this allows us to compute derived properties we expose. 517void TargetLowering::computeRegisterProperties() { 518 assert(MVT::LAST_VALUETYPE <= 32 && 519 "Too many value types for ValueTypeActions to hold!"); 520 521 // Everything defaults to needing one register. 522 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 523 NumRegistersForVT[i] = 1; 524 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 525 } 526 // ...except isVoid, which doesn't need any registers. 527 NumRegistersForVT[MVT::isVoid] = 0; 528 529 // Find the largest integer register class. 530 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 531 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 532 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 533 534 // Every integer value type larger than this largest register takes twice as 535 // many registers to represent as the previous ValueType. 536 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 537 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 538 if (!EVT.isInteger()) 539 break; 540 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 541 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 542 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 543 ValueTypeActions.setTypeAction(EVT, Expand); 544 } 545 546 // Inspect all of the ValueType's smaller than the largest integer 547 // register to see which ones need promotion. 548 unsigned LegalIntReg = LargestIntReg; 549 for (unsigned IntReg = LargestIntReg - 1; 550 IntReg >= (unsigned)MVT::i1; --IntReg) { 551 MVT IVT = (MVT::SimpleValueType)IntReg; 552 if (isTypeLegal(IVT)) { 553 LegalIntReg = IntReg; 554 } else { 555 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 556 (MVT::SimpleValueType)LegalIntReg; 557 ValueTypeActions.setTypeAction(IVT, Promote); 558 } 559 } 560 561 // ppcf128 type is really two f64's. 562 if (!isTypeLegal(MVT::ppcf128)) { 563 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 564 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 565 TransformToType[MVT::ppcf128] = MVT::f64; 566 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 567 } 568 569 // Decide how to handle f64. If the target does not have native f64 support, 570 // expand it to i64 and we will be generating soft float library calls. 571 if (!isTypeLegal(MVT::f64)) { 572 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 573 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 574 TransformToType[MVT::f64] = MVT::i64; 575 ValueTypeActions.setTypeAction(MVT::f64, Expand); 576 } 577 578 // Decide how to handle f32. If the target does not have native support for 579 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 580 if (!isTypeLegal(MVT::f32)) { 581 if (isTypeLegal(MVT::f64)) { 582 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 583 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 584 TransformToType[MVT::f32] = MVT::f64; 585 ValueTypeActions.setTypeAction(MVT::f32, Promote); 586 } else { 587 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 588 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 589 TransformToType[MVT::f32] = MVT::i32; 590 ValueTypeActions.setTypeAction(MVT::f32, Expand); 591 } 592 } 593 594 // Loop over all of the vector value types to see which need transformations. 595 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 596 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 597 MVT VT = (MVT::SimpleValueType)i; 598 if (!isTypeLegal(VT)) { 599 MVT IntermediateVT, RegisterVT; 600 unsigned NumIntermediates; 601 NumRegistersForVT[i] = 602 getVectorTypeBreakdown(VT, 603 IntermediateVT, NumIntermediates, 604 RegisterVT); 605 RegisterTypeForVT[i] = RegisterVT; 606 607 // Determine if there is a legal wider type. 608 bool IsLegalWiderType = false; 609 MVT EltVT = VT.getVectorElementType(); 610 unsigned NElts = VT.getVectorNumElements(); 611 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 612 MVT SVT = (MVT::SimpleValueType)nVT; 613 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 614 SVT.getVectorNumElements() > NElts) { 615 TransformToType[i] = SVT; 616 ValueTypeActions.setTypeAction(VT, Promote); 617 IsLegalWiderType = true; 618 break; 619 } 620 } 621 if (!IsLegalWiderType) { 622 MVT NVT = VT.getPow2VectorType(); 623 if (NVT == VT) { 624 // Type is already a power of 2. The default action is to split. 625 TransformToType[i] = MVT::Other; 626 ValueTypeActions.setTypeAction(VT, Expand); 627 } else { 628 TransformToType[i] = NVT; 629 ValueTypeActions.setTypeAction(VT, Promote); 630 } 631 } 632 } 633 } 634} 635 636const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 637 return NULL; 638} 639 640 641MVT TargetLowering::getSetCCResultType(MVT VT) const { 642 return getValueType(TD->getIntPtrType()); 643} 644 645 646/// getVectorTypeBreakdown - Vector types are broken down into some number of 647/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 648/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 649/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 650/// 651/// This method returns the number of registers needed, and the VT for each 652/// register. It also returns the VT and quantity of the intermediate values 653/// before they are promoted/expanded. 654/// 655unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 656 MVT &IntermediateVT, 657 unsigned &NumIntermediates, 658 MVT &RegisterVT) const { 659 // Figure out the right, legal destination reg to copy into. 660 unsigned NumElts = VT.getVectorNumElements(); 661 MVT EltTy = VT.getVectorElementType(); 662 663 unsigned NumVectorRegs = 1; 664 665 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 666 // could break down into LHS/RHS like LegalizeDAG does. 667 if (!isPowerOf2_32(NumElts)) { 668 NumVectorRegs = NumElts; 669 NumElts = 1; 670 } 671 672 // Divide the input until we get to a supported size. This will always 673 // end with a scalar if the target doesn't support vectors. 674 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 675 NumElts >>= 1; 676 NumVectorRegs <<= 1; 677 } 678 679 NumIntermediates = NumVectorRegs; 680 681 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 682 if (!isTypeLegal(NewVT)) 683 NewVT = EltTy; 684 IntermediateVT = NewVT; 685 686 MVT DestVT = getRegisterType(NewVT); 687 RegisterVT = DestVT; 688 if (DestVT.bitsLT(NewVT)) { 689 // Value is expanded, e.g. i64 -> i16. 690 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 691 } else { 692 // Otherwise, promotion or legal types use the same number of registers as 693 // the vector decimated to the appropriate level. 694 return NumVectorRegs; 695 } 696 697 return 1; 698} 699 700/// getWidenVectorType: given a vector type, returns the type to widen to 701/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 702/// If there is no vector type that we want to widen to, returns MVT::Other 703/// When and where to widen is target dependent based on the cost of 704/// scalarizing vs using the wider vector type. 705MVT TargetLowering::getWidenVectorType(MVT VT) const { 706 assert(VT.isVector()); 707 if (isTypeLegal(VT)) 708 return VT; 709 710 // Default is not to widen until moved to LegalizeTypes 711 return MVT::Other; 712} 713 714/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 715/// function arguments in the caller parameter area. This is the actual 716/// alignment, not its logarithm. 717unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 718 return TD->getCallFrameTypeAlignment(Ty); 719} 720 721SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 722 SelectionDAG &DAG) const { 723 if (usesGlobalOffsetTable()) 724 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 725 return Table; 726} 727 728bool 729TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 730 // Assume that everything is safe in static mode. 731 if (getTargetMachine().getRelocationModel() == Reloc::Static) 732 return true; 733 734 // In dynamic-no-pic mode, assume that known defined values are safe. 735 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 736 GA && 737 !GA->getGlobal()->isDeclaration() && 738 !GA->getGlobal()->isWeakForLinker()) 739 return true; 740 741 // Otherwise assume nothing is safe. 742 return false; 743} 744 745//===----------------------------------------------------------------------===// 746// Optimization Methods 747//===----------------------------------------------------------------------===// 748 749/// ShrinkDemandedConstant - Check to see if the specified operand of the 750/// specified instruction is a constant integer. If so, check to see if there 751/// are any bits set in the constant that are not demanded. If so, shrink the 752/// constant and return true. 753bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 754 const APInt &Demanded) { 755 DebugLoc dl = Op.getDebugLoc(); 756 757 // FIXME: ISD::SELECT, ISD::SELECT_CC 758 switch (Op.getOpcode()) { 759 default: break; 760 case ISD::XOR: 761 case ISD::AND: 762 case ISD::OR: { 763 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 764 if (!C) return false; 765 766 if (Op.getOpcode() == ISD::XOR && 767 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 768 return false; 769 770 // if we can expand it to have all bits set, do it 771 if (C->getAPIntValue().intersects(~Demanded)) { 772 MVT VT = Op.getValueType(); 773 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 774 DAG.getConstant(Demanded & 775 C->getAPIntValue(), 776 VT)); 777 return CombineTo(Op, New); 778 } 779 780 break; 781 } 782 } 783 784 return false; 785} 786 787/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 788/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 789/// cast, but it could be generalized for targets with other types of 790/// implicit widening casts. 791bool 792TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 793 unsigned BitWidth, 794 const APInt &Demanded, 795 DebugLoc dl) { 796 assert(Op.getNumOperands() == 2 && 797 "ShrinkDemandedOp only supports binary operators!"); 798 assert(Op.getNode()->getNumValues() == 1 && 799 "ShrinkDemandedOp only supports nodes with one result!"); 800 801 // Don't do this if the node has another user, which may require the 802 // full value. 803 if (!Op.getNode()->hasOneUse()) 804 return false; 805 806 // Search for the smallest integer type with free casts to and from 807 // Op's type. For expedience, just check power-of-2 integer types. 808 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 809 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 810 if (!isPowerOf2_32(SmallVTBits)) 811 SmallVTBits = NextPowerOf2(SmallVTBits); 812 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 813 MVT SmallVT = MVT::getIntegerVT(SmallVTBits); 814 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 815 TLI.isZExtFree(SmallVT, Op.getValueType())) { 816 // We found a type with free casts. 817 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 818 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 819 Op.getNode()->getOperand(0)), 820 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 821 Op.getNode()->getOperand(1))); 822 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 823 return CombineTo(Op, Z); 824 } 825 } 826 return false; 827} 828 829/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 830/// DemandedMask bits of the result of Op are ever used downstream. If we can 831/// use this information to simplify Op, create a new simplified DAG node and 832/// return true, returning the original and new nodes in Old and New. Otherwise, 833/// analyze the expression and return a mask of KnownOne and KnownZero bits for 834/// the expression (used to simplify the caller). The KnownZero/One bits may 835/// only be accurate for those bits in the DemandedMask. 836bool TargetLowering::SimplifyDemandedBits(SDValue Op, 837 const APInt &DemandedMask, 838 APInt &KnownZero, 839 APInt &KnownOne, 840 TargetLoweringOpt &TLO, 841 unsigned Depth) const { 842 unsigned BitWidth = DemandedMask.getBitWidth(); 843 assert(Op.getValueSizeInBits() == BitWidth && 844 "Mask size mismatches value type size!"); 845 APInt NewMask = DemandedMask; 846 DebugLoc dl = Op.getDebugLoc(); 847 848 // Don't know anything. 849 KnownZero = KnownOne = APInt(BitWidth, 0); 850 851 // Other users may use these bits. 852 if (!Op.getNode()->hasOneUse()) { 853 if (Depth != 0) { 854 // If not at the root, Just compute the KnownZero/KnownOne bits to 855 // simplify things downstream. 856 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 857 return false; 858 } 859 // If this is the root being simplified, allow it to have multiple uses, 860 // just set the NewMask to all bits. 861 NewMask = APInt::getAllOnesValue(BitWidth); 862 } else if (DemandedMask == 0) { 863 // Not demanding any bits from Op. 864 if (Op.getOpcode() != ISD::UNDEF) 865 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 866 return false; 867 } else if (Depth == 6) { // Limit search depth. 868 return false; 869 } 870 871 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 872 switch (Op.getOpcode()) { 873 case ISD::Constant: 874 // We know all of the bits for a constant! 875 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 876 KnownZero = ~KnownOne & NewMask; 877 return false; // Don't fall through, will infinitely loop. 878 case ISD::AND: 879 // If the RHS is a constant, check to see if the LHS would be zero without 880 // using the bits from the RHS. Below, we use knowledge about the RHS to 881 // simplify the LHS, here we're using information from the LHS to simplify 882 // the RHS. 883 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 884 APInt LHSZero, LHSOne; 885 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 886 LHSZero, LHSOne, Depth+1); 887 // If the LHS already has zeros where RHSC does, this and is dead. 888 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 889 return TLO.CombineTo(Op, Op.getOperand(0)); 890 // If any of the set bits in the RHS are known zero on the LHS, shrink 891 // the constant. 892 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 893 return true; 894 } 895 896 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 897 KnownOne, TLO, Depth+1)) 898 return true; 899 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 900 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 901 KnownZero2, KnownOne2, TLO, Depth+1)) 902 return true; 903 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 904 905 // If all of the demanded bits are known one on one side, return the other. 906 // These bits cannot contribute to the result of the 'and'. 907 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 908 return TLO.CombineTo(Op, Op.getOperand(0)); 909 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 910 return TLO.CombineTo(Op, Op.getOperand(1)); 911 // If all of the demanded bits in the inputs are known zeros, return zero. 912 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 913 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 914 // If the RHS is a constant, see if we can simplify it. 915 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 916 return true; 917 // If the operation can be done in a smaller type, do so. 918 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 919 return true; 920 921 // Output known-1 bits are only known if set in both the LHS & RHS. 922 KnownOne &= KnownOne2; 923 // Output known-0 are known to be clear if zero in either the LHS | RHS. 924 KnownZero |= KnownZero2; 925 break; 926 case ISD::OR: 927 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 928 KnownOne, TLO, Depth+1)) 929 return true; 930 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 931 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 932 KnownZero2, KnownOne2, TLO, Depth+1)) 933 return true; 934 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 935 936 // If all of the demanded bits are known zero on one side, return the other. 937 // These bits cannot contribute to the result of the 'or'. 938 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 939 return TLO.CombineTo(Op, Op.getOperand(0)); 940 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 941 return TLO.CombineTo(Op, Op.getOperand(1)); 942 // If all of the potentially set bits on one side are known to be set on 943 // the other side, just use the 'other' side. 944 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 945 return TLO.CombineTo(Op, Op.getOperand(0)); 946 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 947 return TLO.CombineTo(Op, Op.getOperand(1)); 948 // If the RHS is a constant, see if we can simplify it. 949 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 950 return true; 951 // If the operation can be done in a smaller type, do so. 952 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 953 return true; 954 955 // Output known-0 bits are only known if clear in both the LHS & RHS. 956 KnownZero &= KnownZero2; 957 // Output known-1 are known to be set if set in either the LHS | RHS. 958 KnownOne |= KnownOne2; 959 break; 960 case ISD::XOR: 961 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 962 KnownOne, TLO, Depth+1)) 963 return true; 964 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 965 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 966 KnownOne2, TLO, Depth+1)) 967 return true; 968 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 969 970 // If all of the demanded bits are known zero on one side, return the other. 971 // These bits cannot contribute to the result of the 'xor'. 972 if ((KnownZero & NewMask) == NewMask) 973 return TLO.CombineTo(Op, Op.getOperand(0)); 974 if ((KnownZero2 & NewMask) == NewMask) 975 return TLO.CombineTo(Op, Op.getOperand(1)); 976 // If the operation can be done in a smaller type, do so. 977 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 978 return true; 979 980 // If all of the unknown bits are known to be zero on one side or the other 981 // (but not both) turn this into an *inclusive* or. 982 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 983 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 984 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 985 Op.getOperand(0), 986 Op.getOperand(1))); 987 988 // Output known-0 bits are known if clear or set in both the LHS & RHS. 989 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 990 // Output known-1 are known to be set if set in only one of the LHS, RHS. 991 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 992 993 // If all of the demanded bits on one side are known, and all of the set 994 // bits on that side are also known to be set on the other side, turn this 995 // into an AND, as we know the bits will be cleared. 996 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 997 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 998 if ((KnownOne & KnownOne2) == KnownOne) { 999 MVT VT = Op.getValueType(); 1000 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1001 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1002 Op.getOperand(0), ANDC)); 1003 } 1004 } 1005 1006 // If the RHS is a constant, see if we can simplify it. 1007 // for XOR, we prefer to force bits to 1 if they will make a -1. 1008 // if we can't force bits, try to shrink constant 1009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1010 APInt Expanded = C->getAPIntValue() | (~NewMask); 1011 // if we can expand it to have all bits set, do it 1012 if (Expanded.isAllOnesValue()) { 1013 if (Expanded != C->getAPIntValue()) { 1014 MVT VT = Op.getValueType(); 1015 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1016 TLO.DAG.getConstant(Expanded, VT)); 1017 return TLO.CombineTo(Op, New); 1018 } 1019 // if it already has all the bits set, nothing to change 1020 // but don't shrink either! 1021 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1022 return true; 1023 } 1024 } 1025 1026 KnownZero = KnownZeroOut; 1027 KnownOne = KnownOneOut; 1028 break; 1029 case ISD::SELECT: 1030 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1031 KnownOne, TLO, Depth+1)) 1032 return true; 1033 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1034 KnownOne2, TLO, Depth+1)) 1035 return true; 1036 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1037 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1038 1039 // If the operands are constants, see if we can simplify them. 1040 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1041 return true; 1042 1043 // Only known if known in both the LHS and RHS. 1044 KnownOne &= KnownOne2; 1045 KnownZero &= KnownZero2; 1046 break; 1047 case ISD::SELECT_CC: 1048 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1049 KnownOne, TLO, Depth+1)) 1050 return true; 1051 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1052 KnownOne2, TLO, Depth+1)) 1053 return true; 1054 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1055 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1056 1057 // If the operands are constants, see if we can simplify them. 1058 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1059 return true; 1060 1061 // Only known if known in both the LHS and RHS. 1062 KnownOne &= KnownOne2; 1063 KnownZero &= KnownZero2; 1064 break; 1065 case ISD::SHL: 1066 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1067 unsigned ShAmt = SA->getZExtValue(); 1068 SDValue InOp = Op.getOperand(0); 1069 1070 // If the shift count is an invalid immediate, don't do anything. 1071 if (ShAmt >= BitWidth) 1072 break; 1073 1074 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1075 // single shift. We can do this if the bottom bits (which are shifted 1076 // out) are never demanded. 1077 if (InOp.getOpcode() == ISD::SRL && 1078 isa<ConstantSDNode>(InOp.getOperand(1))) { 1079 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1080 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1081 unsigned Opc = ISD::SHL; 1082 int Diff = ShAmt-C1; 1083 if (Diff < 0) { 1084 Diff = -Diff; 1085 Opc = ISD::SRL; 1086 } 1087 1088 SDValue NewSA = 1089 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1090 MVT VT = Op.getValueType(); 1091 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1092 InOp.getOperand(0), NewSA)); 1093 } 1094 } 1095 1096 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1097 KnownZero, KnownOne, TLO, Depth+1)) 1098 return true; 1099 KnownZero <<= SA->getZExtValue(); 1100 KnownOne <<= SA->getZExtValue(); 1101 // low bits known zero. 1102 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1103 } 1104 break; 1105 case ISD::SRL: 1106 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1107 MVT VT = Op.getValueType(); 1108 unsigned ShAmt = SA->getZExtValue(); 1109 unsigned VTSize = VT.getSizeInBits(); 1110 SDValue InOp = Op.getOperand(0); 1111 1112 // If the shift count is an invalid immediate, don't do anything. 1113 if (ShAmt >= BitWidth) 1114 break; 1115 1116 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1117 // single shift. We can do this if the top bits (which are shifted out) 1118 // are never demanded. 1119 if (InOp.getOpcode() == ISD::SHL && 1120 isa<ConstantSDNode>(InOp.getOperand(1))) { 1121 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1122 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1123 unsigned Opc = ISD::SRL; 1124 int Diff = ShAmt-C1; 1125 if (Diff < 0) { 1126 Diff = -Diff; 1127 Opc = ISD::SHL; 1128 } 1129 1130 SDValue NewSA = 1131 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1132 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1133 InOp.getOperand(0), NewSA)); 1134 } 1135 } 1136 1137 // Compute the new bits that are at the top now. 1138 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1139 KnownZero, KnownOne, TLO, Depth+1)) 1140 return true; 1141 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1142 KnownZero = KnownZero.lshr(ShAmt); 1143 KnownOne = KnownOne.lshr(ShAmt); 1144 1145 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1146 KnownZero |= HighBits; // High bits known zero. 1147 } 1148 break; 1149 case ISD::SRA: 1150 // If this is an arithmetic shift right and only the low-bit is set, we can 1151 // always convert this into a logical shr, even if the shift amount is 1152 // variable. The low bit of the shift cannot be an input sign bit unless 1153 // the shift amount is >= the size of the datatype, which is undefined. 1154 if (DemandedMask == 1) 1155 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1156 Op.getOperand(0), Op.getOperand(1))); 1157 1158 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1159 MVT VT = Op.getValueType(); 1160 unsigned ShAmt = SA->getZExtValue(); 1161 1162 // If the shift count is an invalid immediate, don't do anything. 1163 if (ShAmt >= BitWidth) 1164 break; 1165 1166 APInt InDemandedMask = (NewMask << ShAmt); 1167 1168 // If any of the demanded bits are produced by the sign extension, we also 1169 // demand the input sign bit. 1170 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1171 if (HighBits.intersects(NewMask)) 1172 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1173 1174 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1175 KnownZero, KnownOne, TLO, Depth+1)) 1176 return true; 1177 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1178 KnownZero = KnownZero.lshr(ShAmt); 1179 KnownOne = KnownOne.lshr(ShAmt); 1180 1181 // Handle the sign bit, adjusted to where it is now in the mask. 1182 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1183 1184 // If the input sign bit is known to be zero, or if none of the top bits 1185 // are demanded, turn this into an unsigned shift right. 1186 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1187 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1188 Op.getOperand(0), 1189 Op.getOperand(1))); 1190 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1191 KnownOne |= HighBits; 1192 } 1193 } 1194 break; 1195 case ISD::SIGN_EXTEND_INREG: { 1196 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1197 1198 // Sign extension. Compute the demanded bits in the result that are not 1199 // present in the input. 1200 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1201 BitWidth - EVT.getSizeInBits()) & 1202 NewMask; 1203 1204 // If none of the extended bits are demanded, eliminate the sextinreg. 1205 if (NewBits == 0) 1206 return TLO.CombineTo(Op, Op.getOperand(0)); 1207 1208 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1209 InSignBit.zext(BitWidth); 1210 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1211 EVT.getSizeInBits()) & 1212 NewMask; 1213 1214 // Since the sign extended bits are demanded, we know that the sign 1215 // bit is demanded. 1216 InputDemandedBits |= InSignBit; 1217 1218 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1219 KnownZero, KnownOne, TLO, Depth+1)) 1220 return true; 1221 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1222 1223 // If the sign bit of the input is known set or clear, then we know the 1224 // top bits of the result. 1225 1226 // If the input sign bit is known zero, convert this into a zero extension. 1227 if (KnownZero.intersects(InSignBit)) 1228 return TLO.CombineTo(Op, 1229 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1230 1231 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1232 KnownOne |= NewBits; 1233 KnownZero &= ~NewBits; 1234 } else { // Input sign bit unknown 1235 KnownZero &= ~NewBits; 1236 KnownOne &= ~NewBits; 1237 } 1238 break; 1239 } 1240 case ISD::ZERO_EXTEND: { 1241 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1242 APInt InMask = NewMask; 1243 InMask.trunc(OperandBitWidth); 1244 1245 // If none of the top bits are demanded, convert this into an any_extend. 1246 APInt NewBits = 1247 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1248 if (!NewBits.intersects(NewMask)) 1249 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1250 Op.getValueType(), 1251 Op.getOperand(0))); 1252 1253 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1254 KnownZero, KnownOne, TLO, Depth+1)) 1255 return true; 1256 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1257 KnownZero.zext(BitWidth); 1258 KnownOne.zext(BitWidth); 1259 KnownZero |= NewBits; 1260 break; 1261 } 1262 case ISD::SIGN_EXTEND: { 1263 MVT InVT = Op.getOperand(0).getValueType(); 1264 unsigned InBits = InVT.getSizeInBits(); 1265 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1266 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1267 APInt NewBits = ~InMask & NewMask; 1268 1269 // If none of the top bits are demanded, convert this into an any_extend. 1270 if (NewBits == 0) 1271 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1272 Op.getValueType(), 1273 Op.getOperand(0))); 1274 1275 // Since some of the sign extended bits are demanded, we know that the sign 1276 // bit is demanded. 1277 APInt InDemandedBits = InMask & NewMask; 1278 InDemandedBits |= InSignBit; 1279 InDemandedBits.trunc(InBits); 1280 1281 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1282 KnownOne, TLO, Depth+1)) 1283 return true; 1284 KnownZero.zext(BitWidth); 1285 KnownOne.zext(BitWidth); 1286 1287 // If the sign bit is known zero, convert this to a zero extend. 1288 if (KnownZero.intersects(InSignBit)) 1289 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1290 Op.getValueType(), 1291 Op.getOperand(0))); 1292 1293 // If the sign bit is known one, the top bits match. 1294 if (KnownOne.intersects(InSignBit)) { 1295 KnownOne |= NewBits; 1296 KnownZero &= ~NewBits; 1297 } else { // Otherwise, top bits aren't known. 1298 KnownOne &= ~NewBits; 1299 KnownZero &= ~NewBits; 1300 } 1301 break; 1302 } 1303 case ISD::ANY_EXTEND: { 1304 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1305 APInt InMask = NewMask; 1306 InMask.trunc(OperandBitWidth); 1307 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1308 KnownZero, KnownOne, TLO, Depth+1)) 1309 return true; 1310 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1311 KnownZero.zext(BitWidth); 1312 KnownOne.zext(BitWidth); 1313 break; 1314 } 1315 case ISD::TRUNCATE: { 1316 // Simplify the input, using demanded bit information, and compute the known 1317 // zero/one bits live out. 1318 APInt TruncMask = NewMask; 1319 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1320 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1321 KnownZero, KnownOne, TLO, Depth+1)) 1322 return true; 1323 KnownZero.trunc(BitWidth); 1324 KnownOne.trunc(BitWidth); 1325 1326 // If the input is only used by this truncate, see if we can shrink it based 1327 // on the known demanded bits. 1328 if (Op.getOperand(0).getNode()->hasOneUse()) { 1329 SDValue In = Op.getOperand(0); 1330 unsigned InBitWidth = In.getValueSizeInBits(); 1331 switch (In.getOpcode()) { 1332 default: break; 1333 case ISD::SRL: 1334 // Shrink SRL by a constant if none of the high bits shifted in are 1335 // demanded. 1336 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1337 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1338 InBitWidth - BitWidth); 1339 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1340 HighBits.trunc(BitWidth); 1341 1342 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1343 // None of the shifted in bits are needed. Add a truncate of the 1344 // shift input, then shift it. 1345 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1346 Op.getValueType(), 1347 In.getOperand(0)); 1348 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1349 Op.getValueType(), 1350 NewTrunc, 1351 In.getOperand(1))); 1352 } 1353 } 1354 break; 1355 } 1356 } 1357 1358 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1359 break; 1360 } 1361 case ISD::AssertZext: { 1362 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1363 APInt InMask = APInt::getLowBitsSet(BitWidth, 1364 VT.getSizeInBits()); 1365 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1366 KnownZero, KnownOne, TLO, Depth+1)) 1367 return true; 1368 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1369 KnownZero |= ~InMask & NewMask; 1370 break; 1371 } 1372 case ISD::BIT_CONVERT: 1373#if 0 1374 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1375 // is demanded, turn this into a FGETSIGN. 1376 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1377 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1378 !MVT::isVector(Op.getOperand(0).getValueType())) { 1379 // Only do this xform if FGETSIGN is valid or if before legalize. 1380 if (!TLO.AfterLegalize || 1381 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1382 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1383 // place. We expect the SHL to be eliminated by other optimizations. 1384 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1385 Op.getOperand(0)); 1386 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1387 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1388 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1389 Sign, ShAmt)); 1390 } 1391 } 1392#endif 1393 break; 1394 case ISD::ADD: 1395 case ISD::MUL: 1396 case ISD::SUB: { 1397 // Add, Sub, and Mul don't demand any bits in positions beyond that 1398 // of the highest bit demanded of them. 1399 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1400 BitWidth - NewMask.countLeadingZeros()); 1401 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1402 KnownOne2, TLO, Depth+1)) 1403 return true; 1404 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1405 KnownOne2, TLO, Depth+1)) 1406 return true; 1407 // See if the operation should be performed at a smaller bit width. 1408 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1409 return true; 1410 } 1411 // FALL THROUGH 1412 default: 1413 // Just use ComputeMaskedBits to compute output bits. 1414 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1415 break; 1416 } 1417 1418 // If we know the value of all of the demanded bits, return this as a 1419 // constant. 1420 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1421 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1422 1423 return false; 1424} 1425 1426/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1427/// in Mask are known to be either zero or one and return them in the 1428/// KnownZero/KnownOne bitsets. 1429void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1430 const APInt &Mask, 1431 APInt &KnownZero, 1432 APInt &KnownOne, 1433 const SelectionDAG &DAG, 1434 unsigned Depth) const { 1435 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1436 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1437 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1438 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1439 "Should use MaskedValueIsZero if you don't know whether Op" 1440 " is a target node!"); 1441 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1442} 1443 1444/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1445/// targets that want to expose additional information about sign bits to the 1446/// DAG Combiner. 1447unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1448 unsigned Depth) const { 1449 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1450 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1451 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1452 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1453 "Should use ComputeNumSignBits if you don't know whether Op" 1454 " is a target node!"); 1455 return 1; 1456} 1457 1458/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1459/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1460/// determine which bit is set. 1461/// 1462static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1463 // A left-shift of a constant one will have exactly one bit set, because 1464 // shifting the bit off the end is undefined. 1465 if (Val.getOpcode() == ISD::SHL) 1466 if (ConstantSDNode *C = 1467 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1468 if (C->getAPIntValue() == 1) 1469 return true; 1470 1471 // Similarly, a right-shift of a constant sign-bit will have exactly 1472 // one bit set. 1473 if (Val.getOpcode() == ISD::SRL) 1474 if (ConstantSDNode *C = 1475 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1476 if (C->getAPIntValue().isSignBit()) 1477 return true; 1478 1479 // More could be done here, though the above checks are enough 1480 // to handle some common cases. 1481 1482 // Fall back to ComputeMaskedBits to catch other known cases. 1483 MVT OpVT = Val.getValueType(); 1484 unsigned BitWidth = OpVT.getSizeInBits(); 1485 APInt Mask = APInt::getAllOnesValue(BitWidth); 1486 APInt KnownZero, KnownOne; 1487 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1488 return (KnownZero.countPopulation() == BitWidth - 1) && 1489 (KnownOne.countPopulation() == 1); 1490} 1491 1492/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1493/// and cc. If it is unable to simplify it, return a null SDValue. 1494SDValue 1495TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1496 ISD::CondCode Cond, bool foldBooleans, 1497 DAGCombinerInfo &DCI, DebugLoc dl) const { 1498 SelectionDAG &DAG = DCI.DAG; 1499 1500 // These setcc operations always fold. 1501 switch (Cond) { 1502 default: break; 1503 case ISD::SETFALSE: 1504 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1505 case ISD::SETTRUE: 1506 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1507 } 1508 1509 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1510 const APInt &C1 = N1C->getAPIntValue(); 1511 if (isa<ConstantSDNode>(N0.getNode())) { 1512 return DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1513 } else { 1514 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1515 // equality comparison, then we're just comparing whether X itself is 1516 // zero. 1517 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1518 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1519 N0.getOperand(1).getOpcode() == ISD::Constant) { 1520 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1521 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1522 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1523 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1524 // (srl (ctlz x), 5) == 0 -> X != 0 1525 // (srl (ctlz x), 5) != 1 -> X != 0 1526 Cond = ISD::SETNE; 1527 } else { 1528 // (srl (ctlz x), 5) != 0 -> X == 0 1529 // (srl (ctlz x), 5) == 1 -> X == 0 1530 Cond = ISD::SETEQ; 1531 } 1532 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1533 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1534 Zero, Cond); 1535 } 1536 } 1537 1538 // If the LHS is '(and load, const)', the RHS is 0, 1539 // the test is for equality or unsigned, and all 1 bits of the const are 1540 // in the same partial word, see if we can shorten the load. 1541 if (DCI.isBeforeLegalize() && 1542 N0.getOpcode() == ISD::AND && C1 == 0 && 1543 N0.getNode()->hasOneUse() && 1544 isa<LoadSDNode>(N0.getOperand(0)) && 1545 N0.getOperand(0).getNode()->hasOneUse() && 1546 isa<ConstantSDNode>(N0.getOperand(1))) { 1547 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1548 uint64_t bestMask = 0; 1549 unsigned bestWidth = 0, bestOffset = 0; 1550 if (!Lod->isVolatile() && Lod->isUnindexed() && 1551 // FIXME: This uses getZExtValue() below so it only works on i64 and 1552 // below. 1553 N0.getValueType().getSizeInBits() <= 64) { 1554 unsigned origWidth = N0.getValueType().getSizeInBits(); 1555 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1556 // 8 bits, but have to be careful... 1557 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1558 origWidth = Lod->getMemoryVT().getSizeInBits(); 1559 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1560 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1561 uint64_t newMask = (1ULL << width) - 1; 1562 for (unsigned offset=0; offset<origWidth/width; offset++) { 1563 if ((newMask & Mask) == Mask) { 1564 if (!TD->isLittleEndian()) 1565 bestOffset = (origWidth/width - offset - 1) * (width/8); 1566 else 1567 bestOffset = (uint64_t)offset * (width/8); 1568 bestMask = Mask >> (offset * (width/8) * 8); 1569 bestWidth = width; 1570 break; 1571 } 1572 newMask = newMask << width; 1573 } 1574 } 1575 } 1576 if (bestWidth) { 1577 MVT newVT = MVT::getIntegerVT(bestWidth); 1578 if (newVT.isRound()) { 1579 MVT PtrType = Lod->getOperand(1).getValueType(); 1580 SDValue Ptr = Lod->getBasePtr(); 1581 if (bestOffset != 0) 1582 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1583 DAG.getConstant(bestOffset, PtrType)); 1584 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1585 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1586 Lod->getSrcValue(), 1587 Lod->getSrcValueOffset() + bestOffset, 1588 false, NewAlign); 1589 return DAG.getSetCC(dl, VT, 1590 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1591 DAG.getConstant(bestMask, newVT)), 1592 DAG.getConstant(0LL, newVT), Cond); 1593 } 1594 } 1595 } 1596 1597 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1598 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1599 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1600 1601 // If the comparison constant has bits in the upper part, the 1602 // zero-extended value could never match. 1603 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1604 C1.getBitWidth() - InSize))) { 1605 switch (Cond) { 1606 case ISD::SETUGT: 1607 case ISD::SETUGE: 1608 case ISD::SETEQ: return DAG.getConstant(0, VT); 1609 case ISD::SETULT: 1610 case ISD::SETULE: 1611 case ISD::SETNE: return DAG.getConstant(1, VT); 1612 case ISD::SETGT: 1613 case ISD::SETGE: 1614 // True if the sign bit of C1 is set. 1615 return DAG.getConstant(C1.isNegative(), VT); 1616 case ISD::SETLT: 1617 case ISD::SETLE: 1618 // True if the sign bit of C1 isn't set. 1619 return DAG.getConstant(C1.isNonNegative(), VT); 1620 default: 1621 break; 1622 } 1623 } 1624 1625 // Otherwise, we can perform the comparison with the low bits. 1626 switch (Cond) { 1627 case ISD::SETEQ: 1628 case ISD::SETNE: 1629 case ISD::SETUGT: 1630 case ISD::SETUGE: 1631 case ISD::SETULT: 1632 case ISD::SETULE: 1633 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1634 DAG.getConstant(APInt(C1).trunc(InSize), 1635 N0.getOperand(0).getValueType()), 1636 Cond); 1637 default: 1638 break; // todo, be more careful with signed comparisons 1639 } 1640 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1641 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1642 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1643 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1644 MVT ExtDstTy = N0.getValueType(); 1645 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1646 1647 // If the extended part has any inconsistent bits, it cannot ever 1648 // compare equal. In other words, they have to be all ones or all 1649 // zeros. 1650 APInt ExtBits = 1651 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1652 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1653 return DAG.getConstant(Cond == ISD::SETNE, VT); 1654 1655 SDValue ZextOp; 1656 MVT Op0Ty = N0.getOperand(0).getValueType(); 1657 if (Op0Ty == ExtSrcTy) { 1658 ZextOp = N0.getOperand(0); 1659 } else { 1660 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1661 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1662 DAG.getConstant(Imm, Op0Ty)); 1663 } 1664 if (!DCI.isCalledByLegalizer()) 1665 DCI.AddToWorklist(ZextOp.getNode()); 1666 // Otherwise, make this a use of a zext. 1667 return DAG.getSetCC(dl, VT, ZextOp, 1668 DAG.getConstant(C1 & APInt::getLowBitsSet( 1669 ExtDstTyBits, 1670 ExtSrcTyBits), 1671 ExtDstTy), 1672 Cond); 1673 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1674 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1675 1676 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1677 if (N0.getOpcode() == ISD::SETCC) { 1678 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1679 if (TrueWhenTrue) 1680 return N0; 1681 1682 // Invert the condition. 1683 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1684 CC = ISD::getSetCCInverse(CC, 1685 N0.getOperand(0).getValueType().isInteger()); 1686 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1687 } 1688 1689 if ((N0.getOpcode() == ISD::XOR || 1690 (N0.getOpcode() == ISD::AND && 1691 N0.getOperand(0).getOpcode() == ISD::XOR && 1692 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1693 isa<ConstantSDNode>(N0.getOperand(1)) && 1694 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1695 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1696 // can only do this if the top bits are known zero. 1697 unsigned BitWidth = N0.getValueSizeInBits(); 1698 if (DAG.MaskedValueIsZero(N0, 1699 APInt::getHighBitsSet(BitWidth, 1700 BitWidth-1))) { 1701 // Okay, get the un-inverted input value. 1702 SDValue Val; 1703 if (N0.getOpcode() == ISD::XOR) 1704 Val = N0.getOperand(0); 1705 else { 1706 assert(N0.getOpcode() == ISD::AND && 1707 N0.getOperand(0).getOpcode() == ISD::XOR); 1708 // ((X^1)&1)^1 -> X & 1 1709 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1710 N0.getOperand(0).getOperand(0), 1711 N0.getOperand(1)); 1712 } 1713 return DAG.getSetCC(dl, VT, Val, N1, 1714 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1715 } 1716 } 1717 } 1718 1719 APInt MinVal, MaxVal; 1720 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1721 if (ISD::isSignedIntSetCC(Cond)) { 1722 MinVal = APInt::getSignedMinValue(OperandBitSize); 1723 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1724 } else { 1725 MinVal = APInt::getMinValue(OperandBitSize); 1726 MaxVal = APInt::getMaxValue(OperandBitSize); 1727 } 1728 1729 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1730 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1731 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1732 // X >= C0 --> X > (C0-1) 1733 return DAG.getSetCC(dl, VT, N0, 1734 DAG.getConstant(C1-1, N1.getValueType()), 1735 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1736 } 1737 1738 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1739 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1740 // X <= C0 --> X < (C0+1) 1741 return DAG.getSetCC(dl, VT, N0, 1742 DAG.getConstant(C1+1, N1.getValueType()), 1743 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1744 } 1745 1746 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1747 return DAG.getConstant(0, VT); // X < MIN --> false 1748 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1749 return DAG.getConstant(1, VT); // X >= MIN --> true 1750 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1751 return DAG.getConstant(0, VT); // X > MAX --> false 1752 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1753 return DAG.getConstant(1, VT); // X <= MAX --> true 1754 1755 // Canonicalize setgt X, Min --> setne X, Min 1756 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1757 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1758 // Canonicalize setlt X, Max --> setne X, Max 1759 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1760 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1761 1762 // If we have setult X, 1, turn it into seteq X, 0 1763 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1764 return DAG.getSetCC(dl, VT, N0, 1765 DAG.getConstant(MinVal, N0.getValueType()), 1766 ISD::SETEQ); 1767 // If we have setugt X, Max-1, turn it into seteq X, Max 1768 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1769 return DAG.getSetCC(dl, VT, N0, 1770 DAG.getConstant(MaxVal, N0.getValueType()), 1771 ISD::SETEQ); 1772 1773 // If we have "setcc X, C0", check to see if we can shrink the immediate 1774 // by changing cc. 1775 1776 // SETUGT X, SINTMAX -> SETLT X, 0 1777 if (Cond == ISD::SETUGT && 1778 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1779 return DAG.getSetCC(dl, VT, N0, 1780 DAG.getConstant(0, N1.getValueType()), 1781 ISD::SETLT); 1782 1783 // SETULT X, SINTMIN -> SETGT X, -1 1784 if (Cond == ISD::SETULT && 1785 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1786 SDValue ConstMinusOne = 1787 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1788 N1.getValueType()); 1789 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1790 } 1791 1792 // Fold bit comparisons when we can. 1793 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1794 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1795 if (ConstantSDNode *AndRHS = 1796 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1797 MVT ShiftTy = DCI.isBeforeLegalize() ? 1798 getPointerTy() : getShiftAmountTy(); 1799 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1800 // Perform the xform if the AND RHS is a single bit. 1801 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1802 return DAG.getNode(ISD::SRL, dl, VT, N0, 1803 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1804 ShiftTy)); 1805 } 1806 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1807 // (X & 8) == 8 --> (X & 8) >> 3 1808 // Perform the xform if C1 is a single bit. 1809 if (C1.isPowerOf2()) { 1810 return DAG.getNode(ISD::SRL, dl, VT, N0, 1811 DAG.getConstant(C1.logBase2(), ShiftTy)); 1812 } 1813 } 1814 } 1815 } 1816 } else if (isa<ConstantSDNode>(N0.getNode())) { 1817 // Ensure that the constant occurs on the RHS. 1818 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1819 } 1820 1821 if (isa<ConstantFPSDNode>(N0.getNode())) { 1822 // Constant fold or commute setcc. 1823 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1824 if (O.getNode()) return O; 1825 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1826 // If the RHS of an FP comparison is a constant, simplify it away in 1827 // some cases. 1828 if (CFP->getValueAPF().isNaN()) { 1829 // If an operand is known to be a nan, we can fold it. 1830 switch (ISD::getUnorderedFlavor(Cond)) { 1831 default: assert(0 && "Unknown flavor!"); 1832 case 0: // Known false. 1833 return DAG.getConstant(0, VT); 1834 case 1: // Known true. 1835 return DAG.getConstant(1, VT); 1836 case 2: // Undefined. 1837 return DAG.getUNDEF(VT); 1838 } 1839 } 1840 1841 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1842 // constant if knowing that the operand is non-nan is enough. We prefer to 1843 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1844 // materialize 0.0. 1845 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1846 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1847 } 1848 1849 if (N0 == N1) { 1850 // We can always fold X == X for integer setcc's. 1851 if (N0.getValueType().isInteger()) 1852 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1853 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1854 if (UOF == 2) // FP operators that are undefined on NaNs. 1855 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1856 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1857 return DAG.getConstant(UOF, VT); 1858 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1859 // if it is not already. 1860 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1861 if (NewCond != Cond) 1862 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1863 } 1864 1865 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1866 N0.getValueType().isInteger()) { 1867 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1868 N0.getOpcode() == ISD::XOR) { 1869 // Simplify (X+Y) == (X+Z) --> Y == Z 1870 if (N0.getOpcode() == N1.getOpcode()) { 1871 if (N0.getOperand(0) == N1.getOperand(0)) 1872 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1873 if (N0.getOperand(1) == N1.getOperand(1)) 1874 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1875 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1876 // If X op Y == Y op X, try other combinations. 1877 if (N0.getOperand(0) == N1.getOperand(1)) 1878 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1879 Cond); 1880 if (N0.getOperand(1) == N1.getOperand(0)) 1881 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1882 Cond); 1883 } 1884 } 1885 1886 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1887 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1888 // Turn (X+C1) == C2 --> X == C2-C1 1889 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1890 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1891 DAG.getConstant(RHSC->getAPIntValue()- 1892 LHSR->getAPIntValue(), 1893 N0.getValueType()), Cond); 1894 } 1895 1896 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1897 if (N0.getOpcode() == ISD::XOR) 1898 // If we know that all of the inverted bits are zero, don't bother 1899 // performing the inversion. 1900 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1901 return 1902 DAG.getSetCC(dl, VT, N0.getOperand(0), 1903 DAG.getConstant(LHSR->getAPIntValue() ^ 1904 RHSC->getAPIntValue(), 1905 N0.getValueType()), 1906 Cond); 1907 } 1908 1909 // Turn (C1-X) == C2 --> X == C1-C2 1910 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1911 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1912 return 1913 DAG.getSetCC(dl, VT, N0.getOperand(1), 1914 DAG.getConstant(SUBC->getAPIntValue() - 1915 RHSC->getAPIntValue(), 1916 N0.getValueType()), 1917 Cond); 1918 } 1919 } 1920 } 1921 1922 // Simplify (X+Z) == X --> Z == 0 1923 if (N0.getOperand(0) == N1) 1924 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1925 DAG.getConstant(0, N0.getValueType()), Cond); 1926 if (N0.getOperand(1) == N1) { 1927 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1928 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1929 DAG.getConstant(0, N0.getValueType()), Cond); 1930 else if (N0.getNode()->hasOneUse()) { 1931 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1932 // (Z-X) == X --> Z == X<<1 1933 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1934 N1, 1935 DAG.getConstant(1, getShiftAmountTy())); 1936 if (!DCI.isCalledByLegalizer()) 1937 DCI.AddToWorklist(SH.getNode()); 1938 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1939 } 1940 } 1941 } 1942 1943 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1944 N1.getOpcode() == ISD::XOR) { 1945 // Simplify X == (X+Z) --> Z == 0 1946 if (N1.getOperand(0) == N0) { 1947 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1948 DAG.getConstant(0, N1.getValueType()), Cond); 1949 } else if (N1.getOperand(1) == N0) { 1950 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1951 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1952 DAG.getConstant(0, N1.getValueType()), Cond); 1953 } else if (N1.getNode()->hasOneUse()) { 1954 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1955 // X == (Z-X) --> X<<1 == Z 1956 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1957 DAG.getConstant(1, getShiftAmountTy())); 1958 if (!DCI.isCalledByLegalizer()) 1959 DCI.AddToWorklist(SH.getNode()); 1960 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1961 } 1962 } 1963 } 1964 1965 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1966 // Note that where y is variable and is known to have at most 1967 // one bit set (for example, if it is z&1) we cannot do this; 1968 // the expressions are not equivalent when y==0. 1969 if (N0.getOpcode() == ISD::AND) 1970 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1971 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1972 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1973 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1974 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1975 } 1976 } 1977 if (N1.getOpcode() == ISD::AND) 1978 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1979 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1980 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1981 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1982 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1983 } 1984 } 1985 } 1986 1987 // Fold away ALL boolean setcc's. 1988 SDValue Temp; 1989 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1990 switch (Cond) { 1991 default: assert(0 && "Unknown integer setcc!"); 1992 case ISD::SETEQ: // X == Y -> ~(X^Y) 1993 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1994 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1995 if (!DCI.isCalledByLegalizer()) 1996 DCI.AddToWorklist(Temp.getNode()); 1997 break; 1998 case ISD::SETNE: // X != Y --> (X^Y) 1999 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2000 break; 2001 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2002 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2003 Temp = DAG.getNOT(dl, N0, MVT::i1); 2004 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2005 if (!DCI.isCalledByLegalizer()) 2006 DCI.AddToWorklist(Temp.getNode()); 2007 break; 2008 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2009 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2010 Temp = DAG.getNOT(dl, N1, MVT::i1); 2011 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2012 if (!DCI.isCalledByLegalizer()) 2013 DCI.AddToWorklist(Temp.getNode()); 2014 break; 2015 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2016 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2017 Temp = DAG.getNOT(dl, N0, MVT::i1); 2018 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2019 if (!DCI.isCalledByLegalizer()) 2020 DCI.AddToWorklist(Temp.getNode()); 2021 break; 2022 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2023 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2024 Temp = DAG.getNOT(dl, N1, MVT::i1); 2025 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2026 break; 2027 } 2028 if (VT != MVT::i1) { 2029 if (!DCI.isCalledByLegalizer()) 2030 DCI.AddToWorklist(N0.getNode()); 2031 // FIXME: If running after legalize, we probably can't do this. 2032 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2033 } 2034 return N0; 2035 } 2036 2037 // Could not fold it. 2038 return SDValue(); 2039} 2040 2041/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2042/// node is a GlobalAddress + offset. 2043bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2044 int64_t &Offset) const { 2045 if (isa<GlobalAddressSDNode>(N)) { 2046 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2047 GA = GASD->getGlobal(); 2048 Offset += GASD->getOffset(); 2049 return true; 2050 } 2051 2052 if (N->getOpcode() == ISD::ADD) { 2053 SDValue N1 = N->getOperand(0); 2054 SDValue N2 = N->getOperand(1); 2055 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2056 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2057 if (V) { 2058 Offset += V->getSExtValue(); 2059 return true; 2060 } 2061 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2062 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2063 if (V) { 2064 Offset += V->getSExtValue(); 2065 return true; 2066 } 2067 } 2068 } 2069 return false; 2070} 2071 2072 2073/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 2074/// location that is 'Dist' units away from the location that the 'Base' load 2075/// is loading from. 2076bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, 2077 unsigned Bytes, int Dist, 2078 const MachineFrameInfo *MFI) const { 2079 if (LD->getChain() != Base->getChain()) 2080 return false; 2081 MVT VT = LD->getValueType(0); 2082 if (VT.getSizeInBits() / 8 != Bytes) 2083 return false; 2084 2085 SDValue Loc = LD->getOperand(1); 2086 SDValue BaseLoc = Base->getOperand(1); 2087 if (Loc.getOpcode() == ISD::FrameIndex) { 2088 if (BaseLoc.getOpcode() != ISD::FrameIndex) 2089 return false; 2090 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 2091 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 2092 int FS = MFI->getObjectSize(FI); 2093 int BFS = MFI->getObjectSize(BFI); 2094 if (FS != BFS || FS != (int)Bytes) return false; 2095 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 2096 } 2097 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) { 2098 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1)); 2099 if (V && (V->getSExtValue() == Dist*Bytes)) 2100 return true; 2101 } 2102 2103 GlobalValue *GV1 = NULL; 2104 GlobalValue *GV2 = NULL; 2105 int64_t Offset1 = 0; 2106 int64_t Offset2 = 0; 2107 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 2108 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 2109 if (isGA1 && isGA2 && GV1 == GV2) 2110 return Offset1 == (Offset2 + Dist*Bytes); 2111 return false; 2112} 2113 2114 2115SDValue TargetLowering:: 2116PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2117 // Default implementation: no optimization. 2118 return SDValue(); 2119} 2120 2121//===----------------------------------------------------------------------===// 2122// Inline Assembler Implementation Methods 2123//===----------------------------------------------------------------------===// 2124 2125 2126TargetLowering::ConstraintType 2127TargetLowering::getConstraintType(const std::string &Constraint) const { 2128 // FIXME: lots more standard ones to handle. 2129 if (Constraint.size() == 1) { 2130 switch (Constraint[0]) { 2131 default: break; 2132 case 'r': return C_RegisterClass; 2133 case 'm': // memory 2134 case 'o': // offsetable 2135 case 'V': // not offsetable 2136 return C_Memory; 2137 case 'i': // Simple Integer or Relocatable Constant 2138 case 'n': // Simple Integer 2139 case 's': // Relocatable Constant 2140 case 'X': // Allow ANY value. 2141 case 'I': // Target registers. 2142 case 'J': 2143 case 'K': 2144 case 'L': 2145 case 'M': 2146 case 'N': 2147 case 'O': 2148 case 'P': 2149 return C_Other; 2150 } 2151 } 2152 2153 if (Constraint.size() > 1 && Constraint[0] == '{' && 2154 Constraint[Constraint.size()-1] == '}') 2155 return C_Register; 2156 return C_Unknown; 2157} 2158 2159/// LowerXConstraint - try to replace an X constraint, which matches anything, 2160/// with another that has more specific requirements based on the type of the 2161/// corresponding operand. 2162const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2163 if (ConstraintVT.isInteger()) 2164 return "r"; 2165 if (ConstraintVT.isFloatingPoint()) 2166 return "f"; // works for many targets 2167 return 0; 2168} 2169 2170/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2171/// vector. If it is invalid, don't add anything to Ops. 2172void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2173 char ConstraintLetter, 2174 bool hasMemory, 2175 std::vector<SDValue> &Ops, 2176 SelectionDAG &DAG) const { 2177 switch (ConstraintLetter) { 2178 default: break; 2179 case 'X': // Allows any operand; labels (basic block) use this. 2180 if (Op.getOpcode() == ISD::BasicBlock) { 2181 Ops.push_back(Op); 2182 return; 2183 } 2184 // fall through 2185 case 'i': // Simple Integer or Relocatable Constant 2186 case 'n': // Simple Integer 2187 case 's': { // Relocatable Constant 2188 // These operands are interested in values of the form (GV+C), where C may 2189 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2190 // is possible and fine if either GV or C are missing. 2191 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2192 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2193 2194 // If we have "(add GV, C)", pull out GV/C 2195 if (Op.getOpcode() == ISD::ADD) { 2196 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2197 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2198 if (C == 0 || GA == 0) { 2199 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2200 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2201 } 2202 if (C == 0 || GA == 0) 2203 C = 0, GA = 0; 2204 } 2205 2206 // If we find a valid operand, map to the TargetXXX version so that the 2207 // value itself doesn't get selected. 2208 if (GA) { // Either &GV or &GV+C 2209 if (ConstraintLetter != 'n') { 2210 int64_t Offs = GA->getOffset(); 2211 if (C) Offs += C->getZExtValue(); 2212 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2213 Op.getValueType(), Offs)); 2214 return; 2215 } 2216 } 2217 if (C) { // just C, no GV. 2218 // Simple constants are not allowed for 's'. 2219 if (ConstraintLetter != 's') { 2220 // gcc prints these as sign extended. Sign extend value to 64 bits 2221 // now; without this it would get ZExt'd later in 2222 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2223 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2224 MVT::i64)); 2225 return; 2226 } 2227 } 2228 break; 2229 } 2230 } 2231} 2232 2233std::vector<unsigned> TargetLowering:: 2234getRegClassForInlineAsmConstraint(const std::string &Constraint, 2235 MVT VT) const { 2236 return std::vector<unsigned>(); 2237} 2238 2239 2240std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2241getRegForInlineAsmConstraint(const std::string &Constraint, 2242 MVT VT) const { 2243 if (Constraint[0] != '{') 2244 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2245 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2246 2247 // Remove the braces from around the name. 2248 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2249 2250 // Figure out which register class contains this reg. 2251 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2252 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2253 E = RI->regclass_end(); RCI != E; ++RCI) { 2254 const TargetRegisterClass *RC = *RCI; 2255 2256 // If none of the the value types for this register class are valid, we 2257 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2258 bool isLegal = false; 2259 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2260 I != E; ++I) { 2261 if (isTypeLegal(*I)) { 2262 isLegal = true; 2263 break; 2264 } 2265 } 2266 2267 if (!isLegal) continue; 2268 2269 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2270 I != E; ++I) { 2271 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2272 return std::make_pair(*I, RC); 2273 } 2274 } 2275 2276 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2277} 2278 2279//===----------------------------------------------------------------------===// 2280// Constraint Selection. 2281 2282/// isMatchingInputConstraint - Return true of this is an input operand that is 2283/// a matching constraint like "4". 2284bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2285 assert(!ConstraintCode.empty() && "No known constraint!"); 2286 return isdigit(ConstraintCode[0]); 2287} 2288 2289/// getMatchedOperand - If this is an input matching constraint, this method 2290/// returns the output operand it matches. 2291unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2292 assert(!ConstraintCode.empty() && "No known constraint!"); 2293 return atoi(ConstraintCode.c_str()); 2294} 2295 2296 2297/// getConstraintGenerality - Return an integer indicating how general CT 2298/// is. 2299static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2300 switch (CT) { 2301 default: assert(0 && "Unknown constraint type!"); 2302 case TargetLowering::C_Other: 2303 case TargetLowering::C_Unknown: 2304 return 0; 2305 case TargetLowering::C_Register: 2306 return 1; 2307 case TargetLowering::C_RegisterClass: 2308 return 2; 2309 case TargetLowering::C_Memory: 2310 return 3; 2311 } 2312} 2313 2314/// ChooseConstraint - If there are multiple different constraints that we 2315/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2316/// This is somewhat tricky: constraints fall into four classes: 2317/// Other -> immediates and magic values 2318/// Register -> one specific register 2319/// RegisterClass -> a group of regs 2320/// Memory -> memory 2321/// Ideally, we would pick the most specific constraint possible: if we have 2322/// something that fits into a register, we would pick it. The problem here 2323/// is that if we have something that could either be in a register or in 2324/// memory that use of the register could cause selection of *other* 2325/// operands to fail: they might only succeed if we pick memory. Because of 2326/// this the heuristic we use is: 2327/// 2328/// 1) If there is an 'other' constraint, and if the operand is valid for 2329/// that constraint, use it. This makes us take advantage of 'i' 2330/// constraints when available. 2331/// 2) Otherwise, pick the most general constraint present. This prefers 2332/// 'm' over 'r', for example. 2333/// 2334static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2335 bool hasMemory, const TargetLowering &TLI, 2336 SDValue Op, SelectionDAG *DAG) { 2337 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2338 unsigned BestIdx = 0; 2339 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2340 int BestGenerality = -1; 2341 2342 // Loop over the options, keeping track of the most general one. 2343 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2344 TargetLowering::ConstraintType CType = 2345 TLI.getConstraintType(OpInfo.Codes[i]); 2346 2347 // If this is an 'other' constraint, see if the operand is valid for it. 2348 // For example, on X86 we might have an 'rI' constraint. If the operand 2349 // is an integer in the range [0..31] we want to use I (saving a load 2350 // of a register), otherwise we must use 'r'. 2351 if (CType == TargetLowering::C_Other && Op.getNode()) { 2352 assert(OpInfo.Codes[i].size() == 1 && 2353 "Unhandled multi-letter 'other' constraint"); 2354 std::vector<SDValue> ResultOps; 2355 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2356 ResultOps, *DAG); 2357 if (!ResultOps.empty()) { 2358 BestType = CType; 2359 BestIdx = i; 2360 break; 2361 } 2362 } 2363 2364 // This constraint letter is more general than the previous one, use it. 2365 int Generality = getConstraintGenerality(CType); 2366 if (Generality > BestGenerality) { 2367 BestType = CType; 2368 BestIdx = i; 2369 BestGenerality = Generality; 2370 } 2371 } 2372 2373 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2374 OpInfo.ConstraintType = BestType; 2375} 2376 2377/// ComputeConstraintToUse - Determines the constraint code and constraint 2378/// type to use for the specific AsmOperandInfo, setting 2379/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2380void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2381 SDValue Op, 2382 bool hasMemory, 2383 SelectionDAG *DAG) const { 2384 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2385 2386 // Single-letter constraints ('r') are very common. 2387 if (OpInfo.Codes.size() == 1) { 2388 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2389 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2390 } else { 2391 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2392 } 2393 2394 // 'X' matches anything. 2395 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2396 // Labels and constants are handled elsewhere ('X' is the only thing 2397 // that matches labels). 2398 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2399 isa<ConstantInt>(OpInfo.CallOperandVal)) 2400 return; 2401 2402 // Otherwise, try to resolve it to something we know about by looking at 2403 // the actual operand type. 2404 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2405 OpInfo.ConstraintCode = Repl; 2406 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2407 } 2408 } 2409} 2410 2411//===----------------------------------------------------------------------===// 2412// Loop Strength Reduction hooks 2413//===----------------------------------------------------------------------===// 2414 2415/// isLegalAddressingMode - Return true if the addressing mode represented 2416/// by AM is legal for this target, for a load/store of the specified type. 2417bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2418 const Type *Ty) const { 2419 // The default implementation of this implements a conservative RISCy, r+r and 2420 // r+i addr mode. 2421 2422 // Allows a sign-extended 16-bit immediate field. 2423 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2424 return false; 2425 2426 // No global is ever allowed as a base. 2427 if (AM.BaseGV) 2428 return false; 2429 2430 // Only support r+r, 2431 switch (AM.Scale) { 2432 case 0: // "r+i" or just "i", depending on HasBaseReg. 2433 break; 2434 case 1: 2435 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2436 return false; 2437 // Otherwise we have r+r or r+i. 2438 break; 2439 case 2: 2440 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2441 return false; 2442 // Allow 2*r as r+r. 2443 break; 2444 } 2445 2446 return true; 2447} 2448 2449/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2450/// return a DAG expression to select that will generate the same value by 2451/// multiplying by a magic number. See: 2452/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2453SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2454 std::vector<SDNode*>* Created) const { 2455 MVT VT = N->getValueType(0); 2456 DebugLoc dl= N->getDebugLoc(); 2457 2458 // Check to see if we can do this. 2459 // FIXME: We should be more aggressive here. 2460 if (!isTypeLegal(VT)) 2461 return SDValue(); 2462 2463 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2464 APInt::ms magics = d.magic(); 2465 2466 // Multiply the numerator (operand 0) by the magic value 2467 // FIXME: We should support doing a MUL in a wider type 2468 SDValue Q; 2469 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2470 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2471 DAG.getConstant(magics.m, VT)); 2472 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2473 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2474 N->getOperand(0), 2475 DAG.getConstant(magics.m, VT)).getNode(), 1); 2476 else 2477 return SDValue(); // No mulhs or equvialent 2478 // If d > 0 and m < 0, add the numerator 2479 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2480 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2481 if (Created) 2482 Created->push_back(Q.getNode()); 2483 } 2484 // If d < 0 and m > 0, subtract the numerator. 2485 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2486 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2487 if (Created) 2488 Created->push_back(Q.getNode()); 2489 } 2490 // Shift right algebraic if shift value is nonzero 2491 if (magics.s > 0) { 2492 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2493 DAG.getConstant(magics.s, getShiftAmountTy())); 2494 if (Created) 2495 Created->push_back(Q.getNode()); 2496 } 2497 // Extract the sign bit and add it to the quotient 2498 SDValue T = 2499 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2500 getShiftAmountTy())); 2501 if (Created) 2502 Created->push_back(T.getNode()); 2503 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2504} 2505 2506/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2507/// return a DAG expression to select that will generate the same value by 2508/// multiplying by a magic number. See: 2509/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2510SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2511 std::vector<SDNode*>* Created) const { 2512 MVT VT = N->getValueType(0); 2513 DebugLoc dl = N->getDebugLoc(); 2514 2515 // Check to see if we can do this. 2516 // FIXME: We should be more aggressive here. 2517 if (!isTypeLegal(VT)) 2518 return SDValue(); 2519 2520 // FIXME: We should use a narrower constant when the upper 2521 // bits are known to be zero. 2522 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2523 APInt::mu magics = N1C->getAPIntValue().magicu(); 2524 2525 // Multiply the numerator (operand 0) by the magic value 2526 // FIXME: We should support doing a MUL in a wider type 2527 SDValue Q; 2528 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2529 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2530 DAG.getConstant(magics.m, VT)); 2531 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2532 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2533 N->getOperand(0), 2534 DAG.getConstant(magics.m, VT)).getNode(), 1); 2535 else 2536 return SDValue(); // No mulhu or equvialent 2537 if (Created) 2538 Created->push_back(Q.getNode()); 2539 2540 if (magics.a == 0) { 2541 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2542 "We shouldn't generate an undefined shift!"); 2543 return DAG.getNode(ISD::SRL, dl, VT, Q, 2544 DAG.getConstant(magics.s, getShiftAmountTy())); 2545 } else { 2546 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2547 if (Created) 2548 Created->push_back(NPQ.getNode()); 2549 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2550 DAG.getConstant(1, getShiftAmountTy())); 2551 if (Created) 2552 Created->push_back(NPQ.getNode()); 2553 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2554 if (Created) 2555 Created->push_back(NPQ.getNode()); 2556 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2557 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2558 } 2559} 2560 2561/// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET 2562/// node that don't prevent tail call optimization. 2563static SDValue IgnoreHarmlessInstructions(SDValue node) { 2564 // Found call return. 2565 if (node.getOpcode() == ISD::CALL) return node; 2566 // Ignore MERGE_VALUES. Will have at least one operand. 2567 if (node.getOpcode() == ISD::MERGE_VALUES) 2568 return IgnoreHarmlessInstructions(node.getOperand(0)); 2569 // Ignore ANY_EXTEND node. 2570 if (node.getOpcode() == ISD::ANY_EXTEND) 2571 return IgnoreHarmlessInstructions(node.getOperand(0)); 2572 if (node.getOpcode() == ISD::TRUNCATE) 2573 return IgnoreHarmlessInstructions(node.getOperand(0)); 2574 // Any other node type. 2575 return node; 2576} 2577 2578bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall, 2579 SDValue Ret) { 2580 unsigned NumOps = Ret.getNumOperands(); 2581 // ISD::CALL results:(value0, ..., valuen, chain) 2582 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn) 2583 // Value return: 2584 // Check that operand of the RET node sources from the CALL node. The RET node 2585 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the 2586 // value. 2587 if (NumOps > 1 && 2588 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0)) 2589 return true; 2590 // void return: The RET node has the chain result value of the CALL node as 2591 // input. 2592 if (NumOps == 1 && 2593 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2594 return true; 2595 2596 return false; 2597} 2598