LegalizeVectorOps.cpp revision 207618
1193323Sed//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the SelectionDAG::LegalizeVectors method. 11193323Sed// 12193323Sed// The vector legalizer looks for vector operations which might need to be 13193323Sed// scalarized and legalizes them. This is a separate step from Legalize because 14193323Sed// scalarizing can introduce illegal types. For example, suppose we have an 15193323Sed// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16193323Sed// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17193323Sed// operation, which introduces nodes with the illegal type i64 which must be 18193323Sed// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19193323Sed// the operation must be unrolled, which introduces nodes with the illegal 20193323Sed// type i8 which must be promoted. 21193323Sed// 22193323Sed// This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23198090Srdivacky// or operations that happen to take a vector which are custom-lowered; 24198090Srdivacky// the legalization for such operations never produces nodes 25193323Sed// with illegal types, so it's okay to put off legalizing them until 26193323Sed// SelectionDAG::Legalize runs. 27193323Sed// 28193323Sed//===----------------------------------------------------------------------===// 29193323Sed 30193323Sed#include "llvm/CodeGen/SelectionDAG.h" 31193323Sed#include "llvm/Target/TargetLowering.h" 32193323Sedusing namespace llvm; 33193323Sed 34193323Sednamespace { 35193323Sedclass VectorLegalizer { 36193323Sed SelectionDAG& DAG; 37207618Srdivacky const TargetLowering &TLI; 38193323Sed bool Changed; // Keep track of whether anything changed 39193323Sed 40193323Sed /// LegalizedNodes - For nodes that are of legal width, and that have more 41193323Sed /// than one use, this map indicates what regularized operand to use. This 42193323Sed /// allows us to avoid legalizing the same thing more than once. 43193323Sed DenseMap<SDValue, SDValue> LegalizedNodes; 44193323Sed 45193323Sed // Adds a node to the translation cache 46193323Sed void AddLegalizedOperand(SDValue From, SDValue To) { 47193323Sed LegalizedNodes.insert(std::make_pair(From, To)); 48193323Sed // If someone requests legalization of the new node, return itself. 49193323Sed if (From != To) 50193323Sed LegalizedNodes.insert(std::make_pair(To, To)); 51193323Sed } 52193323Sed 53193323Sed // Legalizes the given node 54193323Sed SDValue LegalizeOp(SDValue Op); 55193323Sed // Assuming the node is legal, "legalize" the results 56193323Sed SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 57193323Sed // Implements unrolling a VSETCC. 58193323Sed SDValue UnrollVSETCC(SDValue Op); 59193323Sed // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 60193323Sed // isn't legal. 61193323Sed SDValue ExpandFNEG(SDValue Op); 62193323Sed // Implements vector promotion; this is essentially just bitcasting the 63193323Sed // operands to a different type and bitcasting the result back to the 64193323Sed // original type. 65193323Sed SDValue PromoteVectorOp(SDValue Op); 66193323Sed 67193323Sed public: 68193323Sed bool Run(); 69193323Sed VectorLegalizer(SelectionDAG& dag) : 70193323Sed DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 71193323Sed}; 72193323Sed 73193323Sedbool VectorLegalizer::Run() { 74193323Sed // The legalize process is inherently a bottom-up recursive process (users 75193323Sed // legalize their uses before themselves). Given infinite stack space, we 76193323Sed // could just start legalizing on the root and traverse the whole graph. In 77193323Sed // practice however, this causes us to run out of stack space on large basic 78193323Sed // blocks. To avoid this problem, compute an ordering of the nodes where each 79193323Sed // node is only legalized after all of its operands are legalized. 80193323Sed DAG.AssignTopologicalOrder(); 81193323Sed for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 82200581Srdivacky E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 83193323Sed LegalizeOp(SDValue(I, 0)); 84193323Sed 85193323Sed // Finally, it's possible the root changed. Get the new root. 86193323Sed SDValue OldRoot = DAG.getRoot(); 87193323Sed assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 88193323Sed DAG.setRoot(LegalizedNodes[OldRoot]); 89193323Sed 90193323Sed LegalizedNodes.clear(); 91193323Sed 92193323Sed // Remove dead nodes now. 93193323Sed DAG.RemoveDeadNodes(); 94193323Sed 95193323Sed return Changed; 96193323Sed} 97193323Sed 98193323SedSDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 99193323Sed // Generic legalization: just pass the operand through. 100193323Sed for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 101193323Sed AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 102193323Sed return Result.getValue(Op.getResNo()); 103193323Sed} 104193323Sed 105193323SedSDValue VectorLegalizer::LegalizeOp(SDValue Op) { 106193323Sed // Note that LegalizeOp may be reentered even from single-use nodes, which 107193323Sed // means that we always must cache transformed nodes. 108193323Sed DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 109193323Sed if (I != LegalizedNodes.end()) return I->second; 110193323Sed 111193323Sed SDNode* Node = Op.getNode(); 112193323Sed 113193323Sed // Legalize the operands 114193323Sed SmallVector<SDValue, 8> Ops; 115193323Sed for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 116193323Sed Ops.push_back(LegalizeOp(Node->getOperand(i))); 117193323Sed 118193323Sed SDValue Result = 119193323Sed DAG.UpdateNodeOperands(Op.getValue(0), Ops.data(), Ops.size()); 120193323Sed 121193323Sed bool HasVectorValue = false; 122193323Sed for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 123193323Sed J != E; 124193323Sed ++J) 125193323Sed HasVectorValue |= J->isVector(); 126193323Sed if (!HasVectorValue) 127193323Sed return TranslateLegalizeResults(Op, Result); 128193323Sed 129198090Srdivacky EVT QueryType; 130193323Sed switch (Op.getOpcode()) { 131193323Sed default: 132193323Sed return TranslateLegalizeResults(Op, Result); 133193323Sed case ISD::ADD: 134193323Sed case ISD::SUB: 135193323Sed case ISD::MUL: 136193323Sed case ISD::SDIV: 137193323Sed case ISD::UDIV: 138193323Sed case ISD::SREM: 139193323Sed case ISD::UREM: 140193323Sed case ISD::FADD: 141193323Sed case ISD::FSUB: 142193323Sed case ISD::FMUL: 143193323Sed case ISD::FDIV: 144193323Sed case ISD::FREM: 145193323Sed case ISD::AND: 146193323Sed case ISD::OR: 147193323Sed case ISD::XOR: 148193323Sed case ISD::SHL: 149193323Sed case ISD::SRA: 150193323Sed case ISD::SRL: 151193323Sed case ISD::ROTL: 152193323Sed case ISD::ROTR: 153193323Sed case ISD::CTTZ: 154193323Sed case ISD::CTLZ: 155193323Sed case ISD::CTPOP: 156193323Sed case ISD::SELECT: 157193323Sed case ISD::SELECT_CC: 158193323Sed case ISD::VSETCC: 159193323Sed case ISD::ZERO_EXTEND: 160193323Sed case ISD::ANY_EXTEND: 161193323Sed case ISD::TRUNCATE: 162193323Sed case ISD::SIGN_EXTEND: 163193323Sed case ISD::FP_TO_SINT: 164193323Sed case ISD::FP_TO_UINT: 165193323Sed case ISD::FNEG: 166193323Sed case ISD::FABS: 167193323Sed case ISD::FSQRT: 168193323Sed case ISD::FSIN: 169193323Sed case ISD::FCOS: 170193323Sed case ISD::FPOWI: 171193323Sed case ISD::FPOW: 172193323Sed case ISD::FLOG: 173193323Sed case ISD::FLOG2: 174193323Sed case ISD::FLOG10: 175193323Sed case ISD::FEXP: 176193323Sed case ISD::FEXP2: 177193323Sed case ISD::FCEIL: 178193323Sed case ISD::FTRUNC: 179193323Sed case ISD::FRINT: 180193323Sed case ISD::FNEARBYINT: 181193323Sed case ISD::FFLOOR: 182193574Sed QueryType = Node->getValueType(0); 183193323Sed break; 184202375Srdivacky case ISD::SIGN_EXTEND_INREG: 185202375Srdivacky case ISD::FP_ROUND_INREG: 186202375Srdivacky QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 187202375Srdivacky break; 188193574Sed case ISD::SINT_TO_FP: 189193574Sed case ISD::UINT_TO_FP: 190193574Sed QueryType = Node->getOperand(0).getValueType(); 191193574Sed break; 192193323Sed } 193193323Sed 194193574Sed switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 195193323Sed case TargetLowering::Promote: 196193323Sed // "Promote" the operation by bitcasting 197193323Sed Result = PromoteVectorOp(Op); 198193323Sed Changed = true; 199193323Sed break; 200193323Sed case TargetLowering::Legal: break; 201193323Sed case TargetLowering::Custom: { 202193323Sed SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 203193323Sed if (Tmp1.getNode()) { 204193323Sed Result = Tmp1; 205193323Sed break; 206193323Sed } 207193323Sed // FALL THROUGH 208193323Sed } 209193323Sed case TargetLowering::Expand: 210193323Sed if (Node->getOpcode() == ISD::FNEG) 211193323Sed Result = ExpandFNEG(Op); 212193323Sed else if (Node->getOpcode() == ISD::VSETCC) 213193323Sed Result = UnrollVSETCC(Op); 214193323Sed else 215199989Srdivacky Result = DAG.UnrollVectorOp(Op.getNode()); 216193323Sed break; 217193323Sed } 218193323Sed 219193323Sed // Make sure that the generated code is itself legal. 220193323Sed if (Result != Op) { 221193323Sed Result = LegalizeOp(Result); 222193323Sed Changed = true; 223193323Sed } 224193323Sed 225193323Sed // Note that LegalizeOp may be reentered even from single-use nodes, which 226193323Sed // means that we always must cache transformed nodes. 227193323Sed AddLegalizedOperand(Op, Result); 228193323Sed return Result; 229193323Sed} 230193323Sed 231193323SedSDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { 232193323Sed // Vector "promotion" is basically just bitcasting and doing the operation 233193323Sed // in a different type. For example, x86 promotes ISD::AND on v2i32 to 234193323Sed // v1i64. 235198090Srdivacky EVT VT = Op.getValueType(); 236193323Sed assert(Op.getNode()->getNumValues() == 1 && 237193323Sed "Can't promote a vector with multiple results!"); 238198090Srdivacky EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 239193323Sed DebugLoc dl = Op.getDebugLoc(); 240193323Sed SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 241193323Sed 242193323Sed for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 243193323Sed if (Op.getOperand(j).getValueType().isVector()) 244193323Sed Operands[j] = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Op.getOperand(j)); 245193323Sed else 246193323Sed Operands[j] = Op.getOperand(j); 247193323Sed } 248193323Sed 249193323Sed Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); 250193323Sed 251193323Sed return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); 252193323Sed} 253193323Sed 254193323SedSDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 255193323Sed if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 256193323Sed SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 257193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 258193323Sed Zero, Op.getOperand(0)); 259193323Sed } 260199989Srdivacky return DAG.UnrollVectorOp(Op.getNode()); 261193323Sed} 262193323Sed 263193323SedSDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 264198090Srdivacky EVT VT = Op.getValueType(); 265193323Sed unsigned NumElems = VT.getVectorNumElements(); 266198090Srdivacky EVT EltVT = VT.getVectorElementType(); 267193323Sed SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 268198090Srdivacky EVT TmpEltVT = LHS.getValueType().getVectorElementType(); 269193323Sed DebugLoc dl = Op.getDebugLoc(); 270193323Sed SmallVector<SDValue, 8> Ops(NumElems); 271193323Sed for (unsigned i = 0; i < NumElems; ++i) { 272193323Sed SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 273193323Sed DAG.getIntPtrConstant(i)); 274193323Sed SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 275193323Sed DAG.getIntPtrConstant(i)); 276193323Sed Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 277193323Sed LHSElem, RHSElem, CC); 278193323Sed Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 279193323Sed DAG.getConstant(APInt::getAllOnesValue 280193323Sed (EltVT.getSizeInBits()), EltVT), 281193323Sed DAG.getConstant(0, EltVT)); 282193323Sed } 283193323Sed return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 284193323Sed} 285193323Sed 286193323Sed} 287193323Sed 288193323Sedbool SelectionDAG::LegalizeVectors() { 289193323Sed return VectorLegalizer(*this).Run(); 290193323Sed} 291