LegalizeVectorOps.cpp revision 193574
1193323Sed//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the SelectionDAG::LegalizeVectors method. 11193323Sed// 12193323Sed// The vector legalizer looks for vector operations which might need to be 13193323Sed// scalarized and legalizes them. This is a separate step from Legalize because 14193323Sed// scalarizing can introduce illegal types. For example, suppose we have an 15193323Sed// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16193323Sed// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17193323Sed// operation, which introduces nodes with the illegal type i64 which must be 18193323Sed// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19193323Sed// the operation must be unrolled, which introduces nodes with the illegal 20193323Sed// type i8 which must be promoted. 21193323Sed// 22193323Sed// This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23193323Sed// or operations that happen to take a vector which are custom-lowered like 24193323Sed// ISD::CALL; the legalization for such operations never produces nodes 25193323Sed// with illegal types, so it's okay to put off legalizing them until 26193323Sed// SelectionDAG::Legalize runs. 27193323Sed// 28193323Sed//===----------------------------------------------------------------------===// 29193323Sed 30193323Sed#include "llvm/CodeGen/SelectionDAG.h" 31193323Sed#include "llvm/Target/TargetLowering.h" 32193323Sedusing namespace llvm; 33193323Sed 34193323Sednamespace { 35193323Sedclass VectorLegalizer { 36193323Sed SelectionDAG& DAG; 37193323Sed TargetLowering& TLI; 38193323Sed bool Changed; // Keep track of whether anything changed 39193323Sed 40193323Sed /// LegalizedNodes - For nodes that are of legal width, and that have more 41193323Sed /// than one use, this map indicates what regularized operand to use. This 42193323Sed /// allows us to avoid legalizing the same thing more than once. 43193323Sed DenseMap<SDValue, SDValue> LegalizedNodes; 44193323Sed 45193323Sed // Adds a node to the translation cache 46193323Sed void AddLegalizedOperand(SDValue From, SDValue To) { 47193323Sed LegalizedNodes.insert(std::make_pair(From, To)); 48193323Sed // If someone requests legalization of the new node, return itself. 49193323Sed if (From != To) 50193323Sed LegalizedNodes.insert(std::make_pair(To, To)); 51193323Sed } 52193323Sed 53193323Sed // Legalizes the given node 54193323Sed SDValue LegalizeOp(SDValue Op); 55193323Sed // Assuming the node is legal, "legalize" the results 56193323Sed SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 57193323Sed // Implements unrolling a generic vector operation, i.e. turning it into 58193323Sed // scalar operations. 59193323Sed SDValue UnrollVectorOp(SDValue Op); 60193323Sed // Implements unrolling a VSETCC. 61193323Sed SDValue UnrollVSETCC(SDValue Op); 62193323Sed // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 63193323Sed // isn't legal. 64193323Sed SDValue ExpandFNEG(SDValue Op); 65193323Sed // Implements vector promotion; this is essentially just bitcasting the 66193323Sed // operands to a different type and bitcasting the result back to the 67193323Sed // original type. 68193323Sed SDValue PromoteVectorOp(SDValue Op); 69193323Sed 70193323Sed public: 71193323Sed bool Run(); 72193323Sed VectorLegalizer(SelectionDAG& dag) : 73193323Sed DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 74193323Sed}; 75193323Sed 76193323Sedbool VectorLegalizer::Run() { 77193323Sed // The legalize process is inherently a bottom-up recursive process (users 78193323Sed // legalize their uses before themselves). Given infinite stack space, we 79193323Sed // could just start legalizing on the root and traverse the whole graph. In 80193323Sed // practice however, this causes us to run out of stack space on large basic 81193323Sed // blocks. To avoid this problem, compute an ordering of the nodes where each 82193323Sed // node is only legalized after all of its operands are legalized. 83193323Sed DAG.AssignTopologicalOrder(); 84193323Sed for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 85193323Sed E = prior(DAG.allnodes_end()); I != next(E); ++I) 86193323Sed LegalizeOp(SDValue(I, 0)); 87193323Sed 88193323Sed // Finally, it's possible the root changed. Get the new root. 89193323Sed SDValue OldRoot = DAG.getRoot(); 90193323Sed assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 91193323Sed DAG.setRoot(LegalizedNodes[OldRoot]); 92193323Sed 93193323Sed LegalizedNodes.clear(); 94193323Sed 95193323Sed // Remove dead nodes now. 96193323Sed DAG.RemoveDeadNodes(); 97193323Sed 98193323Sed return Changed; 99193323Sed} 100193323Sed 101193323SedSDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 102193323Sed // Generic legalization: just pass the operand through. 103193323Sed for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 104193323Sed AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 105193323Sed return Result.getValue(Op.getResNo()); 106193323Sed} 107193323Sed 108193323SedSDValue VectorLegalizer::LegalizeOp(SDValue Op) { 109193323Sed // Note that LegalizeOp may be reentered even from single-use nodes, which 110193323Sed // means that we always must cache transformed nodes. 111193323Sed DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 112193323Sed if (I != LegalizedNodes.end()) return I->second; 113193323Sed 114193323Sed SDNode* Node = Op.getNode(); 115193323Sed 116193323Sed // Legalize the operands 117193323Sed SmallVector<SDValue, 8> Ops; 118193323Sed for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 119193323Sed Ops.push_back(LegalizeOp(Node->getOperand(i))); 120193323Sed 121193323Sed SDValue Result = 122193323Sed DAG.UpdateNodeOperands(Op.getValue(0), Ops.data(), Ops.size()); 123193323Sed 124193323Sed bool HasVectorValue = false; 125193323Sed for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 126193323Sed J != E; 127193323Sed ++J) 128193323Sed HasVectorValue |= J->isVector(); 129193323Sed if (!HasVectorValue) 130193323Sed return TranslateLegalizeResults(Op, Result); 131193323Sed 132193574Sed MVT QueryType; 133193323Sed switch (Op.getOpcode()) { 134193323Sed default: 135193323Sed return TranslateLegalizeResults(Op, Result); 136193323Sed case ISD::ADD: 137193323Sed case ISD::SUB: 138193323Sed case ISD::MUL: 139193323Sed case ISD::SDIV: 140193323Sed case ISD::UDIV: 141193323Sed case ISD::SREM: 142193323Sed case ISD::UREM: 143193323Sed case ISD::FADD: 144193323Sed case ISD::FSUB: 145193323Sed case ISD::FMUL: 146193323Sed case ISD::FDIV: 147193323Sed case ISD::FREM: 148193323Sed case ISD::AND: 149193323Sed case ISD::OR: 150193323Sed case ISD::XOR: 151193323Sed case ISD::SHL: 152193323Sed case ISD::SRA: 153193323Sed case ISD::SRL: 154193323Sed case ISD::ROTL: 155193323Sed case ISD::ROTR: 156193323Sed case ISD::CTTZ: 157193323Sed case ISD::CTLZ: 158193323Sed case ISD::CTPOP: 159193323Sed case ISD::SELECT: 160193323Sed case ISD::SELECT_CC: 161193323Sed case ISD::VSETCC: 162193323Sed case ISD::ZERO_EXTEND: 163193323Sed case ISD::ANY_EXTEND: 164193323Sed case ISD::TRUNCATE: 165193323Sed case ISD::SIGN_EXTEND: 166193323Sed case ISD::FP_TO_SINT: 167193323Sed case ISD::FP_TO_UINT: 168193323Sed case ISD::FNEG: 169193323Sed case ISD::FABS: 170193323Sed case ISD::FSQRT: 171193323Sed case ISD::FSIN: 172193323Sed case ISD::FCOS: 173193323Sed case ISD::FPOWI: 174193323Sed case ISD::FPOW: 175193323Sed case ISD::FLOG: 176193323Sed case ISD::FLOG2: 177193323Sed case ISD::FLOG10: 178193323Sed case ISD::FEXP: 179193323Sed case ISD::FEXP2: 180193323Sed case ISD::FCEIL: 181193323Sed case ISD::FTRUNC: 182193323Sed case ISD::FRINT: 183193323Sed case ISD::FNEARBYINT: 184193323Sed case ISD::FFLOOR: 185193574Sed QueryType = Node->getValueType(0); 186193323Sed break; 187193574Sed case ISD::SINT_TO_FP: 188193574Sed case ISD::UINT_TO_FP: 189193574Sed QueryType = Node->getOperand(0).getValueType(); 190193574Sed break; 191193323Sed } 192193323Sed 193193574Sed switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 194193323Sed case TargetLowering::Promote: 195193323Sed // "Promote" the operation by bitcasting 196193323Sed Result = PromoteVectorOp(Op); 197193323Sed Changed = true; 198193323Sed break; 199193323Sed case TargetLowering::Legal: break; 200193323Sed case TargetLowering::Custom: { 201193323Sed SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 202193323Sed if (Tmp1.getNode()) { 203193323Sed Result = Tmp1; 204193323Sed break; 205193323Sed } 206193323Sed // FALL THROUGH 207193323Sed } 208193323Sed case TargetLowering::Expand: 209193323Sed if (Node->getOpcode() == ISD::FNEG) 210193323Sed Result = ExpandFNEG(Op); 211193323Sed else if (Node->getOpcode() == ISD::VSETCC) 212193323Sed Result = UnrollVSETCC(Op); 213193323Sed else 214193323Sed Result = UnrollVectorOp(Op); 215193323Sed break; 216193323Sed } 217193323Sed 218193323Sed // Make sure that the generated code is itself legal. 219193323Sed if (Result != Op) { 220193323Sed Result = LegalizeOp(Result); 221193323Sed Changed = true; 222193323Sed } 223193323Sed 224193323Sed // Note that LegalizeOp may be reentered even from single-use nodes, which 225193323Sed // means that we always must cache transformed nodes. 226193323Sed AddLegalizedOperand(Op, Result); 227193323Sed return Result; 228193323Sed} 229193323Sed 230193323SedSDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { 231193323Sed // Vector "promotion" is basically just bitcasting and doing the operation 232193323Sed // in a different type. For example, x86 promotes ISD::AND on v2i32 to 233193323Sed // v1i64. 234193323Sed MVT VT = Op.getValueType(); 235193323Sed assert(Op.getNode()->getNumValues() == 1 && 236193323Sed "Can't promote a vector with multiple results!"); 237193323Sed MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 238193323Sed DebugLoc dl = Op.getDebugLoc(); 239193323Sed SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 240193323Sed 241193323Sed for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 242193323Sed if (Op.getOperand(j).getValueType().isVector()) 243193323Sed Operands[j] = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Op.getOperand(j)); 244193323Sed else 245193323Sed Operands[j] = Op.getOperand(j); 246193323Sed } 247193323Sed 248193323Sed Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); 249193323Sed 250193323Sed return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); 251193323Sed} 252193323Sed 253193323SedSDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 254193323Sed if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 255193323Sed SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 256193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 257193323Sed Zero, Op.getOperand(0)); 258193323Sed } 259193323Sed return UnrollVectorOp(Op); 260193323Sed} 261193323Sed 262193323SedSDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 263193323Sed MVT VT = Op.getValueType(); 264193323Sed unsigned NumElems = VT.getVectorNumElements(); 265193323Sed MVT EltVT = VT.getVectorElementType(); 266193323Sed SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 267193323Sed MVT TmpEltVT = LHS.getValueType().getVectorElementType(); 268193323Sed DebugLoc dl = Op.getDebugLoc(); 269193323Sed SmallVector<SDValue, 8> Ops(NumElems); 270193323Sed for (unsigned i = 0; i < NumElems; ++i) { 271193323Sed SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 272193323Sed DAG.getIntPtrConstant(i)); 273193323Sed SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 274193323Sed DAG.getIntPtrConstant(i)); 275193323Sed Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 276193323Sed LHSElem, RHSElem, CC); 277193323Sed Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 278193323Sed DAG.getConstant(APInt::getAllOnesValue 279193323Sed (EltVT.getSizeInBits()), EltVT), 280193323Sed DAG.getConstant(0, EltVT)); 281193323Sed } 282193323Sed return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 283193323Sed} 284193323Sed 285193323Sed/// UnrollVectorOp - We know that the given vector has a legal type, however 286193323Sed/// the operation it performs is not legal, and the target has requested that 287193323Sed/// the operation be expanded. "Unroll" the vector, splitting out the scalars 288193323Sed/// and operating on each element individually. 289193323SedSDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { 290193323Sed MVT VT = Op.getValueType(); 291193323Sed assert(Op.getNode()->getNumValues() == 1 && 292193323Sed "Can't unroll a vector with multiple results!"); 293193323Sed unsigned NE = VT.getVectorNumElements(); 294193323Sed MVT EltVT = VT.getVectorElementType(); 295193323Sed DebugLoc dl = Op.getDebugLoc(); 296193323Sed 297193323Sed SmallVector<SDValue, 8> Scalars; 298193323Sed SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 299193323Sed for (unsigned i = 0; i != NE; ++i) { 300193323Sed for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 301193323Sed SDValue Operand = Op.getOperand(j); 302193323Sed MVT OperandVT = Operand.getValueType(); 303193323Sed if (OperandVT.isVector()) { 304193323Sed // A vector operand; extract a single element. 305193323Sed MVT OperandEltVT = OperandVT.getVectorElementType(); 306193323Sed Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 307193323Sed OperandEltVT, 308193323Sed Operand, 309193323Sed DAG.getConstant(i, MVT::i32)); 310193323Sed } else { 311193323Sed // A scalar operand; just use it as is. 312193323Sed Operands[j] = Operand; 313193323Sed } 314193323Sed } 315193323Sed 316193323Sed switch (Op.getOpcode()) { 317193323Sed default: 318193323Sed Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, 319193323Sed &Operands[0], Operands.size())); 320193323Sed break; 321193323Sed case ISD::SHL: 322193323Sed case ISD::SRA: 323193323Sed case ISD::SRL: 324193323Sed case ISD::ROTL: 325193323Sed case ISD::ROTR: 326193323Sed Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], 327193323Sed DAG.getShiftAmountOperand(Operands[1]))); 328193323Sed break; 329193323Sed } 330193323Sed } 331193323Sed 332193323Sed return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); 333193323Sed} 334193323Sed 335193323Sed} 336193323Sed 337193323Sedbool SelectionDAG::LegalizeVectors() { 338193323Sed return VectorLegalizer(*this).Run(); 339193323Sed} 340