Passes.cpp revision 234353
1//===-- Passes.cpp - Target independent code generation passes ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code 11// generation passes provided by the LLVM backend. 12// 13//===---------------------------------------------------------------------===// 14 15#include "llvm/Analysis/Passes.h" 16#include "llvm/Analysis/Verifier.h" 17#include "llvm/Transforms/Scalar.h" 18#include "llvm/PassManager.h" 19#include "llvm/CodeGen/GCStrategy.h" 20#include "llvm/CodeGen/MachineFunctionPass.h" 21#include "llvm/CodeGen/Passes.h" 22#include "llvm/CodeGen/RegAllocRegistry.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Assembly/PrintModulePass.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Debug.h" 28#include "llvm/Support/ErrorHandling.h" 29 30using namespace llvm; 31 32static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 33 cl::desc("Disable Post Regalloc")); 34static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 35 cl::desc("Disable branch folding")); 36static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 37 cl::desc("Disable tail duplication")); 38static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 39 cl::desc("Disable pre-register allocation tail duplication")); 40static cl::opt<bool> EnableBlockPlacement("enable-block-placement", 41 cl::Hidden, cl::desc("Enable probability-driven block placement")); 42static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 43 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 44static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden, 45 cl::desc("Disable code placement")); 46static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 47 cl::desc("Disable Stack Slot Coloring")); 48static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 49 cl::desc("Disable Machine Dead Code Elimination")); 50static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 51 cl::desc("Disable Machine LICM")); 52static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 53 cl::desc("Disable Machine Common Subexpression Elimination")); 54static cl::opt<cl::boolOrDefault> 55OptimizeRegAlloc("optimize-regalloc", cl::Hidden, 56 cl::desc("Enable optimized register allocation compilation path.")); 57static cl::opt<cl::boolOrDefault> 58EnableMachineSched("enable-misched", cl::Hidden, 59 cl::desc("Enable the machine instruction scheduling pass.")); 60static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden, 61 cl::desc("Use strong PHI elimination.")); 62static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 63 cl::Hidden, 64 cl::desc("Disable Machine LICM")); 65static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 66 cl::desc("Disable Machine Sinking")); 67static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 68 cl::desc("Disable Loop Strength Reduction Pass")); 69static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 70 cl::desc("Disable Codegen Prepare")); 71static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 72 cl::desc("Disable Copy Propagation pass")); 73static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 74 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 75static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 76 cl::desc("Print LLVM IR input to isel pass")); 77static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 78 cl::desc("Dump garbage collector data")); 79static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 80 cl::desc("Verify generated machine code"), 81 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); 82 83/// Allow standard passes to be disabled by command line options. This supports 84/// simple binary flags that either suppress the pass or do nothing. 85/// i.e. -disable-mypass=false has no effect. 86/// These should be converted to boolOrDefault in order to use applyOverride. 87static AnalysisID applyDisable(AnalysisID ID, bool Override) { 88 if (Override) 89 return &NoPassID; 90 return ID; 91} 92 93/// Allow Pass selection to be overriden by command line options. This supports 94/// flags with ternary conditions. TargetID is passed through by default. The 95/// pass is suppressed when the option is false. When the option is true, the 96/// StandardID is selected if the target provides no default. 97static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override, 98 AnalysisID StandardID) { 99 switch (Override) { 100 case cl::BOU_UNSET: 101 return TargetID; 102 case cl::BOU_TRUE: 103 if (TargetID != &NoPassID) 104 return TargetID; 105 if (StandardID == &NoPassID) 106 report_fatal_error("Target cannot enable pass"); 107 return StandardID; 108 case cl::BOU_FALSE: 109 return &NoPassID; 110 } 111 llvm_unreachable("Invalid command line option state"); 112} 113 114/// Allow standard passes to be disabled by the command line, regardless of who 115/// is adding the pass. 116/// 117/// StandardID is the pass identified in the standard pass pipeline and provided 118/// to addPass(). It may be a target-specific ID in the case that the target 119/// directly adds its own pass, but in that case we harmlessly fall through. 120/// 121/// TargetID is the pass that the target has configured to override StandardID. 122/// 123/// StandardID may be a pseudo ID. In that case TargetID is the name of the real 124/// pass to run. This allows multiple options to control a single pass depending 125/// on where in the pipeline that pass is added. 126static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) { 127 if (StandardID == &PostRASchedulerID) 128 return applyDisable(TargetID, DisablePostRA); 129 130 if (StandardID == &BranchFolderPassID) 131 return applyDisable(TargetID, DisableBranchFold); 132 133 if (StandardID == &TailDuplicateID) 134 return applyDisable(TargetID, DisableTailDuplicate); 135 136 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID) 137 return applyDisable(TargetID, DisableEarlyTailDup); 138 139 if (StandardID == &MachineBlockPlacementID) 140 return applyDisable(TargetID, DisableCodePlace); 141 142 if (StandardID == &CodePlacementOptID) 143 return applyDisable(TargetID, DisableCodePlace); 144 145 if (StandardID == &StackSlotColoringID) 146 return applyDisable(TargetID, DisableSSC); 147 148 if (StandardID == &DeadMachineInstructionElimID) 149 return applyDisable(TargetID, DisableMachineDCE); 150 151 if (StandardID == &MachineLICMID) 152 return applyDisable(TargetID, DisableMachineLICM); 153 154 if (StandardID == &MachineCSEID) 155 return applyDisable(TargetID, DisableMachineCSE); 156 157 if (StandardID == &MachineSchedulerID) 158 return applyOverride(TargetID, EnableMachineSched, StandardID); 159 160 if (StandardID == &TargetPassConfig::PostRAMachineLICMID) 161 return applyDisable(TargetID, DisablePostRAMachineLICM); 162 163 if (StandardID == &MachineSinkingID) 164 return applyDisable(TargetID, DisableMachineSink); 165 166 if (StandardID == &MachineCopyPropagationID) 167 return applyDisable(TargetID, DisableCopyProp); 168 169 return TargetID; 170} 171 172//===---------------------------------------------------------------------===// 173/// TargetPassConfig 174//===---------------------------------------------------------------------===// 175 176INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 177 "Target Pass Configuration", false, false) 178char TargetPassConfig::ID = 0; 179 180static char NoPassIDAnchor = 0; 181char &llvm::NoPassID = NoPassIDAnchor; 182 183// Pseudo Pass IDs. 184char TargetPassConfig::EarlyTailDuplicateID = 0; 185char TargetPassConfig::PostRAMachineLICMID = 0; 186 187namespace llvm { 188class PassConfigImpl { 189public: 190 // List of passes explicitly substituted by this target. Normally this is 191 // empty, but it is a convenient way to suppress or replace specific passes 192 // that are part of a standard pass pipeline without overridding the entire 193 // pipeline. This mechanism allows target options to inherit a standard pass's 194 // user interface. For example, a target may disable a standard pass by 195 // default by substituting NoPass, and the user may still enable that standard 196 // pass with an explicit command line option. 197 DenseMap<AnalysisID,AnalysisID> TargetPasses; 198}; 199} // namespace llvm 200 201// Out of line virtual method. 202TargetPassConfig::~TargetPassConfig() { 203 delete Impl; 204} 205 206// Out of line constructor provides default values for pass options and 207// registers all common codegen passes. 208TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) 209 : ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false), 210 DisableVerify(false), 211 EnableTailMerge(true) { 212 213 Impl = new PassConfigImpl(); 214 215 // Register all target independent codegen passes to activate their PassIDs, 216 // including this pass itself. 217 initializeCodeGen(*PassRegistry::getPassRegistry()); 218 219 // Substitute Pseudo Pass IDs for real ones. 220 substitutePass(EarlyTailDuplicateID, TailDuplicateID); 221 substitutePass(PostRAMachineLICMID, MachineLICMID); 222 223 // Temporarily disable experimental passes. 224 substitutePass(MachineSchedulerID, NoPassID); 225} 226 227/// createPassConfig - Create a pass configuration object to be used by 228/// addPassToEmitX methods for generating a pipeline of CodeGen passes. 229/// 230/// Targets may override this to extend TargetPassConfig. 231TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 232 return new TargetPassConfig(this, PM); 233} 234 235TargetPassConfig::TargetPassConfig() 236 : ImmutablePass(ID), PM(*(PassManagerBase*)0) { 237 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); 238} 239 240// Helper to verify the analysis is really immutable. 241void TargetPassConfig::setOpt(bool &Opt, bool Val) { 242 assert(!Initialized && "PassConfig is immutable"); 243 Opt = Val; 244} 245 246void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) { 247 Impl->TargetPasses[&StandardID] = &TargetID; 248} 249 250AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 251 DenseMap<AnalysisID, AnalysisID>::const_iterator 252 I = Impl->TargetPasses.find(ID); 253 if (I == Impl->TargetPasses.end()) 254 return ID; 255 return I->second; 256} 257 258/// Add a CodeGen pass at this point in the pipeline after checking for target 259/// and command line overrides. 260AnalysisID TargetPassConfig::addPass(char &ID) { 261 assert(!Initialized && "PassConfig is immutable"); 262 263 AnalysisID TargetID = getPassSubstitution(&ID); 264 AnalysisID FinalID = overridePass(&ID, TargetID); 265 if (FinalID == &NoPassID) 266 return FinalID; 267 268 Pass *P = Pass::createPass(FinalID); 269 if (!P) 270 llvm_unreachable("Pass ID not registered"); 271 PM.add(P); 272 return FinalID; 273} 274 275void TargetPassConfig::printAndVerify(const char *Banner) const { 276 if (TM->shouldPrintMachineCode()) 277 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); 278 279 if (VerifyMachineCode) 280 PM.add(createMachineVerifierPass(Banner)); 281} 282 283/// Add common target configurable passes that perform LLVM IR to IR transforms 284/// following machine independent optimization. 285void TargetPassConfig::addIRPasses() { 286 // Basic AliasAnalysis support. 287 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 288 // BasicAliasAnalysis wins if they disagree. This is intended to help 289 // support "obvious" type-punning idioms. 290 PM.add(createTypeBasedAliasAnalysisPass()); 291 PM.add(createBasicAliasAnalysisPass()); 292 293 // Before running any passes, run the verifier to determine if the input 294 // coming from the front-end and/or optimizer is valid. 295 if (!DisableVerify) 296 PM.add(createVerifierPass()); 297 298 // Run loop strength reduction before anything else. 299 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 300 PM.add(createLoopStrengthReducePass(getTargetLowering())); 301 if (PrintLSR) 302 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 303 } 304 305 PM.add(createGCLoweringPass()); 306 307 // Make sure that no unreachable blocks are instruction selected. 308 PM.add(createUnreachableBlockEliminationPass()); 309} 310 311/// Add common passes that perform LLVM IR to IR transforms in preparation for 312/// instruction selection. 313void TargetPassConfig::addISelPrepare() { 314 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 315 PM.add(createCodeGenPreparePass(getTargetLowering())); 316 317 PM.add(createStackProtectorPass(getTargetLowering())); 318 319 addPreISel(); 320 321 if (PrintISelInput) 322 PM.add(createPrintFunctionPass("\n\n" 323 "*** Final LLVM Code input to ISel ***\n", 324 &dbgs())); 325 326 // All passes which modify the LLVM IR are now complete; run the verifier 327 // to ensure that the IR is valid. 328 if (!DisableVerify) 329 PM.add(createVerifierPass()); 330} 331 332/// Add the complete set of target-independent postISel code generator passes. 333/// 334/// This can be read as the standard order of major LLVM CodeGen stages. Stages 335/// with nontrivial configuration or multiple passes are broken out below in 336/// add%Stage routines. 337/// 338/// Any TargetPassConfig::addXX routine may be overriden by the Target. The 339/// addPre/Post methods with empty header implementations allow injecting 340/// target-specific fixups just before or after major stages. Additionally, 341/// targets have the flexibility to change pass order within a stage by 342/// overriding default implementation of add%Stage routines below. Each 343/// technique has maintainability tradeoffs because alternate pass orders are 344/// not well supported. addPre/Post works better if the target pass is easily 345/// tied to a common pass. But if it has subtle dependencies on multiple passes, 346/// the target should override the stage instead. 347/// 348/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 349/// before/after any target-independent pass. But it's currently overkill. 350void TargetPassConfig::addMachinePasses() { 351 // Print the instruction selected machine code... 352 printAndVerify("After Instruction Selection"); 353 354 // Expand pseudo-instructions emitted by ISel. 355 addPass(ExpandISelPseudosID); 356 357 // Add passes that optimize machine instructions in SSA form. 358 if (getOptLevel() != CodeGenOpt::None) { 359 addMachineSSAOptimization(); 360 } 361 else { 362 // If the target requests it, assign local variables to stack slots relative 363 // to one another and simplify frame index references where possible. 364 addPass(LocalStackSlotAllocationID); 365 } 366 367 // Run pre-ra passes. 368 if (addPreRegAlloc()) 369 printAndVerify("After PreRegAlloc passes"); 370 371 // Run register allocation and passes that are tightly coupled with it, 372 // including phi elimination and scheduling. 373 if (getOptimizeRegAlloc()) 374 addOptimizedRegAlloc(createRegAllocPass(true)); 375 else 376 addFastRegAlloc(createRegAllocPass(false)); 377 378 // Run post-ra passes. 379 if (addPostRegAlloc()) 380 printAndVerify("After PostRegAlloc passes"); 381 382 // Insert prolog/epilog code. Eliminate abstract frame index references... 383 addPass(PrologEpilogCodeInserterID); 384 printAndVerify("After PrologEpilogCodeInserter"); 385 386 /// Add passes that optimize machine instructions after register allocation. 387 if (getOptLevel() != CodeGenOpt::None) 388 addMachineLateOptimization(); 389 390 // Expand pseudo instructions before second scheduling pass. 391 addPass(ExpandPostRAPseudosID); 392 printAndVerify("After ExpandPostRAPseudos"); 393 394 // Run pre-sched2 passes. 395 if (addPreSched2()) 396 printAndVerify("After PreSched2 passes"); 397 398 // Second pass scheduler. 399 if (getOptLevel() != CodeGenOpt::None) { 400 addPass(PostRASchedulerID); 401 printAndVerify("After PostRAScheduler"); 402 } 403 404 // GC 405 addPass(GCMachineCodeAnalysisID); 406 if (PrintGCInfo) 407 PM.add(createGCInfoPrinter(dbgs())); 408 409 // Basic block placement. 410 if (getOptLevel() != CodeGenOpt::None) 411 addBlockPlacement(); 412 413 if (addPreEmitPass()) 414 printAndVerify("After PreEmit passes"); 415} 416 417/// Add passes that optimize machine instructions in SSA form. 418void TargetPassConfig::addMachineSSAOptimization() { 419 // Pre-ra tail duplication. 420 if (addPass(EarlyTailDuplicateID) != &NoPassID) 421 printAndVerify("After Pre-RegAlloc TailDuplicate"); 422 423 // Optimize PHIs before DCE: removing dead PHI cycles may make more 424 // instructions dead. 425 addPass(OptimizePHIsID); 426 427 // If the target requests it, assign local variables to stack slots relative 428 // to one another and simplify frame index references where possible. 429 addPass(LocalStackSlotAllocationID); 430 431 // With optimization, dead code should already be eliminated. However 432 // there is one known exception: lowered code for arguments that are only 433 // used by tail calls, where the tail calls reuse the incoming stack 434 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 435 addPass(DeadMachineInstructionElimID); 436 printAndVerify("After codegen DCE pass"); 437 438 addPass(MachineLICMID); 439 addPass(MachineCSEID); 440 addPass(MachineSinkingID); 441 printAndVerify("After Machine LICM, CSE and Sinking passes"); 442 443 addPass(PeepholeOptimizerID); 444 printAndVerify("After codegen peephole optimization pass"); 445} 446 447//===---------------------------------------------------------------------===// 448/// Register Allocation Pass Configuration 449//===---------------------------------------------------------------------===// 450 451bool TargetPassConfig::getOptimizeRegAlloc() const { 452 switch (OptimizeRegAlloc) { 453 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 454 case cl::BOU_TRUE: return true; 455 case cl::BOU_FALSE: return false; 456 } 457 llvm_unreachable("Invalid optimize-regalloc state"); 458} 459 460/// RegisterRegAlloc's global Registry tracks allocator registration. 461MachinePassRegistry RegisterRegAlloc::Registry; 462 463/// A dummy default pass factory indicates whether the register allocator is 464/// overridden on the command line. 465static FunctionPass *useDefaultRegisterAllocator() { return 0; } 466static RegisterRegAlloc 467defaultRegAlloc("default", 468 "pick register allocator based on -O option", 469 useDefaultRegisterAllocator); 470 471/// -regalloc=... command line option. 472static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 473 RegisterPassParser<RegisterRegAlloc> > 474RegAlloc("regalloc", 475 cl::init(&useDefaultRegisterAllocator), 476 cl::desc("Register allocator to use")); 477 478 479/// Instantiate the default register allocator pass for this target for either 480/// the optimized or unoptimized allocation path. This will be added to the pass 481/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 482/// in the optimized case. 483/// 484/// A target that uses the standard regalloc pass order for fast or optimized 485/// allocation may still override this for per-target regalloc 486/// selection. But -regalloc=... always takes precedence. 487FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 488 if (Optimized) 489 return createGreedyRegisterAllocator(); 490 else 491 return createFastRegisterAllocator(); 492} 493 494/// Find and instantiate the register allocation pass requested by this target 495/// at the current optimization level. Different register allocators are 496/// defined as separate passes because they may require different analysis. 497/// 498/// This helper ensures that the regalloc= option is always available, 499/// even for targets that override the default allocator. 500/// 501/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 502/// this can be folded into addPass. 503FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 504 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 505 506 // Initialize the global default. 507 if (!Ctor) { 508 Ctor = RegAlloc; 509 RegisterRegAlloc::setDefault(RegAlloc); 510 } 511 if (Ctor != useDefaultRegisterAllocator) 512 return Ctor(); 513 514 // With no -regalloc= override, ask the target for a regalloc pass. 515 return createTargetRegisterAllocator(Optimized); 516} 517 518/// Add the minimum set of target-independent passes that are required for 519/// register allocation. No coalescing or scheduling. 520void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 521 addPass(PHIEliminationID); 522 addPass(TwoAddressInstructionPassID); 523 524 PM.add(RegAllocPass); 525 printAndVerify("After Register Allocation"); 526} 527 528/// Add standard target-independent passes that are tightly coupled with 529/// optimized register allocation, including coalescing, machine instruction 530/// scheduling, and register allocation itself. 531void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 532 // LiveVariables currently requires pure SSA form. 533 // 534 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 535 // LiveVariables can be removed completely, and LiveIntervals can be directly 536 // computed. (We still either need to regenerate kill flags after regalloc, or 537 // preferably fix the scavenger to not depend on them). 538 addPass(LiveVariablesID); 539 540 // Add passes that move from transformed SSA into conventional SSA. This is a 541 // "copy coalescing" problem. 542 // 543 if (!EnableStrongPHIElim) { 544 // Edge splitting is smarter with machine loop info. 545 addPass(MachineLoopInfoID); 546 addPass(PHIEliminationID); 547 } 548 addPass(TwoAddressInstructionPassID); 549 550 // FIXME: Either remove this pass completely, or fix it so that it works on 551 // SSA form. We could modify LiveIntervals to be independent of this pass, But 552 // it would be even better to simply eliminate *all* IMPLICIT_DEFs before 553 // leaving SSA. 554 addPass(ProcessImplicitDefsID); 555 556 if (EnableStrongPHIElim) 557 addPass(StrongPHIEliminationID); 558 559 addPass(RegisterCoalescerID); 560 561 // PreRA instruction scheduling. 562 if (addPass(MachineSchedulerID) != &NoPassID) 563 printAndVerify("After Machine Scheduling"); 564 565 // Add the selected register allocation pass. 566 PM.add(RegAllocPass); 567 printAndVerify("After Register Allocation"); 568 569 // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature, 570 // but eventually, all users of it should probably be moved to addPostRA and 571 // it can go away. Currently, it's the intended place for targets to run 572 // FinalizeMachineBundles, because passes other than MachineScheduling an 573 // RegAlloc itself may not be aware of bundles. 574 if (addFinalizeRegAlloc()) 575 printAndVerify("After RegAlloc finalization"); 576 577 // Perform stack slot coloring and post-ra machine LICM. 578 // 579 // FIXME: Re-enable coloring with register when it's capable of adding 580 // kill markers. 581 addPass(StackSlotColoringID); 582 583 // Run post-ra machine LICM to hoist reloads / remats. 584 // 585 // FIXME: can this move into MachineLateOptimization? 586 addPass(PostRAMachineLICMID); 587 588 printAndVerify("After StackSlotColoring and postra Machine LICM"); 589} 590 591//===---------------------------------------------------------------------===// 592/// Post RegAlloc Pass Configuration 593//===---------------------------------------------------------------------===// 594 595/// Add passes that optimize machine instructions after register allocation. 596void TargetPassConfig::addMachineLateOptimization() { 597 // Branch folding must be run after regalloc and prolog/epilog insertion. 598 if (addPass(BranchFolderPassID) != &NoPassID) 599 printAndVerify("After BranchFolding"); 600 601 // Tail duplication. 602 if (addPass(TailDuplicateID) != &NoPassID) 603 printAndVerify("After TailDuplicate"); 604 605 // Copy propagation. 606 if (addPass(MachineCopyPropagationID) != &NoPassID) 607 printAndVerify("After copy propagation pass"); 608} 609 610/// Add standard basic block placement passes. 611void TargetPassConfig::addBlockPlacement() { 612 AnalysisID ID = &NoPassID; 613 if (EnableBlockPlacement) { 614 // MachineBlockPlacement is an experimental pass which is disabled by 615 // default currently. Eventually it should subsume CodePlacementOpt, so 616 // when enabled, the other is disabled. 617 ID = addPass(MachineBlockPlacementID); 618 } else { 619 ID = addPass(CodePlacementOptID); 620 } 621 if (ID != &NoPassID) { 622 // Run a separate pass to collect block placement statistics. 623 if (EnableBlockPlacementStats) 624 addPass(MachineBlockPlacementStatsID); 625 626 printAndVerify("After machine block placement."); 627 } 628} 629