DeadMachineInstructionElim.cpp revision 249423
178388Sbenno//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===// 278388Sbenno// 378388Sbenno// The LLVM Compiler Infrastructure 478388Sbenno// 578388Sbenno// This file is distributed under the University of Illinois Open Source 678388Sbenno// License. See LICENSE.TXT for details. 7101165Sblackend// 878388Sbenno//===----------------------------------------------------------------------===// 978388Sbenno// 1078388Sbenno// This is an extremely simple MachineInstr-level dead-code-elimination pass. 1178388Sbenno// 1278388Sbenno//===----------------------------------------------------------------------===// 1378388Sbenno 1478388Sbenno#define DEBUG_TYPE "codegen-dce" 15100189Sjhb#include "llvm/CodeGen/Passes.h" 16100189Sjhb#include "llvm/ADT/Statistic.h" 17100189Sjhb#include "llvm/CodeGen/MachineFunctionPass.h" 1878388Sbenno#include "llvm/CodeGen/MachineRegisterInfo.h" 1978388Sbenno#include "llvm/Pass.h" 2078388Sbenno#include "llvm/Support/Debug.h" 2178388Sbenno#include "llvm/Support/raw_ostream.h" 22110383Sbenno#include "llvm/Target/TargetInstrInfo.h" 2378388Sbenno#include "llvm/Target/TargetMachine.h" 2478388Sbennousing namespace llvm; 2578388Sbenno 2678388SbennoSTATISTIC(NumDeletes, "Number of dead instructions deleted"); 2778388Sbenno 28108979Sgrehannamespace { 29100476Speter class DeadMachineInstructionElim : public MachineFunctionPass { 3078388Sbenno virtual bool runOnMachineFunction(MachineFunction &MF); 31103629Sgrehan 32103629Sgrehan const TargetRegisterInfo *TRI; 33110832Sobrien const MachineRegisterInfo *MRI; 3484857Smp const TargetInstrInfo *TII; 35124935Sjeff BitVector LivePhysRegs; 36110832Sobrien 37110832Sobrien public: 38110832Sobrien static char ID; // Pass identification, replacement for typeid 39110832Sobrien DeadMachineInstructionElim() : MachineFunctionPass(ID) { 40105463Srwatson initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry()); 41110832Sobrien } 42110832Sobrien 43110832Sobrien private: 44110832Sobrien bool isDead(const MachineInstr *MI) const; 45110832Sobrien }; 46110832Sobrien} 47110832Sobrienchar DeadMachineInstructionElim::ID = 0; 48110832Sobrienchar &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID; 49110832Sobrien 50128845SmarcelINITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination", 51110832Sobrien "Remove dead machine instructions", false, false) 52110832Sobrien 53110832Sobrienbool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { 54110832Sobrien // Technically speaking inline asm without side effects and no defs can still 55110832Sobrien // be deleted. But there is so much bad inline asm code out there, we should 56110832Sobrien // let them be. 57110832Sobrien if (MI->isInlineAsm()) 58137118Sssouhlal return false; 5999667Sbenno 60103629Sgrehan // Don't delete instructions with side effects. 61132063Sgrehan bool SawStore = false; 62132063Sgrehan if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI()) 63110832Sobrien return false; 64110832Sobrien 65110832Sobrien // Examine each operand. 66103629Sgrehan for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 67103629Sgrehan const MachineOperand &MO = MI->getOperand(i); 68110832Sobrien if (MO.isReg() && MO.isDef()) { 69103629Sgrehan unsigned Reg = MO.getReg(); 70103629Sgrehan if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 71100551Speter // Don't delete live physreg defs, or any reserved register defs. 72103629Sgrehan if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) 73103629Sgrehan return false; 74103629Sgrehan } else { 75103629Sgrehan if (!MRI->use_nodbg_empty(Reg)) 76103629Sgrehan // This def has a non-debug use. Don't delete the instruction! 77103629Sgrehan return false; 78103629Sgrehan } 79103629Sgrehan } 80113837Ssimokawa } 81115999Sjmallett 82113837Ssimokawa // If there are no defs with uses, the instruction is dead. 83113837Ssimokawa return true; 84113837Ssimokawa} 85113837Ssimokawa 86113837Ssimokawabool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { 87124775Sgrehan bool AnyChanges = false; 88124775Sgrehan MRI = &MF.getRegInfo(); 89124775Sgrehan TRI = MF.getTarget().getRegisterInfo(); 90124775Sgrehan TII = MF.getTarget().getInstrInfo(); 91124775Sgrehan 92124775Sgrehan // Loop over all instructions in all blocks, from bottom to top, so that it's 93103629Sgrehan // more likely that chains of dependent but ultimately dead instructions will 94103629Sgrehan // be cleaned up. 95110223Sbenno for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend(); 96103629Sgrehan I != E; ++I) { 97103629Sgrehan MachineBasicBlock *MBB = &*I; 98103629Sgrehan 99103771Sbenno // Start out assuming that reserved registers are live out of this block. 100132063Sgrehan LivePhysRegs = MRI->getReservedRegs(); 101132063Sgrehan 102103629Sgrehan // Add live-ins from sucessors to LivePhysRegs. Normally, physregs are not 103132345Smaxim // live across blocks, but some targets (x86) can have flags live out of a 104132956Smarkm // block. 105133855Sssouhlal for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(), 106103629Sgrehan E = MBB->succ_end(); S != E; S++) 107103629Sgrehan for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin(); 108103629Sgrehan LI != (*S)->livein_end(); LI++) 109103629Sgrehan LivePhysRegs.set(*LI); 110103629Sgrehan 111103629Sgrehan // Now scan the instructions and delete dead ones, tracking physreg 112103629Sgrehan // liveness as we go. 113133862Smarius for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(), 114103629Sgrehan MIE = MBB->rend(); MII != MIE; ) { 115103629Sgrehan MachineInstr *MI = &*MII; 116103629Sgrehan 117103629Sgrehan // If the instruction is dead, delete it! 118103629Sgrehan if (isDead(MI)) { 119103629Sgrehan DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI); 120103629Sgrehan // It is possible that some DBG_VALUE instructions refer to this 121103629Sgrehan // instruction. Examine each def operand for such references; 122124775Sgrehan // if found, mark the DBG_VALUE as undef (but don't delete it). 123124775Sgrehan for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 124124775Sgrehan const MachineOperand &MO = MI->getOperand(i); 125124775Sgrehan if (!MO.isReg() || !MO.isDef()) 126124775Sgrehan continue; 127124775Sgrehan unsigned Reg = MO.getReg(); 128124775Sgrehan if (!TargetRegisterInfo::isVirtualRegister(Reg)) 129124775Sgrehan continue; 130124775Sgrehan MachineRegisterInfo::use_iterator nextI; 131124775Sgrehan for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), 132124775Sgrehan E = MRI->use_end(); I!=E; I=nextI) { 133103629Sgrehan nextI = llvm::next(I); // I is invalidated by the setReg 134128838Sobrien MachineOperand& Use = I.getOperand(); 135128838Sobrien MachineInstr *UseMI = Use.getParent(); 136128838Sobrien if (UseMI==MI) 137128838Sobrien continue; 138103629Sgrehan assert(Use.isDebug()); 139113803Ssimokawa UseMI->getOperand(0).setReg(0U); 140113803Ssimokawa } 141113803Ssimokawa } 142113803Ssimokawa AnyChanges = true; 143113803Ssimokawa MI->eraseFromParent(); 144103629Sgrehan ++NumDeletes; 145103629Sgrehan MIE = MBB->rend(); 146103629Sgrehan // MII is now pointing to the next instruction to process, 147110832Sobrien // so don't increment it. 148110832Sobrien continue; 149110832Sobrien } 150110832Sobrien 151 // Record the physreg defs. 152 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 153 const MachineOperand &MO = MI->getOperand(i); 154 if (MO.isReg() && MO.isDef()) { 155 unsigned Reg = MO.getReg(); 156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 157 LivePhysRegs.reset(Reg); 158 // Check the subreg set, not the alias set, because a def 159 // of a super-register may still be partially live after 160 // this def. 161 for (MCSubRegIterator SR(Reg, TRI); SR.isValid(); ++SR) 162 LivePhysRegs.reset(*SR); 163 } 164 } else if (MO.isRegMask()) { 165 // Register mask of preserved registers. All clobbers are dead. 166 LivePhysRegs.clearBitsNotInMask(MO.getRegMask()); 167 } 168 } 169 // Record the physreg uses, after the defs, in case a physreg is 170 // both defined and used in the same instruction. 171 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 172 const MachineOperand &MO = MI->getOperand(i); 173 if (MO.isReg() && MO.isUse()) { 174 unsigned Reg = MO.getReg(); 175 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 177 LivePhysRegs.set(*AI); 178 } 179 } 180 } 181 182 // We didn't delete the current instruction, so increment MII to 183 // the next one. 184 ++MII; 185 } 186 } 187 188 LivePhysRegs.clear(); 189 return AnyChanges; 190} 191