TargetOpcodes.h revision 207618 
1//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the target independent instruction opcodes.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETOPCODES_H
15#define LLVM_TARGET_TARGETOPCODES_H
16
17namespace llvm {
18
19/// Invariant opcodes: All instruction sets have these as their low opcodes.
20namespace TargetOpcode {
21  enum {
22    PHI = 0,
23    INLINEASM = 1,
24    DBG_LABEL = 2,
25    EH_LABEL = 3,
26    GC_LABEL = 4,
27
28    /// KILL - This instruction is a noop that is used only to adjust the
29    /// liveness of registers. This can be useful when dealing with
30    /// sub-registers.
31    KILL = 5,
32
33    /// EXTRACT_SUBREG - This instruction takes two operands: a register
34    /// that has subregisters, and a subregister index. It returns the
35    /// extracted subregister value. This is commonly used to implement
36    /// truncation operations on target architectures which support it.
37    EXTRACT_SUBREG = 6,
38
39    /// INSERT_SUBREG - This instruction takes three operands: a register
40    /// that has subregisters, a register providing an insert value, and a
41    /// subregister index. It returns the value of the first register with
42    /// the value of the second register inserted. The first register is
43    /// often defined by an IMPLICIT_DEF, as is commonly used to implement
44    /// anyext operations on target architectures which support it.
45    INSERT_SUBREG = 7,
46
47    /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
48    IMPLICIT_DEF = 8,
49
50    /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
51    /// that the first operand is an immediate integer constant. This constant
52    /// is often zero, as is commonly used to implement zext operations on
53    /// target architectures which support it, such as with x86-64 (with
54    /// zext from i32 to i64 via implicit zero-extension).
55    SUBREG_TO_REG = 9,
56
57    /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
58    /// register-to-register copy into a specific register class. This is only
59    /// used between instruction selection and MachineInstr creation, before
60    /// virtual registers have been created for all the instructions, and it's
61    /// only needed in cases where the register classes implied by the
62    /// instructions are insufficient. The actual MachineInstrs to perform
63    /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
64    COPY_TO_REGCLASS = 10,
65
66    /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
67    DBG_VALUE = 11,
68
69    /// REG_SEQUENCE - This variadic instruction is used to form a register that
70    /// represent a consecutive sequence of sub-registers. It's used as register
71    /// coalescing / allocation aid and must be eliminated before code emission.
72    /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
73    /// After register coalescing references of v1024 should be replace with
74    /// v1027:3, v1025 with v1027:4, etc.
75    REG_SEQUENCE = 12
76  };
77} // end namespace TargetOpcode
78} // end namespace llvm
79
80#endif
81