1193323Sed//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the SelectionDAGISel class, which is used as the common 11193323Sed// base class for SelectionDAG-based instruction selectors. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15249423Sdim#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16249423Sdim#define LLVM_CODEGEN_SELECTIONDAGISEL_H 17193323Sed 18249423Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 19249423Sdim#include "llvm/CodeGen/SelectionDAG.h" 20249423Sdim#include "llvm/IR/BasicBlock.h" 21193323Sed#include "llvm/Pass.h" 22193323Sed 23193323Sednamespace llvm { 24193323Sed class FastISel; 25199989Srdivacky class SelectionDAGBuilder; 26193323Sed class SDValue; 27193323Sed class MachineRegisterInfo; 28193323Sed class MachineBasicBlock; 29193323Sed class MachineFunction; 30193323Sed class MachineInstr; 31193323Sed class TargetLowering; 32234353Sdim class TargetLibraryInfo; 33249423Sdim class TargetTransformInfo; 34193323Sed class FunctionLoweringInfo; 35193323Sed class ScheduleHazardRecognizer; 36193323Sed class GCFunctionInfo; 37193323Sed class ScheduleDAGSDNodes; 38218893Sdim class LoadInst; 39218893Sdim 40193323Sed/// SelectionDAGISel - This is the common base class used for SelectionDAG-based 41193323Sed/// pattern-matching instruction selectors. 42198090Srdivackyclass SelectionDAGISel : public MachineFunctionPass { 43193323Sedpublic: 44263508Sdim TargetMachine &TM; 45234353Sdim const TargetLibraryInfo *LibInfo; 46249423Sdim const TargetTransformInfo *TTI; 47193323Sed FunctionLoweringInfo *FuncInfo; 48193323Sed MachineFunction *MF; 49193323Sed MachineRegisterInfo *RegInfo; 50193323Sed SelectionDAG *CurDAG; 51199989Srdivacky SelectionDAGBuilder *SDB; 52193323Sed AliasAnalysis *AA; 53193323Sed GCFunctionInfo *GFI; 54193323Sed CodeGenOpt::Level OptLevel; 55193323Sed static char ID; 56193323Sed 57263508Sdim explicit SelectionDAGISel(TargetMachine &tm, 58193323Sed CodeGenOpt::Level OL = CodeGenOpt::Default); 59193323Sed virtual ~SelectionDAGISel(); 60218893Sdim 61263508Sdim const TargetLowering *getTargetLowering() const { 62263508Sdim return TM.getTargetLowering(); 63263508Sdim } 64193323Sed 65193323Sed virtual void getAnalysisUsage(AnalysisUsage &AU) const; 66193323Sed 67198090Srdivacky virtual bool runOnMachineFunction(MachineFunction &MF); 68193323Sed 69207618Srdivacky virtual void EmitFunctionEntryCode() {} 70218893Sdim 71204642Srdivacky /// PreprocessISelDAG - This hook allows targets to hack on the graph before 72204642Srdivacky /// instruction selection starts. 73204642Srdivacky virtual void PreprocessISelDAG() {} 74218893Sdim 75204642Srdivacky /// PostprocessISelDAG() - This hook allows the target to hack on the graph 76204642Srdivacky /// right after selection. 77204642Srdivacky virtual void PostprocessISelDAG() {} 78218893Sdim 79204642Srdivacky /// Select - Main hook targets implement to select a node. 80204642Srdivacky virtual SDNode *Select(SDNode *N) = 0; 81218893Sdim 82193323Sed /// SelectInlineAsmMemoryOperand - Select the specified address as a target 83193323Sed /// addressing mode, according to the specified constraint code. If this does 84193323Sed /// not match or is not implemented, return true. The resultant operands 85193323Sed /// (which will appear in the machine instruction) should be added to the 86193323Sed /// OutOps vector. 87193323Sed virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 88193323Sed char ConstraintCode, 89193323Sed std::vector<SDValue> &OutOps) { 90193323Sed return true; 91193323Sed } 92193323Sed 93203954Srdivacky /// IsProfitableToFold - Returns true if it's profitable to fold the specific 94203954Srdivacky /// operand node N of U during instruction selection that starts at Root. 95203954Srdivacky virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 96193323Sed 97203954Srdivacky /// IsLegalToFold - Returns true if the specific operand node N of 98203954Srdivacky /// U can be folded during instruction selection that starts at Root. 99234353Sdim /// FIXME: This is a static member function because the MSP430/X86 100218893Sdim /// targets, which uses it during isel. This could become a proper member. 101207618Srdivacky static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 102207618Srdivacky CodeGenOpt::Level OptLevel, 103207618Srdivacky bool IgnoreChains = false); 104203954Srdivacky 105204642Srdivacky // Opcodes used by the DAG state machine: 106204642Srdivacky enum BuiltinOpcodes { 107204642Srdivacky OPC_Scope, 108204642Srdivacky OPC_RecordNode, 109218893Sdim OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 110204642Srdivacky OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 111204642Srdivacky OPC_RecordMemRef, 112218893Sdim OPC_CaptureGlueInput, 113204642Srdivacky OPC_MoveChild, 114204642Srdivacky OPC_MoveParent, 115204642Srdivacky OPC_CheckSame, 116263508Sdim OPC_CheckChild0Same, OPC_CheckChild1Same, 117263508Sdim OPC_CheckChild2Same, OPC_CheckChild3Same, 118204642Srdivacky OPC_CheckPatternPredicate, 119204642Srdivacky OPC_CheckPredicate, 120204642Srdivacky OPC_CheckOpcode, 121204642Srdivacky OPC_SwitchOpcode, 122204642Srdivacky OPC_CheckType, 123204642Srdivacky OPC_SwitchType, 124204642Srdivacky OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 125204642Srdivacky OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 126204642Srdivacky OPC_CheckChild6Type, OPC_CheckChild7Type, 127204642Srdivacky OPC_CheckInteger, 128204642Srdivacky OPC_CheckCondCode, 129204642Srdivacky OPC_CheckValueType, 130204642Srdivacky OPC_CheckComplexPat, 131204642Srdivacky OPC_CheckAndImm, OPC_CheckOrImm, 132204642Srdivacky OPC_CheckFoldableChainNode, 133218893Sdim 134204642Srdivacky OPC_EmitInteger, 135204642Srdivacky OPC_EmitRegister, 136221345Sdim OPC_EmitRegister2, 137204642Srdivacky OPC_EmitConvertToTarget, 138204642Srdivacky OPC_EmitMergeInputChains, 139206083Srdivacky OPC_EmitMergeInputChains1_0, 140206083Srdivacky OPC_EmitMergeInputChains1_1, 141204642Srdivacky OPC_EmitCopyToReg, 142204642Srdivacky OPC_EmitNodeXForm, 143204642Srdivacky OPC_EmitNode, 144204642Srdivacky OPC_MorphNodeTo, 145218893Sdim OPC_MarkGlueResults, 146204642Srdivacky OPC_CompleteMatch 147204642Srdivacky }; 148218893Sdim 149204642Srdivacky enum { 150218893Sdim OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 151204642Srdivacky OPFL_Chain = 1, // Node has a chain input. 152218893Sdim OPFL_GlueInput = 2, // Node has a glue input. 153218893Sdim OPFL_GlueOutput = 4, // Node has a glue output. 154204642Srdivacky OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 155204642Srdivacky OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 156204642Srdivacky OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 157204642Srdivacky OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 158204642Srdivacky OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 159204642Srdivacky OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 160204642Srdivacky OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 161204642Srdivacky OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 162218893Sdim 163204642Srdivacky OPFL_VariadicInfo = OPFL_Variadic6 164204642Srdivacky }; 165218893Sdim 166204642Srdivacky /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 167204642Srdivacky /// number of fixed arity values that should be skipped when copying from the 168204642Srdivacky /// root. 169204642Srdivacky static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 170204642Srdivacky return ((Flags&OPFL_VariadicInfo) >> 4)-1; 171204642Srdivacky } 172218893Sdim 173218893Sdim 174193323Sedprotected: 175193323Sed /// DAGSize - Size of DAG being instruction selected. 176193323Sed /// 177193323Sed unsigned DAGSize; 178218893Sdim 179204642Srdivacky /// ReplaceUses - replace all uses of the old node F with the use 180204642Srdivacky /// of the new node T. 181204642Srdivacky void ReplaceUses(SDValue F, SDValue T) { 182239462Sdim CurDAG->ReplaceAllUsesOfValueWith(F, T); 183204642Srdivacky } 184218893Sdim 185204642Srdivacky /// ReplaceUses - replace all uses of the old nodes F with the use 186204642Srdivacky /// of the new nodes T. 187204642Srdivacky void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 188239462Sdim CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 189204642Srdivacky } 190218893Sdim 191204642Srdivacky /// ReplaceUses - replace all uses of the old node F with the use 192204642Srdivacky /// of the new node T. 193204642Srdivacky void ReplaceUses(SDNode *F, SDNode *T) { 194239462Sdim CurDAG->ReplaceAllUsesWith(F, T); 195204642Srdivacky } 196204642Srdivacky 197218893Sdim 198193323Sed /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 199193323Sed /// by tblgen. Others should not call it. 200193323Sed void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); 201193323Sed 202218893Sdim 203204642Srdivackypublic: 204193323Sed // Calls to these predicates are generated by tblgen. 205193323Sed bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 206193323Sed int64_t DesiredMaskS) const; 207193323Sed bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 208193323Sed int64_t DesiredMaskS) const; 209218893Sdim 210218893Sdim 211203954Srdivacky /// CheckPatternPredicate - This function is generated by tblgen in the 212203954Srdivacky /// target. It runs the specified pattern predicate and returns true if it 213203954Srdivacky /// succeeds or false if it fails. The number is a private implementation 214203954Srdivacky /// detail to the code tblgen produces. 215203954Srdivacky virtual bool CheckPatternPredicate(unsigned PredNo) const { 216234353Sdim llvm_unreachable("Tblgen should generate the implementation of this!"); 217203954Srdivacky } 218203954Srdivacky 219204642Srdivacky /// CheckNodePredicate - This function is generated by tblgen in the target. 220204642Srdivacky /// It runs node predicate number PredNo and returns true if it succeeds or 221203954Srdivacky /// false if it fails. The number is a private implementation 222203954Srdivacky /// detail to the code tblgen produces. 223203954Srdivacky virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 224234353Sdim llvm_unreachable("Tblgen should generate the implementation of this!"); 225203954Srdivacky } 226218893Sdim 227218893Sdim virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 228218893Sdim unsigned PatternNo, 229218893Sdim SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 230234353Sdim llvm_unreachable("Tblgen should generate the implementation of this!"); 231204642Srdivacky } 232218893Sdim 233204642Srdivacky virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 234234353Sdim llvm_unreachable("Tblgen should generate this!"); 235204642Srdivacky } 236204642Srdivacky 237204642Srdivacky SDNode *SelectCodeCommon(SDNode *NodeToMatch, 238204642Srdivacky const unsigned char *MatcherTable, 239204642Srdivacky unsigned TableSize); 240218893Sdim 241286033Sdim /// \brief Return true if complex patterns for this target can mutate the 242286033Sdim /// DAG. 243286033Sdim virtual bool ComplexPatternFuncMutatesDAG() const { 244286033Sdim return false; 245286033Sdim } 246286033Sdim 247204642Srdivackyprivate: 248218893Sdim 249198892Srdivacky // Calls to these functions are generated by tblgen. 250202375Srdivacky SDNode *Select_INLINEASM(SDNode *N); 251202375Srdivacky SDNode *Select_UNDEF(SDNode *N); 252202375Srdivacky void CannotYetSelect(SDNode *N); 253198892Srdivacky 254193323Sedprivate: 255204642Srdivacky void DoInstructionSelection(); 256204642Srdivacky SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 257204642Srdivacky const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo); 258218893Sdim 259210299Sed void PrepareEHLandingPad(); 260249423Sdim 261249423Sdim /// \brief Perform instruction selection on all basic blocks in the function. 262207618Srdivacky void SelectAllBasicBlocks(const Function &Fn); 263249423Sdim 264249423Sdim /// \brief Perform instruction selection on a single basic block, for 265249423Sdim /// instructions between \p Begin and \p End. \p HadTailCall will be set 266249423Sdim /// to true if a call in the block was translated as a tail call. 267249423Sdim void SelectBasicBlock(BasicBlock::const_iterator Begin, 268249423Sdim BasicBlock::const_iterator End, 269249423Sdim bool &HadTailCall); 270210299Sed void FinishBasicBlock(); 271193323Sed 272210299Sed void CodeGenAndEmitDAG(); 273218893Sdim 274249423Sdim /// \brief Generate instructions for lowering the incoming arguments of the 275249423Sdim /// given function. 276249423Sdim void LowerArguments(const Function &F); 277249423Sdim 278193323Sed void ComputeLiveOutVRegInfo(); 279193323Sed 280193323Sed /// Create the scheduler. If a specific scheduler was specified 281193323Sed /// via the SchedulerRegistry, use it, otherwise select the 282193323Sed /// one preferred by the target. 283193323Sed /// 284193323Sed ScheduleDAGSDNodes *CreateScheduler(); 285218893Sdim 286204642Srdivacky /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 287204642Srdivacky /// state machines that start with a OPC_SwitchOpcode node. 288204642Srdivacky std::vector<unsigned> OpcodeOffset; 289218893Sdim 290218893Sdim void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 291218893Sdim const SmallVectorImpl<SDNode*> &ChainNodesMatched, 292218893Sdim SDValue InputGlue, const SmallVectorImpl<SDNode*> &F, 293218893Sdim bool isMorphNodeTo); 294218893Sdim 295193323Sed}; 296193323Sed 297193323Sed} 298193323Sed 299249423Sdim#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 300