1193323Sed//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the implementation for instruction scheduler function 11193323Sed// pass registry (RegisterScheduler). 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15249423Sdim#ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H 16249423Sdim#define LLVM_CODEGEN_SCHEDULERREGISTRY_H 17193323Sed 18193323Sed#include "llvm/CodeGen/MachinePassRegistry.h" 19193323Sed#include "llvm/Target/TargetMachine.h" 20193323Sed 21193323Sednamespace llvm { 22193323Sed 23193323Sed//===----------------------------------------------------------------------===// 24193323Sed/// 25193323Sed/// RegisterScheduler class - Track the registration of instruction schedulers. 26193323Sed/// 27193323Sed//===----------------------------------------------------------------------===// 28193323Sed 29193323Sedclass SelectionDAGISel; 30193323Sedclass ScheduleDAGSDNodes; 31193323Sedclass SelectionDAG; 32193323Sedclass MachineBasicBlock; 33193323Sed 34193323Sedclass RegisterScheduler : public MachinePassRegistryNode { 35193323Sedpublic: 36193323Sed typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, 37193323Sed CodeGenOpt::Level); 38193323Sed 39193323Sed static MachinePassRegistry Registry; 40193323Sed 41193323Sed RegisterScheduler(const char *N, const char *D, FunctionPassCtor C) 42193323Sed : MachinePassRegistryNode(N, D, (MachinePassCtor)C) 43193323Sed { Registry.Add(this); } 44193323Sed ~RegisterScheduler() { Registry.Remove(this); } 45193323Sed 46234353Sdim 47193323Sed // Accessors. 48193323Sed // 49193323Sed RegisterScheduler *getNext() const { 50193323Sed return (RegisterScheduler *)MachinePassRegistryNode::getNext(); 51193323Sed } 52193323Sed static RegisterScheduler *getList() { 53193323Sed return (RegisterScheduler *)Registry.getList(); 54193323Sed } 55193323Sed static FunctionPassCtor getDefault() { 56193323Sed return (FunctionPassCtor)Registry.getDefault(); 57193323Sed } 58193323Sed static void setDefault(FunctionPassCtor C) { 59193323Sed Registry.setDefault((MachinePassCtor)C); 60193323Sed } 61193323Sed static void setListener(MachinePassRegistryListener *L) { 62193323Sed Registry.setListener(L); 63193323Sed } 64193323Sed}; 65193323Sed 66193323Sed/// createBURRListDAGScheduler - This creates a bottom up register usage 67193323Sed/// reduction list scheduler. 68193323SedScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, 69193323Sed CodeGenOpt::Level OptLevel); 70193323Sed 71208599Srdivacky/// createBURRListDAGScheduler - This creates a bottom up list scheduler that 72208599Srdivacky/// schedules nodes in source code order when possible. 73202878SrdivackyScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, 74202878Srdivacky CodeGenOpt::Level OptLevel); 75202878Srdivacky 76212904Sdim/// createHybridListDAGScheduler - This creates a bottom up register pressure 77212904Sdim/// aware list scheduler that make use of latency information to avoid stalls 78212904Sdim/// for long latency instructions in low register pressure mode. In high 79212904Sdim/// register pressure mode it schedules to reduce register pressure. 80208599SrdivackyScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS, 81208599Srdivacky CodeGenOpt::Level); 82208599Srdivacky 83212904Sdim/// createILPListDAGScheduler - This creates a bottom up register pressure 84212904Sdim/// aware list scheduler that tries to increase instruction level parallelism 85212904Sdim/// in low register pressure mode. In high register pressure mode it schedules 86212904Sdim/// to reduce register pressure. 87212904SdimScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS, 88212904Sdim CodeGenOpt::Level); 89193323Sed 90193323Sed/// createFastDAGScheduler - This creates a "fast" scheduler. 91193323Sed/// 92193323SedScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, 93193323Sed CodeGenOpt::Level OptLevel); 94193323Sed 95234353Sdim/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down 96234353Sdim/// DFA driven list scheduler with clustering heuristic to control 97234353Sdim/// register pressure. 98234353SdimScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS, 99234353Sdim CodeGenOpt::Level OptLevel); 100193323Sed/// createDefaultScheduler - This creates an instruction scheduler appropriate 101193323Sed/// for the target. 102193323SedScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, 103193323Sed CodeGenOpt::Level OptLevel); 104193323Sed 105243830Sdim/// createDAGLinearizer - This creates a "no-scheduling" scheduler which 106243830Sdim/// linearize the DAG using topological order. 107243830SdimScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS, 108243830Sdim CodeGenOpt::Level OptLevel); 109243830Sdim 110193323Sed} // end namespace llvm 111193323Sed 112193323Sed#endif 113