1193323Sed//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the MachineRegisterInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15193323Sed#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16193323Sed 17193323Sed#include "llvm/ADT/BitVector.h" 18218893Sdim#include "llvm/ADT/IndexedMap.h" 19249423Sdim#include "llvm/CodeGen/MachineInstrBundle.h" 20263508Sdim#include "llvm/Target/TargetMachine.h" 21249423Sdim#include "llvm/Target/TargetRegisterInfo.h" 22193323Sed#include <vector> 23193323Sed 24193323Sednamespace llvm { 25263508Sdimclass PSetIterator; 26234353Sdim 27193323Sed/// MachineRegisterInfo - Keep track of information for virtual and physical 28193323Sed/// registers, including vreg register classes, use/def chains for registers, 29193323Sed/// etc. 30193323Sedclass MachineRegisterInfo { 31263508Sdimpublic: 32263508Sdim class Delegate { 33263508Sdim virtual void anchor(); 34263508Sdim public: 35263508Sdim virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0; 36226633Sdim 37263508Sdim virtual ~Delegate() {} 38263508Sdim }; 39263508Sdim 40263508Sdimprivate: 41263508Sdim const TargetMachine &TM; 42263508Sdim Delegate *TheDelegate; 43263508Sdim 44226633Sdim /// IsSSA - True when the machine function is in SSA form and virtual 45226633Sdim /// registers have a single def. 46226633Sdim bool IsSSA; 47226633Sdim 48234353Sdim /// TracksLiveness - True while register liveness is being tracked accurately. 49234353Sdim /// Basic block live-in lists, kill flags, and implicit defs may not be 50234353Sdim /// accurate when after this flag is cleared. 51234353Sdim bool TracksLiveness; 52234353Sdim 53218893Sdim /// VRegInfo - Information we keep for each virtual register. 54193323Sed /// 55193323Sed /// Each element in this list contains the register class of the vreg and the 56193323Sed /// start of the use/def list for the register. 57218893Sdim IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 58218893Sdim VirtReg2IndexFunctor> VRegInfo; 59193323Sed 60194612Sed /// RegAllocHints - This vector records register allocation hints for virtual 61194612Sed /// registers. For each virtual register, it keeps a register and hint type 62194612Sed /// pair making up the allocation hint. Hint type is target specific except 63194612Sed /// for the value 0 which means the second value of the pair is the preferred 64194612Sed /// register for allocation. For example, if the hint is <0, 1024>, it means 65194612Sed /// the allocator should prefer the physical register allocated to the virtual 66194612Sed /// register of the hint. 67218893Sdim IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 68234353Sdim 69193323Sed /// PhysRegUseDefLists - This is an array of the head of the use/def list for 70193323Sed /// physical registers. 71234353Sdim MachineOperand **PhysRegUseDefLists; 72234353Sdim 73239462Sdim /// getRegUseDefListHead - Return the head pointer for the register use/def 74239462Sdim /// list for the specified virtual or physical register. 75239462Sdim MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 76239462Sdim if (TargetRegisterInfo::isVirtualRegister(RegNo)) 77239462Sdim return VRegInfo[RegNo].second; 78239462Sdim return PhysRegUseDefLists[RegNo]; 79239462Sdim } 80239462Sdim 81239462Sdim MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 82239462Sdim if (TargetRegisterInfo::isVirtualRegister(RegNo)) 83239462Sdim return VRegInfo[RegNo].second; 84239462Sdim return PhysRegUseDefLists[RegNo]; 85239462Sdim } 86239462Sdim 87239462Sdim /// Get the next element in the use-def chain. 88239462Sdim static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 89239462Sdim assert(MO && MO->isReg() && "This is not a register operand!"); 90239462Sdim return MO->Contents.Reg.Next; 91239462Sdim } 92239462Sdim 93243830Sdim /// UsedRegUnits - This is a bit vector that is computed and set by the 94193323Sed /// register allocator, and must be kept up to date by passes that run after 95193323Sed /// register allocation (though most don't modify this). This is used 96193323Sed /// so that the code generator knows which callee save registers to save and 97193323Sed /// for other target specific uses. 98243830Sdim /// This vector has bits set for register units that are modified in the 99243830Sdim /// current function. It doesn't include registers clobbered by function 100243830Sdim /// calls with register mask operands. 101243830Sdim BitVector UsedRegUnits; 102234353Sdim 103243830Sdim /// UsedPhysRegMask - Additional used physregs including aliases. 104243830Sdim /// This bit vector represents all the registers clobbered by function calls. 105243830Sdim /// It can model things that UsedRegUnits can't, such as function calls that 106243830Sdim /// clobber ymm7 but preserve the low half in xmm7. 107234353Sdim BitVector UsedPhysRegMask; 108234353Sdim 109234353Sdim /// ReservedRegs - This is a bit vector of reserved registers. The target 110234353Sdim /// may change its mind about which registers should be reserved. This 111234353Sdim /// vector is the frozen set of reserved registers when register allocation 112234353Sdim /// started. 113234353Sdim BitVector ReservedRegs; 114234353Sdim 115249423Sdim /// Keep track of the physical registers that are live in to the function. 116249423Sdim /// Live in values are typically arguments in registers. LiveIn values are 117249423Sdim /// allowed to have virtual registers associated with them, stored in the 118249423Sdim /// second element. 119193323Sed std::vector<std::pair<unsigned, unsigned> > LiveIns; 120234353Sdim 121243830Sdim MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 122243830Sdim void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 123193323Sedpublic: 124263508Sdim explicit MachineRegisterInfo(const TargetMachine &TM); 125193323Sed ~MachineRegisterInfo(); 126226633Sdim 127263508Sdim const TargetRegisterInfo *getTargetRegisterInfo() const { 128263508Sdim return TM.getRegisterInfo(); 129263508Sdim } 130263508Sdim 131263508Sdim void resetDelegate(Delegate *delegate) { 132263508Sdim // Ensure another delegate does not take over unless the current 133263508Sdim // delegate first unattaches itself. If we ever need to multicast 134263508Sdim // notifications, we will need to change to using a list. 135263508Sdim assert(TheDelegate == delegate && 136263508Sdim "Only the current delegate can perform reset!"); 137263508Sdim TheDelegate = 0; 138263508Sdim } 139263508Sdim 140263508Sdim void setDelegate(Delegate *delegate) { 141263508Sdim assert(delegate && !TheDelegate && 142263508Sdim "Attempted to set delegate to null, or to change it without " 143263508Sdim "first resetting it!"); 144263508Sdim 145263508Sdim TheDelegate = delegate; 146263508Sdim } 147263508Sdim 148193323Sed //===--------------------------------------------------------------------===// 149226633Sdim // Function State 150226633Sdim //===--------------------------------------------------------------------===// 151226633Sdim 152226633Sdim // isSSA - Returns true when the machine function is in SSA form. Early 153226633Sdim // passes require the machine function to be in SSA form where every virtual 154226633Sdim // register has a single defining instruction. 155226633Sdim // 156226633Sdim // The TwoAddressInstructionPass and PHIElimination passes take the machine 157226633Sdim // function out of SSA form when they introduce multiple defs per virtual 158226633Sdim // register. 159226633Sdim bool isSSA() const { return IsSSA; } 160226633Sdim 161226633Sdim // leaveSSA - Indicates that the machine function is no longer in SSA form. 162226633Sdim void leaveSSA() { IsSSA = false; } 163226633Sdim 164234353Sdim /// tracksLiveness - Returns true when tracking register liveness accurately. 165234353Sdim /// 166234353Sdim /// While this flag is true, register liveness information in basic block 167234353Sdim /// live-in lists and machine instruction operands is accurate. This means it 168234353Sdim /// can be used to change the code in ways that affect the values in 169234353Sdim /// registers, for example by the register scavenger. 170234353Sdim /// 171234353Sdim /// When this flag is false, liveness is no longer reliable. 172234353Sdim bool tracksLiveness() const { return TracksLiveness; } 173234353Sdim 174234353Sdim /// invalidateLiveness - Indicates that register liveness is no longer being 175234353Sdim /// tracked accurately. 176234353Sdim /// 177234353Sdim /// This should be called by late passes that invalidate the liveness 178234353Sdim /// information. 179234353Sdim void invalidateLiveness() { TracksLiveness = false; } 180234353Sdim 181226633Sdim //===--------------------------------------------------------------------===// 182193323Sed // Register Info 183193323Sed //===--------------------------------------------------------------------===// 184193323Sed 185239462Sdim // Strictly for use by MachineInstr.cpp. 186239462Sdim void addRegOperandToUseList(MachineOperand *MO); 187239462Sdim 188239462Sdim // Strictly for use by MachineInstr.cpp. 189239462Sdim void removeRegOperandFromUseList(MachineOperand *MO); 190239462Sdim 191249423Sdim // Strictly for use by MachineInstr.cpp. 192249423Sdim void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 193249423Sdim 194251662Sdim /// Verify the sanity of the use list for Reg. 195251662Sdim void verifyUseList(unsigned Reg) const; 196251662Sdim 197251662Sdim /// Verify the use list of all registers. 198251662Sdim void verifyUseLists() const; 199251662Sdim 200193323Sed /// reg_begin/reg_end - Provide iteration support to walk over all definitions 201193323Sed /// and uses of a register within the MachineFunction that corresponds to this 202193323Sed /// MachineRegisterInfo object. 203203954Srdivacky template<bool Uses, bool Defs, bool SkipDebug> 204193323Sed class defusechain_iterator; 205193323Sed 206239462Sdim // Make it a friend so it can access getNextOperandForReg(). 207239462Sdim template<bool, bool, bool> friend class defusechain_iterator; 208239462Sdim 209193323Sed /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 210193323Sed /// register. 211203954Srdivacky typedef defusechain_iterator<true,true,false> reg_iterator; 212193323Sed reg_iterator reg_begin(unsigned RegNo) const { 213193323Sed return reg_iterator(getRegUseDefListHead(RegNo)); 214193323Sed } 215193323Sed static reg_iterator reg_end() { return reg_iterator(0); } 216193323Sed 217193323Sed /// reg_empty - Return true if there are no instructions using or defining the 218193323Sed /// specified register (it may be live-in). 219193323Sed bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 220193323Sed 221208599Srdivacky /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 222208599Srdivacky /// of the specified register, skipping those marked as Debug. 223208599Srdivacky typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 224208599Srdivacky reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 225208599Srdivacky return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 226208599Srdivacky } 227208599Srdivacky static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 228208599Srdivacky 229208599Srdivacky /// reg_nodbg_empty - Return true if the only instructions using or defining 230208599Srdivacky /// Reg are Debug instructions. 231208599Srdivacky bool reg_nodbg_empty(unsigned RegNo) const { 232208599Srdivacky return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 233208599Srdivacky } 234208599Srdivacky 235193323Sed /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 236203954Srdivacky typedef defusechain_iterator<false,true,false> def_iterator; 237193323Sed def_iterator def_begin(unsigned RegNo) const { 238193323Sed return def_iterator(getRegUseDefListHead(RegNo)); 239193323Sed } 240193323Sed static def_iterator def_end() { return def_iterator(0); } 241193323Sed 242193323Sed /// def_empty - Return true if there are no instructions defining the 243193323Sed /// specified register (it may be live-in). 244193323Sed bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 245193323Sed 246239462Sdim /// hasOneDef - Return true if there is exactly one instruction defining the 247239462Sdim /// specified register. 248239462Sdim bool hasOneDef(unsigned RegNo) const { 249239462Sdim def_iterator DI = def_begin(RegNo); 250239462Sdim if (DI == def_end()) 251239462Sdim return false; 252239462Sdim return ++DI == def_end(); 253239462Sdim } 254239462Sdim 255193323Sed /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 256203954Srdivacky typedef defusechain_iterator<true,false,false> use_iterator; 257193323Sed use_iterator use_begin(unsigned RegNo) const { 258193323Sed return use_iterator(getRegUseDefListHead(RegNo)); 259193323Sed } 260193323Sed static use_iterator use_end() { return use_iterator(0); } 261234353Sdim 262193323Sed /// use_empty - Return true if there are no instructions using the specified 263193323Sed /// register. 264193323Sed bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 265193323Sed 266204792Srdivacky /// hasOneUse - Return true if there is exactly one instruction using the 267204792Srdivacky /// specified register. 268239462Sdim bool hasOneUse(unsigned RegNo) const { 269239462Sdim use_iterator UI = use_begin(RegNo); 270239462Sdim if (UI == use_end()) 271239462Sdim return false; 272239462Sdim return ++UI == use_end(); 273239462Sdim } 274204792Srdivacky 275203954Srdivacky /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 276203954Srdivacky /// specified register, skipping those marked as Debug. 277203954Srdivacky typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 278203954Srdivacky use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 279203954Srdivacky return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 280203954Srdivacky } 281203954Srdivacky static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 282234353Sdim 283203954Srdivacky /// use_nodbg_empty - Return true if there are no non-Debug instructions 284203954Srdivacky /// using the specified register. 285203954Srdivacky bool use_nodbg_empty(unsigned RegNo) const { 286203954Srdivacky return use_nodbg_begin(RegNo) == use_nodbg_end(); 287203954Srdivacky } 288203954Srdivacky 289204792Srdivacky /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 290204792Srdivacky /// instruction using the specified register. 291204792Srdivacky bool hasOneNonDBGUse(unsigned RegNo) const; 292204792Srdivacky 293193323Sed /// replaceRegWith - Replace all instances of FromReg with ToReg in the 294193323Sed /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 295193323Sed /// except that it also changes any definitions of the register as well. 296234353Sdim /// 297234353Sdim /// Note that it is usually necessary to first constrain ToReg's register 298234353Sdim /// class to match the FromReg constraints using: 299234353Sdim /// 300234353Sdim /// constrainRegClass(ToReg, getRegClass(FromReg)) 301234353Sdim /// 302234353Sdim /// That function will return NULL if the virtual registers have incompatible 303234353Sdim /// constraints. 304193323Sed void replaceRegWith(unsigned FromReg, unsigned ToReg); 305234353Sdim 306193323Sed /// getVRegDef - Return the machine instr that defines the specified virtual 307193323Sed /// register or null if none is found. This assumes that the code is in SSA 308193323Sed /// form, so there should only be one definition. 309193323Sed MachineInstr *getVRegDef(unsigned Reg) const; 310208599Srdivacky 311239462Sdim /// getUniqueVRegDef - Return the unique machine instr that defines the 312239462Sdim /// specified virtual register or null if none is found. If there are 313239462Sdim /// multiple definitions or no definition, return null. 314239462Sdim MachineInstr *getUniqueVRegDef(unsigned Reg) const; 315239462Sdim 316208599Srdivacky /// clearKillFlags - Iterate over all the uses of the given register and 317208599Srdivacky /// clear the kill flag from the MachineOperand. This function is used by 318208599Srdivacky /// optimization passes which extend register lifetimes and need only 319208599Srdivacky /// preserve conservative kill flag information. 320208599Srdivacky void clearKillFlags(unsigned Reg) const; 321234353Sdim 322193323Sed#ifndef NDEBUG 323193323Sed void dumpUses(unsigned RegNo) const; 324193323Sed#endif 325234353Sdim 326234353Sdim /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 327234353Sdim /// throughout the function. It is safe to move instructions that read such 328234353Sdim /// a physreg. 329234353Sdim bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 330234353Sdim 331263508Sdim /// Get an iterator over the pressure sets affected by the given physical or 332263508Sdim /// virtual register. If RegUnit is physical, it must be a register unit (from 333263508Sdim /// MCRegUnitIterator). 334263508Sdim PSetIterator getPressureSets(unsigned RegUnit) const; 335263508Sdim 336193323Sed //===--------------------------------------------------------------------===// 337193323Sed // Virtual Register Info 338193323Sed //===--------------------------------------------------------------------===// 339234353Sdim 340193323Sed /// getRegClass - Return the register class of the specified virtual register. 341193323Sed /// 342193323Sed const TargetRegisterClass *getRegClass(unsigned Reg) const { 343193323Sed return VRegInfo[Reg].first; 344193323Sed } 345193323Sed 346193323Sed /// setRegClass - Set the register class of the specified virtual register. 347193323Sed /// 348193323Sed void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 349193323Sed 350218893Sdim /// constrainRegClass - Constrain the register class of the specified virtual 351226633Sdim /// register to be a common subclass of RC and the current register class, 352226633Sdim /// but only if the new class has at least MinNumRegs registers. Return the 353226633Sdim /// new register class, or NULL if no such class exists. 354218893Sdim /// This should only be used when the constraint is known to be trivial, like 355218893Sdim /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 356226633Sdim /// 357218893Sdim const TargetRegisterClass *constrainRegClass(unsigned Reg, 358226633Sdim const TargetRegisterClass *RC, 359226633Sdim unsigned MinNumRegs = 0); 360218893Sdim 361226633Sdim /// recomputeRegClass - Try to find a legal super-class of Reg's register 362226633Sdim /// class that still satisfies the constraints from the instructions using 363226633Sdim /// Reg. Returns true if Reg was upgraded. 364226633Sdim /// 365226633Sdim /// This method can be used after constraints have been removed from a 366226633Sdim /// virtual register, for example after removing instructions or splitting 367226633Sdim /// the live range. 368226633Sdim /// 369226633Sdim bool recomputeRegClass(unsigned Reg, const TargetMachine&); 370226633Sdim 371193323Sed /// createVirtualRegister - Create and return a new virtual register in the 372193323Sed /// function with the specified register class. 373193323Sed /// 374193323Sed unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 375193323Sed 376218893Sdim /// getNumVirtRegs - Return the number of virtual registers created. 377193323Sed /// 378218893Sdim unsigned getNumVirtRegs() const { return VRegInfo.size(); } 379193323Sed 380234353Sdim /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 381234353Sdim void clearVirtRegs(); 382234353Sdim 383194612Sed /// setRegAllocationHint - Specify a register allocation hint for the 384194612Sed /// specified virtual register. 385194612Sed void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 386194612Sed RegAllocHints[Reg].first = Type; 387194612Sed RegAllocHints[Reg].second = PrefReg; 388194612Sed } 389194612Sed 390194612Sed /// getRegAllocationHint - Return the register allocation hint for the 391194612Sed /// specified virtual register. 392194612Sed std::pair<unsigned, unsigned> 393194612Sed getRegAllocationHint(unsigned Reg) const { 394194612Sed return RegAllocHints[Reg]; 395194612Sed } 396194612Sed 397224145Sdim /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 398224145Sdim /// standard simple hint (Type == 0) is not set. 399224145Sdim unsigned getSimpleHint(unsigned Reg) const { 400224145Sdim std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 401224145Sdim return Hint.first ? 0 : Hint.second; 402224145Sdim } 403224145Sdim 404224145Sdim 405193323Sed //===--------------------------------------------------------------------===// 406193323Sed // Physical Register Use Info 407193323Sed //===--------------------------------------------------------------------===// 408234353Sdim 409193323Sed /// isPhysRegUsed - Return true if the specified register is used in this 410243830Sdim /// function. Also check for clobbered aliases and registers clobbered by 411243830Sdim /// function calls with register mask operands. 412243830Sdim /// 413243830Sdim /// This only works after register allocation. It is primarily used by 414243830Sdim /// PrologEpilogInserter to determine which callee-saved registers need 415243830Sdim /// spilling. 416234353Sdim bool isPhysRegUsed(unsigned Reg) const { 417234353Sdim if (UsedPhysRegMask.test(Reg)) 418234353Sdim return true; 419263508Sdim for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 420263508Sdim Units.isValid(); ++Units) 421243830Sdim if (UsedRegUnits.test(*Units)) 422234353Sdim return true; 423234353Sdim return false; 424234353Sdim } 425234353Sdim 426249423Sdim /// Mark the specified register unit as used in this function. 427249423Sdim /// This should only be called during and after register allocation. 428249423Sdim void setRegUnitUsed(unsigned RegUnit) { 429249423Sdim UsedRegUnits.set(RegUnit); 430249423Sdim } 431249423Sdim 432193323Sed /// setPhysRegUsed - Mark the specified register used in this function. 433193323Sed /// This should only be called during and after register allocation. 434243830Sdim void setPhysRegUsed(unsigned Reg) { 435263508Sdim for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 436263508Sdim Units.isValid(); ++Units) 437243830Sdim UsedRegUnits.set(*Units); 438243830Sdim } 439208599Srdivacky 440234353Sdim /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 441234353Sdim /// This corresponds to the bit mask attached to register mask operands. 442234353Sdim void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 443234353Sdim UsedPhysRegMask.setBitsNotInMask(RegMask); 444234353Sdim } 445234353Sdim 446193323Sed /// setPhysRegUnused - Mark the specified register unused in this function. 447193323Sed /// This should only be called during and after register allocation. 448234353Sdim void setPhysRegUnused(unsigned Reg) { 449234353Sdim UsedPhysRegMask.reset(Reg); 450263508Sdim for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 451263508Sdim Units.isValid(); ++Units) 452243830Sdim UsedRegUnits.reset(*Units); 453234353Sdim } 454193323Sed 455208599Srdivacky 456193323Sed //===--------------------------------------------------------------------===// 457234353Sdim // Reserved Register Info 458234353Sdim //===--------------------------------------------------------------------===// 459234353Sdim // 460234353Sdim // The set of reserved registers must be invariant during register 461234353Sdim // allocation. For example, the target cannot suddenly decide it needs a 462234353Sdim // frame pointer when the register allocator has already used the frame 463234353Sdim // pointer register for something else. 464234353Sdim // 465234353Sdim // These methods can be used by target hooks like hasFP() to avoid changing 466234353Sdim // the reserved register set during register allocation. 467234353Sdim 468234353Sdim /// freezeReservedRegs - Called by the register allocator to freeze the set 469234353Sdim /// of reserved registers before allocation begins. 470234353Sdim void freezeReservedRegs(const MachineFunction&); 471234353Sdim 472234353Sdim /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 473234353Sdim /// to ensure the set of reserved registers stays constant. 474234353Sdim bool reservedRegsFrozen() const { 475234353Sdim return !ReservedRegs.empty(); 476234353Sdim } 477234353Sdim 478234353Sdim /// canReserveReg - Returns true if PhysReg can be used as a reserved 479234353Sdim /// register. Any register can be reserved before freezeReservedRegs() is 480234353Sdim /// called. 481234353Sdim bool canReserveReg(unsigned PhysReg) const { 482234353Sdim return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 483234353Sdim } 484234353Sdim 485243830Sdim /// getReservedRegs - Returns a reference to the frozen set of reserved 486243830Sdim /// registers. This method should always be preferred to calling 487243830Sdim /// TRI::getReservedRegs() when possible. 488243830Sdim const BitVector &getReservedRegs() const { 489243830Sdim assert(reservedRegsFrozen() && 490243830Sdim "Reserved registers haven't been frozen yet. " 491243830Sdim "Use TRI::getReservedRegs()."); 492243830Sdim return ReservedRegs; 493243830Sdim } 494234353Sdim 495243830Sdim /// isReserved - Returns true when PhysReg is a reserved register. 496243830Sdim /// 497243830Sdim /// Reserved registers may belong to an allocatable register class, but the 498243830Sdim /// target has explicitly requested that they are not used. 499243830Sdim /// 500243830Sdim bool isReserved(unsigned PhysReg) const { 501243830Sdim return getReservedRegs().test(PhysReg); 502243830Sdim } 503243830Sdim 504243830Sdim /// isAllocatable - Returns true when PhysReg belongs to an allocatable 505243830Sdim /// register class and it hasn't been reserved. 506243830Sdim /// 507243830Sdim /// Allocatable registers may show up in the allocation order of some virtual 508243830Sdim /// register, so a register allocator needs to track its liveness and 509243830Sdim /// availability. 510243830Sdim bool isAllocatable(unsigned PhysReg) const { 511263508Sdim return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 512263508Sdim !isReserved(PhysReg); 513243830Sdim } 514243830Sdim 515234353Sdim //===--------------------------------------------------------------------===// 516249423Sdim // LiveIn Management 517193323Sed //===--------------------------------------------------------------------===// 518234353Sdim 519249423Sdim /// addLiveIn - Add the specified register as a live-in. Note that it 520193323Sed /// is an error to add the same register to the same set more than once. 521193323Sed void addLiveIn(unsigned Reg, unsigned vreg = 0) { 522193323Sed LiveIns.push_back(std::make_pair(Reg, vreg)); 523193323Sed } 524234353Sdim 525249423Sdim // Iteration support for the live-ins set. It's kept in sorted order 526249423Sdim // by register number. 527193323Sed typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 528193323Sed livein_iterator; 529193323Sed livein_iterator livein_begin() const { return LiveIns.begin(); } 530193323Sed livein_iterator livein_end() const { return LiveIns.end(); } 531193323Sed bool livein_empty() const { return LiveIns.empty(); } 532193323Sed 533207618Srdivacky bool isLiveIn(unsigned Reg) const; 534193323Sed 535207618Srdivacky /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 536207618Srdivacky /// corresponding live-in physical register. 537207618Srdivacky unsigned getLiveInPhysReg(unsigned VReg) const; 538207618Srdivacky 539208599Srdivacky /// getLiveInVirtReg - If PReg is a live-in physical register, return the 540208599Srdivacky /// corresponding live-in physical register. 541208599Srdivacky unsigned getLiveInVirtReg(unsigned PReg) const; 542208599Srdivacky 543207618Srdivacky /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 544207618Srdivacky /// into the given entry block. 545207618Srdivacky void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 546207618Srdivacky const TargetRegisterInfo &TRI, 547207618Srdivacky const TargetInstrInfo &TII); 548207618Srdivacky 549193323Sed /// defusechain_iterator - This class provides iterator support for machine 550193323Sed /// operands in the function that use or define a specific register. If 551193323Sed /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 552193323Sed /// returns defs. If neither are true then you are silly and it always 553203954Srdivacky /// returns end(). If SkipDebug is true it skips uses marked Debug 554203954Srdivacky /// when incrementing. 555203954Srdivacky template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 556193323Sed class defusechain_iterator 557198090Srdivacky : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 558193323Sed MachineOperand *Op; 559193323Sed explicit defusechain_iterator(MachineOperand *op) : Op(op) { 560193323Sed // If the first node isn't one we're interested in, advance to one that 561193323Sed // we are interested in. 562193323Sed if (op) { 563193323Sed if ((!ReturnUses && op->isUse()) || 564203954Srdivacky (!ReturnDefs && op->isDef()) || 565203954Srdivacky (SkipDebug && op->isDebug())) 566193323Sed ++*this; 567193323Sed } 568193323Sed } 569193323Sed friend class MachineRegisterInfo; 570193323Sed public: 571198090Srdivacky typedef std::iterator<std::forward_iterator_tag, 572198090Srdivacky MachineInstr, ptrdiff_t>::reference reference; 573198090Srdivacky typedef std::iterator<std::forward_iterator_tag, 574198090Srdivacky MachineInstr, ptrdiff_t>::pointer pointer; 575234353Sdim 576193323Sed defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 577193323Sed defusechain_iterator() : Op(0) {} 578234353Sdim 579193323Sed bool operator==(const defusechain_iterator &x) const { 580193323Sed return Op == x.Op; 581193323Sed } 582193323Sed bool operator!=(const defusechain_iterator &x) const { 583193323Sed return !operator==(x); 584193323Sed } 585234353Sdim 586193323Sed /// atEnd - return true if this iterator is equal to reg_end() on the value. 587193323Sed bool atEnd() const { return Op == 0; } 588234353Sdim 589193323Sed // Iterator traversal: forward iteration only 590193323Sed defusechain_iterator &operator++() { // Preincrement 591193323Sed assert(Op && "Cannot increment end iterator!"); 592239462Sdim Op = getNextOperandForReg(Op); 593234353Sdim 594239462Sdim // All defs come before the uses, so stop def_iterator early. 595239462Sdim if (!ReturnUses) { 596239462Sdim if (Op) { 597239462Sdim if (Op->isUse()) 598239462Sdim Op = 0; 599239462Sdim else 600239462Sdim assert(!Op->isDebug() && "Can't have debug defs"); 601239462Sdim } 602239462Sdim } else { 603239462Sdim // If this is an operand we don't care about, skip it. 604239462Sdim while (Op && ((!ReturnDefs && Op->isDef()) || 605239462Sdim (SkipDebug && Op->isDebug()))) 606239462Sdim Op = getNextOperandForReg(Op); 607239462Sdim } 608234353Sdim 609193323Sed return *this; 610193323Sed } 611193323Sed defusechain_iterator operator++(int) { // Postincrement 612193323Sed defusechain_iterator tmp = *this; ++*this; return tmp; 613193323Sed } 614210299Sed 615210299Sed /// skipInstruction - move forward until reaching a different instruction. 616210299Sed /// Return the skipped instruction that is no longer pointed to, or NULL if 617210299Sed /// already pointing to end(). 618210299Sed MachineInstr *skipInstruction() { 619210299Sed if (!Op) return 0; 620210299Sed MachineInstr *MI = Op->getParent(); 621210299Sed do ++*this; 622210299Sed while (Op && Op->getParent() == MI); 623210299Sed return MI; 624210299Sed } 625210299Sed 626234353Sdim MachineInstr *skipBundle() { 627234353Sdim if (!Op) return 0; 628234353Sdim MachineInstr *MI = getBundleStart(Op->getParent()); 629234353Sdim do ++*this; 630234353Sdim while (Op && getBundleStart(Op->getParent()) == MI); 631234353Sdim return MI; 632234353Sdim } 633234353Sdim 634193323Sed MachineOperand &getOperand() const { 635193323Sed assert(Op && "Cannot dereference end iterator!"); 636193323Sed return *Op; 637193323Sed } 638234353Sdim 639193323Sed /// getOperandNo - Return the operand # of this MachineOperand in its 640193323Sed /// MachineInstr. 641193323Sed unsigned getOperandNo() const { 642193323Sed assert(Op && "Cannot dereference end iterator!"); 643193323Sed return Op - &Op->getParent()->getOperand(0); 644193323Sed } 645234353Sdim 646193323Sed // Retrieve a reference to the current operand. 647193323Sed MachineInstr &operator*() const { 648193323Sed assert(Op && "Cannot dereference end iterator!"); 649193323Sed return *Op->getParent(); 650193323Sed } 651234353Sdim 652193323Sed MachineInstr *operator->() const { 653193323Sed assert(Op && "Cannot dereference end iterator!"); 654193323Sed return Op->getParent(); 655193323Sed } 656193323Sed }; 657263508Sdim}; 658234353Sdim 659263508Sdim/// Iterate over the pressure sets affected by the given physical or virtual 660263508Sdim/// register. If Reg is physical, it must be a register unit (from 661263508Sdim/// MCRegUnitIterator). 662263508Sdimclass PSetIterator { 663263508Sdim const int *PSet; 664263508Sdim unsigned Weight; 665263508Sdimpublic: 666263508Sdim PSetIterator(): PSet(0), Weight(0) {} 667263508Sdim PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { 668263508Sdim const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 669263508Sdim if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { 670263508Sdim const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 671263508Sdim PSet = TRI->getRegClassPressureSets(RC); 672263508Sdim Weight = TRI->getRegClassWeight(RC).RegWeight; 673263508Sdim } 674263508Sdim else { 675263508Sdim PSet = TRI->getRegUnitPressureSets(RegUnit); 676263508Sdim Weight = TRI->getRegUnitWeight(RegUnit); 677263508Sdim } 678263508Sdim if (*PSet == -1) 679263508Sdim PSet = 0; 680263508Sdim } 681263508Sdim bool isValid() const { return PSet; } 682263508Sdim 683263508Sdim unsigned getWeight() const { return Weight; } 684263508Sdim 685263508Sdim unsigned operator*() const { return *PSet; } 686263508Sdim 687263508Sdim void operator++() { 688263508Sdim assert(isValid() && "Invalid PSetIterator."); 689263508Sdim ++PSet; 690263508Sdim if (*PSet == -1) 691263508Sdim PSet = 0; 692263508Sdim } 693193323Sed}; 694193323Sed 695263508Sdiminline PSetIterator MachineRegisterInfo:: 696263508SdimgetPressureSets(unsigned RegUnit) const { 697263508Sdim return PSetIterator(RegUnit, this); 698263508Sdim} 699263508Sdim 700193323Sed} // End llvm namespace 701193323Sed 702193323Sed#endif 703