1130812Smarcel/* Common target dependent code for GDB on ARM systems. 2130812Smarcel Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, 3130812Smarcel 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4130812Smarcel 5130812Smarcel This file is part of GDB. 6130812Smarcel 7130812Smarcel This program is free software; you can redistribute it and/or modify 8130812Smarcel it under the terms of the GNU General Public License as published by 9130812Smarcel the Free Software Foundation; either version 2 of the License, or 10130812Smarcel (at your option) any later version. 11130812Smarcel 12130812Smarcel This program is distributed in the hope that it will be useful, 13130812Smarcel but WITHOUT ANY WARRANTY; without even the implied warranty of 14130812Smarcel MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15130812Smarcel GNU General Public License for more details. 16130812Smarcel 17130812Smarcel You should have received a copy of the GNU General Public License 18130812Smarcel along with this program; if not, write to the Free Software 19130812Smarcel Foundation, Inc., 59 Temple Place - Suite 330, 20130812Smarcel Boston, MA 02111-1307, USA. */ 21130812Smarcel 22130812Smarcel#include <ctype.h> /* XXX for isupper () */ 23130812Smarcel 24130812Smarcel#include "defs.h" 25130812Smarcel#include "frame.h" 26130812Smarcel#include "inferior.h" 27130812Smarcel#include "gdbcmd.h" 28130812Smarcel#include "gdbcore.h" 29130812Smarcel#include "gdb_string.h" 30130812Smarcel#include "dis-asm.h" /* For register styles. */ 31130812Smarcel#include "regcache.h" 32130812Smarcel#include "doublest.h" 33130812Smarcel#include "value.h" 34130812Smarcel#include "arch-utils.h" 35130812Smarcel#include "osabi.h" 36130812Smarcel#include "frame-unwind.h" 37130812Smarcel#include "frame-base.h" 38130812Smarcel#include "trad-frame.h" 39130812Smarcel 40130812Smarcel#include "arm-tdep.h" 41130812Smarcel#include "gdb/sim-arm.h" 42130812Smarcel 43130812Smarcel#include "elf-bfd.h" 44130812Smarcel#include "coff/internal.h" 45130812Smarcel#include "elf/arm.h" 46130812Smarcel 47130812Smarcel#include "gdb_assert.h" 48130812Smarcel 49130812Smarcelstatic int arm_debug; 50130812Smarcel 51130812Smarcel/* Each OS has a different mechanism for accessing the various 52130812Smarcel registers stored in the sigcontext structure. 53130812Smarcel 54130812Smarcel SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or 55130812Smarcel function pointer) which may be used to determine the addresses 56130812Smarcel of the various saved registers in the sigcontext structure. 57130812Smarcel 58130812Smarcel For the ARM target, there are three parameters to this function. 59130812Smarcel The first is the pc value of the frame under consideration, the 60130812Smarcel second the stack pointer of this frame, and the last is the 61130812Smarcel register number to fetch. 62130812Smarcel 63130812Smarcel If the tm.h file does not define this macro, then it's assumed that 64130812Smarcel no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to 65130812Smarcel be 0. 66130812Smarcel 67130812Smarcel When it comes time to multi-arching this code, see the identically 68130812Smarcel named machinery in ia64-tdep.c for an example of how it could be 69130812Smarcel done. It should not be necessary to modify the code below where 70130812Smarcel this macro is used. */ 71130812Smarcel 72130812Smarcel#ifdef SIGCONTEXT_REGISTER_ADDRESS 73130812Smarcel#ifndef SIGCONTEXT_REGISTER_ADDRESS_P 74130812Smarcel#define SIGCONTEXT_REGISTER_ADDRESS_P() 1 75130812Smarcel#endif 76130812Smarcel#else 77130812Smarcel#define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 78130812Smarcel#define SIGCONTEXT_REGISTER_ADDRESS_P() 0 79130812Smarcel#endif 80130812Smarcel 81130812Smarcel/* Macros for setting and testing a bit in a minimal symbol that marks 82130812Smarcel it as Thumb function. The MSB of the minimal symbol's "info" field 83130812Smarcel is used for this purpose. 84130812Smarcel 85130812Smarcel MSYMBOL_SET_SPECIAL Actually sets the "special" bit. 86130812Smarcel MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ 87130812Smarcel 88130812Smarcel#define MSYMBOL_SET_SPECIAL(msym) \ 89130812Smarcel MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ 90130812Smarcel | 0x80000000) 91130812Smarcel 92130812Smarcel#define MSYMBOL_IS_SPECIAL(msym) \ 93130812Smarcel (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) 94130812Smarcel 95130812Smarcel/* The list of available "set arm ..." and "show arm ..." commands. */ 96130812Smarcelstatic struct cmd_list_element *setarmcmdlist = NULL; 97130812Smarcelstatic struct cmd_list_element *showarmcmdlist = NULL; 98130812Smarcel 99130812Smarcel/* The type of floating-point to use. Keep this in sync with enum 100130812Smarcel arm_float_model, and the help string in _initialize_arm_tdep. */ 101130812Smarcelstatic const char *fp_model_strings[] = 102130812Smarcel{ 103130812Smarcel "auto", 104130812Smarcel "softfpa", 105130812Smarcel "fpa", 106130812Smarcel "softvfp", 107130812Smarcel "vfp" 108130812Smarcel}; 109130812Smarcel 110130812Smarcel/* A variable that can be configured by the user. */ 111130812Smarcelstatic enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; 112130812Smarcelstatic const char *current_fp_model = "auto"; 113130812Smarcel 114130812Smarcel/* Number of different reg name sets (options). */ 115130812Smarcelstatic int num_disassembly_options; 116130812Smarcel 117130812Smarcel/* We have more registers than the disassembler as gdb can print the value 118130812Smarcel of special registers as well. 119130812Smarcel The general register names are overwritten by whatever is being used by 120130812Smarcel the disassembler at the moment. We also adjust the case of cpsr and fps. */ 121130812Smarcel 122130812Smarcel/* Initial value: Register names used in ARM's ISA documentation. */ 123130812Smarcelstatic char * arm_register_name_strings[] = 124130812Smarcel{"r0", "r1", "r2", "r3", /* 0 1 2 3 */ 125130812Smarcel "r4", "r5", "r6", "r7", /* 4 5 6 7 */ 126130812Smarcel "r8", "r9", "r10", "r11", /* 8 9 10 11 */ 127130812Smarcel "r12", "sp", "lr", "pc", /* 12 13 14 15 */ 128130812Smarcel "f0", "f1", "f2", "f3", /* 16 17 18 19 */ 129130812Smarcel "f4", "f5", "f6", "f7", /* 20 21 22 23 */ 130130812Smarcel "fps", "cpsr" }; /* 24 25 */ 131130812Smarcelstatic char **arm_register_names = arm_register_name_strings; 132130812Smarcel 133130812Smarcel/* Valid register name styles. */ 134130812Smarcelstatic const char **valid_disassembly_styles; 135130812Smarcel 136130812Smarcel/* Disassembly style to use. Default to "std" register names. */ 137130812Smarcelstatic const char *disassembly_style; 138130812Smarcel/* Index to that option in the opcodes table. */ 139130812Smarcelstatic int current_option; 140130812Smarcel 141130812Smarcel/* This is used to keep the bfd arch_info in sync with the disassembly 142130812Smarcel style. */ 143130812Smarcelstatic void set_disassembly_style_sfunc(char *, int, 144130812Smarcel struct cmd_list_element *); 145130812Smarcelstatic void set_disassembly_style (void); 146130812Smarcel 147130812Smarcelstatic void convert_from_extended (const struct floatformat *, const void *, 148130812Smarcel void *); 149130812Smarcelstatic void convert_to_extended (const struct floatformat *, void *, 150130812Smarcel const void *); 151130812Smarcel 152130812Smarcelstruct arm_prologue_cache 153130812Smarcel{ 154130812Smarcel /* The stack pointer at the time this frame was created; i.e. the 155130812Smarcel caller's stack pointer when this function was called. It is used 156130812Smarcel to identify this frame. */ 157130812Smarcel CORE_ADDR prev_sp; 158130812Smarcel 159130812Smarcel /* The frame base for this frame is just prev_sp + frame offset - 160130812Smarcel frame size. FRAMESIZE is the size of this stack frame, and 161130812Smarcel FRAMEOFFSET if the initial offset from the stack pointer (this 162130812Smarcel frame's stack pointer, not PREV_SP) to the frame base. */ 163130812Smarcel 164130812Smarcel int framesize; 165130812Smarcel int frameoffset; 166130812Smarcel 167130812Smarcel /* The register used to hold the frame pointer for this frame. */ 168130812Smarcel int framereg; 169130812Smarcel 170130812Smarcel /* Saved register offsets. */ 171130812Smarcel struct trad_frame_saved_reg *saved_regs; 172130812Smarcel}; 173130812Smarcel 174130812Smarcel/* Addresses for calling Thumb functions have the bit 0 set. 175130812Smarcel Here are some macros to test, set, or clear bit 0 of addresses. */ 176130812Smarcel#define IS_THUMB_ADDR(addr) ((addr) & 1) 177130812Smarcel#define MAKE_THUMB_ADDR(addr) ((addr) | 1) 178130812Smarcel#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) 179130812Smarcel 180130812Smarcel/* Set to true if the 32-bit mode is in use. */ 181130812Smarcel 182130812Smarcelint arm_apcs_32 = 1; 183130812Smarcel 184130812Smarcel/* Determine if the program counter specified in MEMADDR is in a Thumb 185130812Smarcel function. */ 186130812Smarcel 187130812Smarcelint 188130812Smarcelarm_pc_is_thumb (CORE_ADDR memaddr) 189130812Smarcel{ 190130812Smarcel struct minimal_symbol *sym; 191130812Smarcel 192130812Smarcel /* If bit 0 of the address is set, assume this is a Thumb address. */ 193130812Smarcel if (IS_THUMB_ADDR (memaddr)) 194130812Smarcel return 1; 195130812Smarcel 196130812Smarcel /* Thumb functions have a "special" bit set in minimal symbols. */ 197130812Smarcel sym = lookup_minimal_symbol_by_pc (memaddr); 198130812Smarcel if (sym) 199130812Smarcel { 200130812Smarcel return (MSYMBOL_IS_SPECIAL (sym)); 201130812Smarcel } 202130812Smarcel else 203130812Smarcel { 204130812Smarcel return 0; 205130812Smarcel } 206130812Smarcel} 207130812Smarcel 208130812Smarcel/* Remove useless bits from addresses in a running program. */ 209130812Smarcelstatic CORE_ADDR 210130812Smarcelarm_addr_bits_remove (CORE_ADDR val) 211130812Smarcel{ 212130812Smarcel if (arm_apcs_32) 213130812Smarcel return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); 214130812Smarcel else 215130812Smarcel return (val & 0x03fffffc); 216130812Smarcel} 217130812Smarcel 218130812Smarcel/* When reading symbols, we need to zap the low bit of the address, 219130812Smarcel which may be set to 1 for Thumb functions. */ 220130812Smarcelstatic CORE_ADDR 221130812Smarcelarm_smash_text_address (CORE_ADDR val) 222130812Smarcel{ 223130812Smarcel return val & ~1; 224130812Smarcel} 225130812Smarcel 226130812Smarcel/* Immediately after a function call, return the saved pc. Can't 227130812Smarcel always go through the frames for this because on some machines the 228130812Smarcel new frame is not set up until the new function executes some 229130812Smarcel instructions. */ 230130812Smarcel 231130812Smarcelstatic CORE_ADDR 232130812Smarcelarm_saved_pc_after_call (struct frame_info *frame) 233130812Smarcel{ 234130812Smarcel return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); 235130812Smarcel} 236130812Smarcel 237130812Smarcel/* Determine whether the function invocation represented by FI has a 238130812Smarcel frame on the stack associated with it. If it does return zero, 239130812Smarcel otherwise return 1. */ 240130812Smarcel 241130812Smarcelstatic int 242130812Smarcelarm_frameless_function_invocation (struct frame_info *fi) 243130812Smarcel{ 244130812Smarcel CORE_ADDR func_start, after_prologue; 245130812Smarcel int frameless; 246130812Smarcel 247130812Smarcel /* Sometimes we have functions that do a little setup (like saving the 248130812Smarcel vN registers with the stmdb instruction, but DO NOT set up a frame. 249130812Smarcel The symbol table will report this as a prologue. However, it is 250130812Smarcel important not to try to parse these partial frames as frames, or we 251130812Smarcel will get really confused. 252130812Smarcel 253130812Smarcel So I will demand 3 instructions between the start & end of the 254130812Smarcel prologue before I call it a real prologue, i.e. at least 255130812Smarcel mov ip, sp, 256130812Smarcel stmdb sp!, {} 257130812Smarcel sub sp, ip, #4. */ 258130812Smarcel 259130812Smarcel func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET); 260130812Smarcel after_prologue = SKIP_PROLOGUE (func_start); 261130812Smarcel 262130812Smarcel /* There are some frameless functions whose first two instructions 263130812Smarcel follow the standard APCS form, in which case after_prologue will 264130812Smarcel be func_start + 8. */ 265130812Smarcel 266130812Smarcel frameless = (after_prologue < func_start + 12); 267130812Smarcel return frameless; 268130812Smarcel} 269130812Smarcel 270130812Smarcel/* A typical Thumb prologue looks like this: 271130812Smarcel push {r7, lr} 272130812Smarcel add sp, sp, #-28 273130812Smarcel add r7, sp, #12 274130812Smarcel Sometimes the latter instruction may be replaced by: 275130812Smarcel mov r7, sp 276130812Smarcel 277130812Smarcel or like this: 278130812Smarcel push {r7, lr} 279130812Smarcel mov r7, sp 280130812Smarcel sub sp, #12 281130812Smarcel 282130812Smarcel or, on tpcs, like this: 283130812Smarcel sub sp,#16 284130812Smarcel push {r7, lr} 285130812Smarcel (many instructions) 286130812Smarcel mov r7, sp 287130812Smarcel sub sp, #12 288130812Smarcel 289130812Smarcel There is always one instruction of three classes: 290130812Smarcel 1 - push 291130812Smarcel 2 - setting of r7 292130812Smarcel 3 - adjusting of sp 293130812Smarcel 294130812Smarcel When we have found at least one of each class we are done with the prolog. 295130812Smarcel Note that the "sub sp, #NN" before the push does not count. 296130812Smarcel */ 297130812Smarcel 298130812Smarcelstatic CORE_ADDR 299130812Smarcelthumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) 300130812Smarcel{ 301130812Smarcel CORE_ADDR current_pc; 302130812Smarcel /* findmask: 303130812Smarcel bit 0 - push { rlist } 304130812Smarcel bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) 305130812Smarcel bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) 306130812Smarcel */ 307130812Smarcel int findmask = 0; 308130812Smarcel 309130812Smarcel for (current_pc = pc; 310130812Smarcel current_pc + 2 < func_end && current_pc < pc + 40; 311130812Smarcel current_pc += 2) 312130812Smarcel { 313130812Smarcel unsigned short insn = read_memory_unsigned_integer (current_pc, 2); 314130812Smarcel 315130812Smarcel if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ 316130812Smarcel { 317130812Smarcel findmask |= 1; /* push found */ 318130812Smarcel } 319130812Smarcel else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR 320130812Smarcel sub sp, #simm */ 321130812Smarcel { 322130812Smarcel if ((findmask & 1) == 0) /* before push ? */ 323130812Smarcel continue; 324130812Smarcel else 325130812Smarcel findmask |= 4; /* add/sub sp found */ 326130812Smarcel } 327130812Smarcel else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ 328130812Smarcel { 329130812Smarcel findmask |= 2; /* setting of r7 found */ 330130812Smarcel } 331130812Smarcel else if (insn == 0x466f) /* mov r7, sp */ 332130812Smarcel { 333130812Smarcel findmask |= 2; /* setting of r7 found */ 334130812Smarcel } 335130812Smarcel else if (findmask == (4+2+1)) 336130812Smarcel { 337130812Smarcel /* We have found one of each type of prologue instruction */ 338130812Smarcel break; 339130812Smarcel } 340130812Smarcel else 341130812Smarcel /* Something in the prolog that we don't care about or some 342130812Smarcel instruction from outside the prolog scheduled here for 343130812Smarcel optimization. */ 344130812Smarcel continue; 345130812Smarcel } 346130812Smarcel 347130812Smarcel return current_pc; 348130812Smarcel} 349130812Smarcel 350130812Smarcel/* Advance the PC across any function entry prologue instructions to 351130812Smarcel reach some "real" code. 352130812Smarcel 353130812Smarcel The APCS (ARM Procedure Call Standard) defines the following 354130812Smarcel prologue: 355130812Smarcel 356130812Smarcel mov ip, sp 357130812Smarcel [stmfd sp!, {a1,a2,a3,a4}] 358130812Smarcel stmfd sp!, {...,fp,ip,lr,pc} 359130812Smarcel [stfe f7, [sp, #-12]!] 360130812Smarcel [stfe f6, [sp, #-12]!] 361130812Smarcel [stfe f5, [sp, #-12]!] 362130812Smarcel [stfe f4, [sp, #-12]!] 363130812Smarcel sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ 364130812Smarcel 365130812Smarcelstatic CORE_ADDR 366130812Smarcelarm_skip_prologue (CORE_ADDR pc) 367130812Smarcel{ 368130812Smarcel unsigned long inst; 369130812Smarcel CORE_ADDR skip_pc; 370130812Smarcel CORE_ADDR func_addr, func_end = 0; 371130812Smarcel char *func_name; 372130812Smarcel struct symtab_and_line sal; 373130812Smarcel 374130812Smarcel /* If we're in a dummy frame, don't even try to skip the prologue. */ 375130812Smarcel if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) 376130812Smarcel return pc; 377130812Smarcel 378130812Smarcel /* See what the symbol table says. */ 379130812Smarcel 380130812Smarcel if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) 381130812Smarcel { 382130812Smarcel struct symbol *sym; 383130812Smarcel 384130812Smarcel /* Found a function. */ 385130812Smarcel sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); 386130812Smarcel if (sym && SYMBOL_LANGUAGE (sym) != language_asm) 387130812Smarcel { 388130812Smarcel /* Don't use this trick for assembly source files. */ 389130812Smarcel sal = find_pc_line (func_addr, 0); 390130812Smarcel if ((sal.line != 0) && (sal.end < func_end)) 391130812Smarcel return sal.end; 392130812Smarcel } 393130812Smarcel } 394130812Smarcel 395130812Smarcel /* Check if this is Thumb code. */ 396130812Smarcel if (arm_pc_is_thumb (pc)) 397130812Smarcel return thumb_skip_prologue (pc, func_end); 398130812Smarcel 399130812Smarcel /* Can't find the prologue end in the symbol table, try it the hard way 400130812Smarcel by disassembling the instructions. */ 401130812Smarcel 402130812Smarcel /* Like arm_scan_prologue, stop no later than pc + 64. */ 403130812Smarcel if (func_end == 0 || func_end > pc + 64) 404130812Smarcel func_end = pc + 64; 405130812Smarcel 406130812Smarcel for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) 407130812Smarcel { 408130812Smarcel inst = read_memory_integer (skip_pc, 4); 409130812Smarcel 410130812Smarcel /* "mov ip, sp" is no longer a required part of the prologue. */ 411130812Smarcel if (inst == 0xe1a0c00d) /* mov ip, sp */ 412130812Smarcel continue; 413130812Smarcel 414130812Smarcel if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ 415130812Smarcel continue; 416130812Smarcel 417130812Smarcel if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ 418130812Smarcel continue; 419130812Smarcel 420130812Smarcel /* Some prologues begin with "str lr, [sp, #-4]!". */ 421130812Smarcel if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ 422130812Smarcel continue; 423130812Smarcel 424130812Smarcel if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ 425130812Smarcel continue; 426130812Smarcel 427130812Smarcel if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ 428130812Smarcel continue; 429130812Smarcel 430130812Smarcel /* Any insns after this point may float into the code, if it makes 431130812Smarcel for better instruction scheduling, so we skip them only if we 432130812Smarcel find them, but still consider the function to be frame-ful. */ 433130812Smarcel 434130812Smarcel /* We may have either one sfmfd instruction here, or several stfe 435130812Smarcel insns, depending on the version of floating point code we 436130812Smarcel support. */ 437130812Smarcel if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ 438130812Smarcel continue; 439130812Smarcel 440130812Smarcel if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ 441130812Smarcel continue; 442130812Smarcel 443130812Smarcel if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ 444130812Smarcel continue; 445130812Smarcel 446130812Smarcel if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ 447130812Smarcel continue; 448130812Smarcel 449130812Smarcel if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ 450130812Smarcel (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ 451130812Smarcel (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ 452130812Smarcel continue; 453130812Smarcel 454130812Smarcel if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ 455130812Smarcel (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ 456130812Smarcel (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ 457130812Smarcel continue; 458130812Smarcel 459130812Smarcel /* Un-recognized instruction; stop scanning. */ 460130812Smarcel break; 461130812Smarcel } 462130812Smarcel 463130812Smarcel return skip_pc; /* End of prologue */ 464130812Smarcel} 465130812Smarcel 466130812Smarcel/* *INDENT-OFF* */ 467130812Smarcel/* Function: thumb_scan_prologue (helper function for arm_scan_prologue) 468130812Smarcel This function decodes a Thumb function prologue to determine: 469130812Smarcel 1) the size of the stack frame 470130812Smarcel 2) which registers are saved on it 471130812Smarcel 3) the offsets of saved regs 472130812Smarcel 4) the offset from the stack pointer to the frame pointer 473130812Smarcel 474130812Smarcel A typical Thumb function prologue would create this stack frame 475130812Smarcel (offsets relative to FP) 476130812Smarcel old SP -> 24 stack parameters 477130812Smarcel 20 LR 478130812Smarcel 16 R7 479130812Smarcel R7 -> 0 local variables (16 bytes) 480130812Smarcel SP -> -12 additional stack space (12 bytes) 481130812Smarcel The frame size would thus be 36 bytes, and the frame offset would be 482130812Smarcel 12 bytes. The frame register is R7. 483130812Smarcel 484130812Smarcel The comments for thumb_skip_prolog() describe the algorithm we use 485130812Smarcel to detect the end of the prolog. */ 486130812Smarcel/* *INDENT-ON* */ 487130812Smarcel 488130812Smarcelstatic void 489130812Smarcelthumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) 490130812Smarcel{ 491130812Smarcel CORE_ADDR prologue_start; 492130812Smarcel CORE_ADDR prologue_end; 493130812Smarcel CORE_ADDR current_pc; 494130812Smarcel /* Which register has been copied to register n? */ 495130812Smarcel int saved_reg[16]; 496130812Smarcel /* findmask: 497130812Smarcel bit 0 - push { rlist } 498130812Smarcel bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) 499130812Smarcel bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) 500130812Smarcel */ 501130812Smarcel int findmask = 0; 502130812Smarcel int i; 503130812Smarcel 504130812Smarcel if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) 505130812Smarcel { 506130812Smarcel struct symtab_and_line sal = find_pc_line (prologue_start, 0); 507130812Smarcel 508130812Smarcel if (sal.line == 0) /* no line info, use current PC */ 509130812Smarcel prologue_end = prev_pc; 510130812Smarcel else if (sal.end < prologue_end) /* next line begins after fn end */ 511130812Smarcel prologue_end = sal.end; /* (probably means no prologue) */ 512130812Smarcel } 513130812Smarcel else 514130812Smarcel /* We're in the boondocks: allow for 515130812Smarcel 16 pushes, an add, and "mv fp,sp". */ 516130812Smarcel prologue_end = prologue_start + 40; 517130812Smarcel 518130812Smarcel prologue_end = min (prologue_end, prev_pc); 519130812Smarcel 520130812Smarcel /* Initialize the saved register map. When register H is copied to 521130812Smarcel register L, we will put H in saved_reg[L]. */ 522130812Smarcel for (i = 0; i < 16; i++) 523130812Smarcel saved_reg[i] = i; 524130812Smarcel 525130812Smarcel /* Search the prologue looking for instructions that set up the 526130812Smarcel frame pointer, adjust the stack pointer, and save registers. 527130812Smarcel Do this until all basic prolog instructions are found. */ 528130812Smarcel 529130812Smarcel cache->framesize = 0; 530130812Smarcel for (current_pc = prologue_start; 531130812Smarcel (current_pc < prologue_end) && ((findmask & 7) != 7); 532130812Smarcel current_pc += 2) 533130812Smarcel { 534130812Smarcel unsigned short insn; 535130812Smarcel int regno; 536130812Smarcel int offset; 537130812Smarcel 538130812Smarcel insn = read_memory_unsigned_integer (current_pc, 2); 539130812Smarcel 540130812Smarcel if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ 541130812Smarcel { 542130812Smarcel int mask; 543130812Smarcel findmask |= 1; /* push found */ 544130812Smarcel /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says 545130812Smarcel whether to save LR (R14). */ 546130812Smarcel mask = (insn & 0xff) | ((insn & 0x100) << 6); 547130812Smarcel 548130812Smarcel /* Calculate offsets of saved R0-R7 and LR. */ 549130812Smarcel for (regno = ARM_LR_REGNUM; regno >= 0; regno--) 550130812Smarcel if (mask & (1 << regno)) 551130812Smarcel { 552130812Smarcel cache->framesize += 4; 553130812Smarcel cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; 554130812Smarcel /* Reset saved register map. */ 555130812Smarcel saved_reg[regno] = regno; 556130812Smarcel } 557130812Smarcel } 558130812Smarcel else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR 559130812Smarcel sub sp, #simm */ 560130812Smarcel { 561130812Smarcel if ((findmask & 1) == 0) /* before push? */ 562130812Smarcel continue; 563130812Smarcel else 564130812Smarcel findmask |= 4; /* add/sub sp found */ 565130812Smarcel 566130812Smarcel offset = (insn & 0x7f) << 2; /* get scaled offset */ 567130812Smarcel if (insn & 0x80) /* is it signed? (==subtracting) */ 568130812Smarcel { 569130812Smarcel cache->frameoffset += offset; 570130812Smarcel offset = -offset; 571130812Smarcel } 572130812Smarcel cache->framesize -= offset; 573130812Smarcel } 574130812Smarcel else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ 575130812Smarcel { 576130812Smarcel findmask |= 2; /* setting of r7 found */ 577130812Smarcel cache->framereg = THUMB_FP_REGNUM; 578130812Smarcel /* get scaled offset */ 579130812Smarcel cache->frameoffset = (insn & 0xff) << 2; 580130812Smarcel } 581130812Smarcel else if (insn == 0x466f) /* mov r7, sp */ 582130812Smarcel { 583130812Smarcel findmask |= 2; /* setting of r7 found */ 584130812Smarcel cache->framereg = THUMB_FP_REGNUM; 585130812Smarcel cache->frameoffset = 0; 586130812Smarcel saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; 587130812Smarcel } 588130812Smarcel else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ 589130812Smarcel { 590130812Smarcel int lo_reg = insn & 7; /* dest. register (r0-r7) */ 591130812Smarcel int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ 592130812Smarcel saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ 593130812Smarcel } 594130812Smarcel else 595130812Smarcel /* Something in the prolog that we don't care about or some 596130812Smarcel instruction from outside the prolog scheduled here for 597130812Smarcel optimization. */ 598130812Smarcel continue; 599130812Smarcel } 600130812Smarcel} 601130812Smarcel 602130812Smarcel/* This function decodes an ARM function prologue to determine: 603130812Smarcel 1) the size of the stack frame 604130812Smarcel 2) which registers are saved on it 605130812Smarcel 3) the offsets of saved regs 606130812Smarcel 4) the offset from the stack pointer to the frame pointer 607130812Smarcel This information is stored in the "extra" fields of the frame_info. 608130812Smarcel 609130812Smarcel There are two basic forms for the ARM prologue. The fixed argument 610130812Smarcel function call will look like: 611130812Smarcel 612130812Smarcel mov ip, sp 613130812Smarcel stmfd sp!, {fp, ip, lr, pc} 614130812Smarcel sub fp, ip, #4 615130812Smarcel [sub sp, sp, #4] 616130812Smarcel 617130812Smarcel Which would create this stack frame (offsets relative to FP): 618130812Smarcel IP -> 4 (caller's stack) 619130812Smarcel FP -> 0 PC (points to address of stmfd instruction + 8 in callee) 620130812Smarcel -4 LR (return address in caller) 621130812Smarcel -8 IP (copy of caller's SP) 622130812Smarcel -12 FP (caller's FP) 623130812Smarcel SP -> -28 Local variables 624130812Smarcel 625130812Smarcel The frame size would thus be 32 bytes, and the frame offset would be 626130812Smarcel 28 bytes. The stmfd call can also save any of the vN registers it 627130812Smarcel plans to use, which increases the frame size accordingly. 628130812Smarcel 629130812Smarcel Note: The stored PC is 8 off of the STMFD instruction that stored it 630130812Smarcel because the ARM Store instructions always store PC + 8 when you read 631130812Smarcel the PC register. 632130812Smarcel 633130812Smarcel A variable argument function call will look like: 634130812Smarcel 635130812Smarcel mov ip, sp 636130812Smarcel stmfd sp!, {a1, a2, a3, a4} 637130812Smarcel stmfd sp!, {fp, ip, lr, pc} 638130812Smarcel sub fp, ip, #20 639130812Smarcel 640130812Smarcel Which would create this stack frame (offsets relative to FP): 641130812Smarcel IP -> 20 (caller's stack) 642130812Smarcel 16 A4 643130812Smarcel 12 A3 644130812Smarcel 8 A2 645130812Smarcel 4 A1 646130812Smarcel FP -> 0 PC (points to address of stmfd instruction + 8 in callee) 647130812Smarcel -4 LR (return address in caller) 648130812Smarcel -8 IP (copy of caller's SP) 649130812Smarcel -12 FP (caller's FP) 650130812Smarcel SP -> -28 Local variables 651130812Smarcel 652130812Smarcel The frame size would thus be 48 bytes, and the frame offset would be 653130812Smarcel 28 bytes. 654130812Smarcel 655130812Smarcel There is another potential complication, which is that the optimizer 656130812Smarcel will try to separate the store of fp in the "stmfd" instruction from 657130812Smarcel the "sub fp, ip, #NN" instruction. Almost anything can be there, so 658130812Smarcel we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... 659130812Smarcel 660130812Smarcel Also, note, the original version of the ARM toolchain claimed that there 661130812Smarcel should be an 662130812Smarcel 663130812Smarcel instruction at the end of the prologue. I have never seen GCC produce 664130812Smarcel this, and the ARM docs don't mention it. We still test for it below in 665130812Smarcel case it happens... 666130812Smarcel 667130812Smarcel */ 668130812Smarcel 669130812Smarcelstatic void 670130812Smarcelarm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) 671130812Smarcel{ 672130812Smarcel int regno, sp_offset, fp_offset, ip_offset; 673130812Smarcel CORE_ADDR prologue_start, prologue_end, current_pc; 674130812Smarcel CORE_ADDR prev_pc = frame_pc_unwind (next_frame); 675130812Smarcel 676130812Smarcel /* Assume there is no frame until proven otherwise. */ 677130812Smarcel cache->framereg = ARM_SP_REGNUM; 678130812Smarcel cache->framesize = 0; 679130812Smarcel cache->frameoffset = 0; 680130812Smarcel 681130812Smarcel /* Check for Thumb prologue. */ 682130812Smarcel if (arm_pc_is_thumb (prev_pc)) 683130812Smarcel { 684130812Smarcel thumb_scan_prologue (prev_pc, cache); 685130812Smarcel return; 686130812Smarcel } 687130812Smarcel 688130812Smarcel /* Find the function prologue. If we can't find the function in 689130812Smarcel the symbol table, peek in the stack frame to find the PC. */ 690130812Smarcel if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) 691130812Smarcel { 692130812Smarcel /* One way to find the end of the prologue (which works well 693130812Smarcel for unoptimized code) is to do the following: 694130812Smarcel 695130812Smarcel struct symtab_and_line sal = find_pc_line (prologue_start, 0); 696130812Smarcel 697130812Smarcel if (sal.line == 0) 698130812Smarcel prologue_end = prev_pc; 699130812Smarcel else if (sal.end < prologue_end) 700130812Smarcel prologue_end = sal.end; 701130812Smarcel 702130812Smarcel This mechanism is very accurate so long as the optimizer 703130812Smarcel doesn't move any instructions from the function body into the 704130812Smarcel prologue. If this happens, sal.end will be the last 705130812Smarcel instruction in the first hunk of prologue code just before 706130812Smarcel the first instruction that the scheduler has moved from 707130812Smarcel the body to the prologue. 708130812Smarcel 709130812Smarcel In order to make sure that we scan all of the prologue 710130812Smarcel instructions, we use a slightly less accurate mechanism which 711130812Smarcel may scan more than necessary. To help compensate for this 712130812Smarcel lack of accuracy, the prologue scanning loop below contains 713130812Smarcel several clauses which'll cause the loop to terminate early if 714130812Smarcel an implausible prologue instruction is encountered. 715130812Smarcel 716130812Smarcel The expression 717130812Smarcel 718130812Smarcel prologue_start + 64 719130812Smarcel 720130812Smarcel is a suitable endpoint since it accounts for the largest 721130812Smarcel possible prologue plus up to five instructions inserted by 722130812Smarcel the scheduler. */ 723130812Smarcel 724130812Smarcel if (prologue_end > prologue_start + 64) 725130812Smarcel { 726130812Smarcel prologue_end = prologue_start + 64; /* See above. */ 727130812Smarcel } 728130812Smarcel } 729130812Smarcel else 730130812Smarcel { 731130812Smarcel /* We have no symbol information. Our only option is to assume this 732130812Smarcel function has a standard stack frame and the normal frame register. 733130812Smarcel Then, we can find the value of our frame pointer on entrance to 734130812Smarcel the callee (or at the present moment if this is the innermost frame). 735130812Smarcel The value stored there should be the address of the stmfd + 8. */ 736130812Smarcel CORE_ADDR frame_loc; 737130812Smarcel LONGEST return_value; 738130812Smarcel 739130812Smarcel frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); 740130812Smarcel if (!safe_read_memory_integer (frame_loc, 4, &return_value)) 741130812Smarcel return; 742130812Smarcel else 743130812Smarcel { 744130812Smarcel prologue_start = ADDR_BITS_REMOVE (return_value) - 8; 745130812Smarcel prologue_end = prologue_start + 64; /* See above. */ 746130812Smarcel } 747130812Smarcel } 748130812Smarcel 749130812Smarcel if (prev_pc < prologue_end) 750130812Smarcel prologue_end = prev_pc; 751130812Smarcel 752130812Smarcel /* Now search the prologue looking for instructions that set up the 753130812Smarcel frame pointer, adjust the stack pointer, and save registers. 754130812Smarcel 755130812Smarcel Be careful, however, and if it doesn't look like a prologue, 756130812Smarcel don't try to scan it. If, for instance, a frameless function 757130812Smarcel begins with stmfd sp!, then we will tell ourselves there is 758130812Smarcel a frame, which will confuse stack traceback, as well as "finish" 759130812Smarcel and other operations that rely on a knowledge of the stack 760130812Smarcel traceback. 761130812Smarcel 762130812Smarcel In the APCS, the prologue should start with "mov ip, sp" so 763130812Smarcel if we don't see this as the first insn, we will stop. 764130812Smarcel 765130812Smarcel [Note: This doesn't seem to be true any longer, so it's now an 766130812Smarcel optional part of the prologue. - Kevin Buettner, 2001-11-20] 767130812Smarcel 768130812Smarcel [Note further: The "mov ip,sp" only seems to be missing in 769130812Smarcel frameless functions at optimization level "-O2" or above, 770130812Smarcel in which case it is often (but not always) replaced by 771130812Smarcel "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ 772130812Smarcel 773130812Smarcel sp_offset = fp_offset = ip_offset = 0; 774130812Smarcel 775130812Smarcel for (current_pc = prologue_start; 776130812Smarcel current_pc < prologue_end; 777130812Smarcel current_pc += 4) 778130812Smarcel { 779130812Smarcel unsigned int insn = read_memory_unsigned_integer (current_pc, 4); 780130812Smarcel 781130812Smarcel if (insn == 0xe1a0c00d) /* mov ip, sp */ 782130812Smarcel { 783130812Smarcel ip_offset = 0; 784130812Smarcel continue; 785130812Smarcel } 786130812Smarcel else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ 787130812Smarcel { 788130812Smarcel unsigned imm = insn & 0xff; /* immediate value */ 789130812Smarcel unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ 790130812Smarcel imm = (imm >> rot) | (imm << (32 - rot)); 791130812Smarcel ip_offset = imm; 792130812Smarcel continue; 793130812Smarcel } 794130812Smarcel else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ 795130812Smarcel { 796130812Smarcel unsigned imm = insn & 0xff; /* immediate value */ 797130812Smarcel unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ 798130812Smarcel imm = (imm >> rot) | (imm << (32 - rot)); 799130812Smarcel ip_offset = -imm; 800130812Smarcel continue; 801130812Smarcel } 802130812Smarcel else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ 803130812Smarcel { 804130812Smarcel sp_offset -= 4; 805130812Smarcel cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; 806130812Smarcel continue; 807130812Smarcel } 808130812Smarcel else if ((insn & 0xffff0000) == 0xe92d0000) 809130812Smarcel /* stmfd sp!, {..., fp, ip, lr, pc} 810130812Smarcel or 811130812Smarcel stmfd sp!, {a1, a2, a3, a4} */ 812130812Smarcel { 813130812Smarcel int mask = insn & 0xffff; 814130812Smarcel 815130812Smarcel /* Calculate offsets of saved registers. */ 816130812Smarcel for (regno = ARM_PC_REGNUM; regno >= 0; regno--) 817130812Smarcel if (mask & (1 << regno)) 818130812Smarcel { 819130812Smarcel sp_offset -= 4; 820130812Smarcel cache->saved_regs[regno].addr = sp_offset; 821130812Smarcel } 822130812Smarcel } 823130812Smarcel else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ 824130812Smarcel (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ 825130812Smarcel (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ 826130812Smarcel { 827130812Smarcel /* No need to add this to saved_regs -- it's just an arg reg. */ 828130812Smarcel continue; 829130812Smarcel } 830130812Smarcel else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ 831130812Smarcel (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ 832130812Smarcel (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ 833130812Smarcel { 834130812Smarcel /* No need to add this to saved_regs -- it's just an arg reg. */ 835130812Smarcel continue; 836130812Smarcel } 837130812Smarcel else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ 838130812Smarcel { 839130812Smarcel unsigned imm = insn & 0xff; /* immediate value */ 840130812Smarcel unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ 841130812Smarcel imm = (imm >> rot) | (imm << (32 - rot)); 842130812Smarcel fp_offset = -imm + ip_offset; 843130812Smarcel cache->framereg = ARM_FP_REGNUM; 844130812Smarcel } 845130812Smarcel else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ 846130812Smarcel { 847130812Smarcel unsigned imm = insn & 0xff; /* immediate value */ 848130812Smarcel unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ 849130812Smarcel imm = (imm >> rot) | (imm << (32 - rot)); 850130812Smarcel sp_offset -= imm; 851130812Smarcel } 852130812Smarcel else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ 853130812Smarcel { 854130812Smarcel sp_offset -= 12; 855130812Smarcel regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); 856130812Smarcel cache->saved_regs[regno].addr = sp_offset; 857130812Smarcel } 858130812Smarcel else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ 859130812Smarcel { 860130812Smarcel int n_saved_fp_regs; 861130812Smarcel unsigned int fp_start_reg, fp_bound_reg; 862130812Smarcel 863130812Smarcel if ((insn & 0x800) == 0x800) /* N0 is set */ 864130812Smarcel { 865130812Smarcel if ((insn & 0x40000) == 0x40000) /* N1 is set */ 866130812Smarcel n_saved_fp_regs = 3; 867130812Smarcel else 868130812Smarcel n_saved_fp_regs = 1; 869130812Smarcel } 870130812Smarcel else 871130812Smarcel { 872130812Smarcel if ((insn & 0x40000) == 0x40000) /* N1 is set */ 873130812Smarcel n_saved_fp_regs = 2; 874130812Smarcel else 875130812Smarcel n_saved_fp_regs = 4; 876130812Smarcel } 877130812Smarcel 878130812Smarcel fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); 879130812Smarcel fp_bound_reg = fp_start_reg + n_saved_fp_regs; 880130812Smarcel for (; fp_start_reg < fp_bound_reg; fp_start_reg++) 881130812Smarcel { 882130812Smarcel sp_offset -= 12; 883130812Smarcel cache->saved_regs[fp_start_reg++].addr = sp_offset; 884130812Smarcel } 885130812Smarcel } 886130812Smarcel else if ((insn & 0xf0000000) != 0xe0000000) 887130812Smarcel break; /* Condition not true, exit early */ 888130812Smarcel else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ 889130812Smarcel break; /* Don't scan past a block load */ 890130812Smarcel else 891130812Smarcel /* The optimizer might shove anything into the prologue, 892130812Smarcel so we just skip what we don't recognize. */ 893130812Smarcel continue; 894130812Smarcel } 895130812Smarcel 896130812Smarcel /* The frame size is just the negative of the offset (from the 897130812Smarcel original SP) of the last thing thing we pushed on the stack. 898130812Smarcel The frame offset is [new FP] - [new SP]. */ 899130812Smarcel cache->framesize = -sp_offset; 900130812Smarcel if (cache->framereg == ARM_FP_REGNUM) 901130812Smarcel cache->frameoffset = fp_offset - sp_offset; 902130812Smarcel else 903130812Smarcel cache->frameoffset = 0; 904130812Smarcel} 905130812Smarcel 906130812Smarcelstatic struct arm_prologue_cache * 907130812Smarcelarm_make_prologue_cache (struct frame_info *next_frame) 908130812Smarcel{ 909130812Smarcel int reg; 910130812Smarcel struct arm_prologue_cache *cache; 911130812Smarcel CORE_ADDR unwound_fp; 912130812Smarcel 913130812Smarcel cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); 914130812Smarcel cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); 915130812Smarcel 916130812Smarcel arm_scan_prologue (next_frame, cache); 917130812Smarcel 918130812Smarcel unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); 919130812Smarcel if (unwound_fp == 0) 920130812Smarcel return cache; 921130812Smarcel 922130812Smarcel cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; 923130812Smarcel 924130812Smarcel /* Calculate actual addresses of saved registers using offsets 925130812Smarcel determined by arm_scan_prologue. */ 926130812Smarcel for (reg = 0; reg < NUM_REGS; reg++) 927130812Smarcel if (trad_frame_addr_p (cache->saved_regs, reg)) 928130812Smarcel cache->saved_regs[reg].addr += cache->prev_sp; 929130812Smarcel 930130812Smarcel return cache; 931130812Smarcel} 932130812Smarcel 933130812Smarcel/* Our frame ID for a normal frame is the current function's starting PC 934130812Smarcel and the caller's SP when we were called. */ 935130812Smarcel 936130812Smarcelstatic void 937130812Smarcelarm_prologue_this_id (struct frame_info *next_frame, 938130812Smarcel void **this_cache, 939130812Smarcel struct frame_id *this_id) 940130812Smarcel{ 941130812Smarcel struct arm_prologue_cache *cache; 942130812Smarcel struct frame_id id; 943130812Smarcel CORE_ADDR func; 944130812Smarcel 945130812Smarcel if (*this_cache == NULL) 946130812Smarcel *this_cache = arm_make_prologue_cache (next_frame); 947130812Smarcel cache = *this_cache; 948130812Smarcel 949130812Smarcel func = frame_func_unwind (next_frame); 950130812Smarcel 951130812Smarcel /* This is meant to halt the backtrace at "_start". Make sure we 952130812Smarcel don't halt it at a generic dummy frame. */ 953130812Smarcel if (func <= LOWEST_PC) 954130812Smarcel return; 955130812Smarcel 956130812Smarcel /* If we've hit a wall, stop. */ 957130812Smarcel if (cache->prev_sp == 0) 958130812Smarcel return; 959130812Smarcel 960130812Smarcel id = frame_id_build (cache->prev_sp, func); 961130812Smarcel 962130812Smarcel /* Check that we're not going round in circles with the same frame 963130812Smarcel ID (but avoid applying the test to sentinel frames which do go 964130812Smarcel round in circles). */ 965130812Smarcel if (frame_relative_level (next_frame) >= 0 966130812Smarcel && get_frame_type (next_frame) == NORMAL_FRAME 967130812Smarcel && frame_id_eq (get_frame_id (next_frame), id)) 968130812Smarcel return; 969130812Smarcel 970130812Smarcel *this_id = id; 971130812Smarcel} 972130812Smarcel 973130812Smarcelstatic void 974130812Smarcelarm_prologue_prev_register (struct frame_info *next_frame, 975130812Smarcel void **this_cache, 976130812Smarcel int prev_regnum, 977130812Smarcel int *optimized, 978130812Smarcel enum lval_type *lvalp, 979130812Smarcel CORE_ADDR *addrp, 980130812Smarcel int *realnump, 981130812Smarcel void *valuep) 982130812Smarcel{ 983130812Smarcel struct arm_prologue_cache *cache; 984130812Smarcel 985130812Smarcel if (*this_cache == NULL) 986130812Smarcel *this_cache = arm_make_prologue_cache (next_frame); 987130812Smarcel cache = *this_cache; 988130812Smarcel 989130812Smarcel /* If we are asked to unwind the PC, then we need to return the LR 990130812Smarcel instead. The saved value of PC points into this frame's 991130812Smarcel prologue, not the next frame's resume location. */ 992130812Smarcel if (prev_regnum == ARM_PC_REGNUM) 993130812Smarcel prev_regnum = ARM_LR_REGNUM; 994130812Smarcel 995130812Smarcel /* SP is generally not saved to the stack, but this frame is 996130812Smarcel identified by NEXT_FRAME's stack pointer at the time of the call. 997130812Smarcel The value was already reconstructed into PREV_SP. */ 998130812Smarcel if (prev_regnum == ARM_SP_REGNUM) 999130812Smarcel { 1000130812Smarcel *lvalp = not_lval; 1001130812Smarcel if (valuep) 1002130812Smarcel store_unsigned_integer (valuep, 4, cache->prev_sp); 1003130812Smarcel return; 1004130812Smarcel } 1005130812Smarcel 1006130812Smarcel trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, 1007130812Smarcel optimized, lvalp, addrp, realnump, valuep); 1008130812Smarcel} 1009130812Smarcel 1010130812Smarcelstruct frame_unwind arm_prologue_unwind = { 1011130812Smarcel NORMAL_FRAME, 1012130812Smarcel arm_prologue_this_id, 1013130812Smarcel arm_prologue_prev_register 1014130812Smarcel}; 1015130812Smarcel 1016130812Smarcelstatic const struct frame_unwind * 1017130812Smarcelarm_prologue_unwind_sniffer (struct frame_info *next_frame) 1018130812Smarcel{ 1019130812Smarcel return &arm_prologue_unwind; 1020130812Smarcel} 1021130812Smarcel 1022130812Smarcelstatic CORE_ADDR 1023130812Smarcelarm_normal_frame_base (struct frame_info *next_frame, void **this_cache) 1024130812Smarcel{ 1025130812Smarcel struct arm_prologue_cache *cache; 1026130812Smarcel 1027130812Smarcel if (*this_cache == NULL) 1028130812Smarcel *this_cache = arm_make_prologue_cache (next_frame); 1029130812Smarcel cache = *this_cache; 1030130812Smarcel 1031130812Smarcel return cache->prev_sp + cache->frameoffset - cache->framesize; 1032130812Smarcel} 1033130812Smarcel 1034130812Smarcelstruct frame_base arm_normal_base = { 1035130812Smarcel &arm_prologue_unwind, 1036130812Smarcel arm_normal_frame_base, 1037130812Smarcel arm_normal_frame_base, 1038130812Smarcel arm_normal_frame_base 1039130812Smarcel}; 1040130812Smarcel 1041130812Smarcelstatic struct arm_prologue_cache * 1042130812Smarcelarm_make_sigtramp_cache (struct frame_info *next_frame) 1043130812Smarcel{ 1044130812Smarcel struct arm_prologue_cache *cache; 1045130812Smarcel int reg; 1046130812Smarcel 1047130812Smarcel cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); 1048130812Smarcel 1049130812Smarcel cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); 1050130812Smarcel 1051130812Smarcel cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); 1052130812Smarcel 1053130812Smarcel for (reg = 0; reg < NUM_REGS; reg++) 1054130812Smarcel cache->saved_regs[reg].addr 1055130812Smarcel = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, 1056130812Smarcel frame_pc_unwind (next_frame), reg); 1057130812Smarcel 1058130812Smarcel /* FIXME: What about thumb mode? */ 1059130812Smarcel cache->framereg = ARM_SP_REGNUM; 1060130812Smarcel cache->prev_sp 1061130812Smarcel = read_memory_integer (cache->saved_regs[cache->framereg].addr, 1062130812Smarcel register_size (current_gdbarch, cache->framereg)); 1063130812Smarcel 1064130812Smarcel return cache; 1065130812Smarcel} 1066130812Smarcel 1067130812Smarcelstatic void 1068130812Smarcelarm_sigtramp_this_id (struct frame_info *next_frame, 1069130812Smarcel void **this_cache, 1070130812Smarcel struct frame_id *this_id) 1071130812Smarcel{ 1072130812Smarcel struct arm_prologue_cache *cache; 1073130812Smarcel 1074130812Smarcel if (*this_cache == NULL) 1075130812Smarcel *this_cache = arm_make_sigtramp_cache (next_frame); 1076130812Smarcel cache = *this_cache; 1077130812Smarcel 1078130812Smarcel /* FIXME drow/2003-07-07: This isn't right if we single-step within 1079130812Smarcel the sigtramp frame; the PC should be the beginning of the trampoline. */ 1080130812Smarcel *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); 1081130812Smarcel} 1082130812Smarcel 1083130812Smarcelstatic void 1084130812Smarcelarm_sigtramp_prev_register (struct frame_info *next_frame, 1085130812Smarcel void **this_cache, 1086130812Smarcel int prev_regnum, 1087130812Smarcel int *optimized, 1088130812Smarcel enum lval_type *lvalp, 1089130812Smarcel CORE_ADDR *addrp, 1090130812Smarcel int *realnump, 1091130812Smarcel void *valuep) 1092130812Smarcel{ 1093130812Smarcel struct arm_prologue_cache *cache; 1094130812Smarcel 1095130812Smarcel if (*this_cache == NULL) 1096130812Smarcel *this_cache = arm_make_sigtramp_cache (next_frame); 1097130812Smarcel cache = *this_cache; 1098130812Smarcel 1099130812Smarcel trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, 1100130812Smarcel optimized, lvalp, addrp, realnump, valuep); 1101130812Smarcel} 1102130812Smarcel 1103130812Smarcelstruct frame_unwind arm_sigtramp_unwind = { 1104130812Smarcel SIGTRAMP_FRAME, 1105130812Smarcel arm_sigtramp_this_id, 1106130812Smarcel arm_sigtramp_prev_register 1107130812Smarcel}; 1108130812Smarcel 1109130812Smarcelstatic const struct frame_unwind * 1110130812Smarcelarm_sigtramp_unwind_sniffer (struct frame_info *next_frame) 1111130812Smarcel{ 1112130812Smarcel /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare 1113130812Smarcel against the name of the function, the code below will have to be 1114130812Smarcel changed to first fetch the name of the function and then pass 1115130812Smarcel this name to PC_IN_SIGTRAMP. */ 1116130812Smarcel 1117130812Smarcel if (SIGCONTEXT_REGISTER_ADDRESS_P () 1118130812Smarcel && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame), (char *) 0)) 1119130812Smarcel return &arm_sigtramp_unwind; 1120130812Smarcel 1121130812Smarcel return NULL; 1122130812Smarcel} 1123130812Smarcel 1124130812Smarcel/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 1125130812Smarcel dummy frame. The frame ID's base needs to match the TOS value 1126130812Smarcel saved by save_dummy_frame_tos() and returned from 1127130812Smarcel arm_push_dummy_call, and the PC needs to match the dummy frame's 1128130812Smarcel breakpoint. */ 1129130812Smarcel 1130130812Smarcelstatic struct frame_id 1131130812Smarcelarm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1132130812Smarcel{ 1133130812Smarcel return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), 1134130812Smarcel frame_pc_unwind (next_frame)); 1135130812Smarcel} 1136130812Smarcel 1137130812Smarcel/* Given THIS_FRAME, find the previous frame's resume PC (which will 1138130812Smarcel be used to construct the previous frame's ID, after looking up the 1139130812Smarcel containing function). */ 1140130812Smarcel 1141130812Smarcelstatic CORE_ADDR 1142130812Smarcelarm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) 1143130812Smarcel{ 1144130812Smarcel CORE_ADDR pc; 1145130812Smarcel pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); 1146130812Smarcel return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; 1147130812Smarcel} 1148130812Smarcel 1149130812Smarcelstatic CORE_ADDR 1150130812Smarcelarm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) 1151130812Smarcel{ 1152130812Smarcel return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); 1153130812Smarcel} 1154130812Smarcel 1155130812Smarcel/* DEPRECATED_CALL_DUMMY_WORDS: 1156130812Smarcel This sequence of words is the instructions 1157130812Smarcel 1158130812Smarcel mov lr,pc 1159130812Smarcel mov pc,r4 1160130812Smarcel illegal 1161130812Smarcel 1162130812Smarcel Note this is 12 bytes. */ 1163130812Smarcel 1164130812Smarcelstatic LONGEST arm_call_dummy_words[] = 1165130812Smarcel{ 1166130812Smarcel 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe 1167130812Smarcel}; 1168130812Smarcel 1169130812Smarcel/* When arguments must be pushed onto the stack, they go on in reverse 1170130812Smarcel order. The code below implements a FILO (stack) to do this. */ 1171130812Smarcel 1172130812Smarcelstruct stack_item 1173130812Smarcel{ 1174130812Smarcel int len; 1175130812Smarcel struct stack_item *prev; 1176130812Smarcel void *data; 1177130812Smarcel}; 1178130812Smarcel 1179130812Smarcelstatic struct stack_item * 1180130812Smarcelpush_stack_item (struct stack_item *prev, void *contents, int len) 1181130812Smarcel{ 1182130812Smarcel struct stack_item *si; 1183130812Smarcel si = xmalloc (sizeof (struct stack_item)); 1184130812Smarcel si->data = xmalloc (len); 1185130812Smarcel si->len = len; 1186130812Smarcel si->prev = prev; 1187130812Smarcel memcpy (si->data, contents, len); 1188130812Smarcel return si; 1189130812Smarcel} 1190130812Smarcel 1191130812Smarcelstatic struct stack_item * 1192130812Smarcelpop_stack_item (struct stack_item *si) 1193130812Smarcel{ 1194130812Smarcel struct stack_item *dead = si; 1195130812Smarcel si = si->prev; 1196130812Smarcel xfree (dead->data); 1197130812Smarcel xfree (dead); 1198130812Smarcel return si; 1199130812Smarcel} 1200130812Smarcel 1201130812Smarcel/* We currently only support passing parameters in integer registers. This 1202130812Smarcel conforms with GCC's default model. Several other variants exist and 1203130812Smarcel we should probably support some of them based on the selected ABI. */ 1204130812Smarcel 1205130812Smarcelstatic CORE_ADDR 1206130812Smarcelarm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 1207130812Smarcel struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 1208130812Smarcel struct value **args, CORE_ADDR sp, int struct_return, 1209130812Smarcel CORE_ADDR struct_addr) 1210130812Smarcel{ 1211130812Smarcel int argnum; 1212130812Smarcel int argreg; 1213130812Smarcel int nstack; 1214130812Smarcel struct stack_item *si = NULL; 1215130812Smarcel 1216130812Smarcel /* Set the return address. For the ARM, the return breakpoint is 1217130812Smarcel always at BP_ADDR. */ 1218130812Smarcel /* XXX Fix for Thumb. */ 1219130812Smarcel regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); 1220130812Smarcel 1221130812Smarcel /* Walk through the list of args and determine how large a temporary 1222130812Smarcel stack is required. Need to take care here as structs may be 1223130812Smarcel passed on the stack, and we have to to push them. */ 1224130812Smarcel nstack = 0; 1225130812Smarcel 1226130812Smarcel argreg = ARM_A1_REGNUM; 1227130812Smarcel nstack = 0; 1228130812Smarcel 1229130812Smarcel /* Some platforms require a double-word aligned stack. Make sure sp 1230130812Smarcel is correctly aligned before we start. We always do this even if 1231130812Smarcel it isn't really needed -- it can never hurt things. */ 1232130812Smarcel sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); 1233130812Smarcel 1234130812Smarcel /* The struct_return pointer occupies the first parameter 1235130812Smarcel passing register. */ 1236130812Smarcel if (struct_return) 1237130812Smarcel { 1238130812Smarcel if (arm_debug) 1239130812Smarcel fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", 1240130812Smarcel REGISTER_NAME (argreg), paddr (struct_addr)); 1241130812Smarcel regcache_cooked_write_unsigned (regcache, argreg, struct_addr); 1242130812Smarcel argreg++; 1243130812Smarcel } 1244130812Smarcel 1245130812Smarcel for (argnum = 0; argnum < nargs; argnum++) 1246130812Smarcel { 1247130812Smarcel int len; 1248130812Smarcel struct type *arg_type; 1249130812Smarcel struct type *target_type; 1250130812Smarcel enum type_code typecode; 1251130812Smarcel char *val; 1252130812Smarcel 1253130812Smarcel arg_type = check_typedef (VALUE_TYPE (args[argnum])); 1254130812Smarcel len = TYPE_LENGTH (arg_type); 1255130812Smarcel target_type = TYPE_TARGET_TYPE (arg_type); 1256130812Smarcel typecode = TYPE_CODE (arg_type); 1257130812Smarcel val = VALUE_CONTENTS (args[argnum]); 1258130812Smarcel 1259130812Smarcel /* If the argument is a pointer to a function, and it is a 1260130812Smarcel Thumb function, create a LOCAL copy of the value and set 1261130812Smarcel the THUMB bit in it. */ 1262130812Smarcel if (TYPE_CODE_PTR == typecode 1263130812Smarcel && target_type != NULL 1264130812Smarcel && TYPE_CODE_FUNC == TYPE_CODE (target_type)) 1265130812Smarcel { 1266130812Smarcel CORE_ADDR regval = extract_unsigned_integer (val, len); 1267130812Smarcel if (arm_pc_is_thumb (regval)) 1268130812Smarcel { 1269130812Smarcel val = alloca (len); 1270130812Smarcel store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); 1271130812Smarcel } 1272130812Smarcel } 1273130812Smarcel 1274130812Smarcel /* Copy the argument to general registers or the stack in 1275130812Smarcel register-sized pieces. Large arguments are split between 1276130812Smarcel registers and stack. */ 1277130812Smarcel while (len > 0) 1278130812Smarcel { 1279130812Smarcel int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; 1280130812Smarcel 1281130812Smarcel if (argreg <= ARM_LAST_ARG_REGNUM) 1282130812Smarcel { 1283130812Smarcel /* The argument is being passed in a general purpose 1284130812Smarcel register. */ 1285130812Smarcel CORE_ADDR regval = extract_unsigned_integer (val, partial_len); 1286130812Smarcel if (arm_debug) 1287130812Smarcel fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", 1288130812Smarcel argnum, REGISTER_NAME (argreg), 1289130812Smarcel phex (regval, DEPRECATED_REGISTER_SIZE)); 1290130812Smarcel regcache_cooked_write_unsigned (regcache, argreg, regval); 1291130812Smarcel argreg++; 1292130812Smarcel } 1293130812Smarcel else 1294130812Smarcel { 1295130812Smarcel /* Push the arguments onto the stack. */ 1296130812Smarcel if (arm_debug) 1297130812Smarcel fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", 1298130812Smarcel argnum, nstack); 1299130812Smarcel si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); 1300130812Smarcel nstack += DEPRECATED_REGISTER_SIZE; 1301130812Smarcel } 1302130812Smarcel 1303130812Smarcel len -= partial_len; 1304130812Smarcel val += partial_len; 1305130812Smarcel } 1306130812Smarcel } 1307130812Smarcel /* If we have an odd number of words to push, then decrement the stack 1308130812Smarcel by one word now, so first stack argument will be dword aligned. */ 1309130812Smarcel if (nstack & 4) 1310130812Smarcel sp -= 4; 1311130812Smarcel 1312130812Smarcel while (si) 1313130812Smarcel { 1314130812Smarcel sp -= si->len; 1315130812Smarcel write_memory (sp, si->data, si->len); 1316130812Smarcel si = pop_stack_item (si); 1317130812Smarcel } 1318130812Smarcel 1319130812Smarcel /* Finally, update teh SP register. */ 1320130812Smarcel regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); 1321130812Smarcel 1322130812Smarcel return sp; 1323130812Smarcel} 1324130812Smarcel 1325130812Smarcelstatic void 1326130812Smarcelprint_fpu_flags (int flags) 1327130812Smarcel{ 1328130812Smarcel if (flags & (1 << 0)) 1329130812Smarcel fputs ("IVO ", stdout); 1330130812Smarcel if (flags & (1 << 1)) 1331130812Smarcel fputs ("DVZ ", stdout); 1332130812Smarcel if (flags & (1 << 2)) 1333130812Smarcel fputs ("OFL ", stdout); 1334130812Smarcel if (flags & (1 << 3)) 1335130812Smarcel fputs ("UFL ", stdout); 1336130812Smarcel if (flags & (1 << 4)) 1337130812Smarcel fputs ("INX ", stdout); 1338130812Smarcel putchar ('\n'); 1339130812Smarcel} 1340130812Smarcel 1341130812Smarcel/* Print interesting information about the floating point processor 1342130812Smarcel (if present) or emulator. */ 1343130812Smarcelstatic void 1344130812Smarcelarm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, 1345130812Smarcel struct frame_info *frame, const char *args) 1346130812Smarcel{ 1347130812Smarcel unsigned long status = read_register (ARM_FPS_REGNUM); 1348130812Smarcel int type; 1349130812Smarcel 1350130812Smarcel type = (status >> 24) & 127; 1351130812Smarcel printf ("%s FPU type %d\n", 1352130812Smarcel (status & (1 << 31)) ? "Hardware" : "Software", 1353130812Smarcel type); 1354130812Smarcel fputs ("mask: ", stdout); 1355130812Smarcel print_fpu_flags (status >> 16); 1356130812Smarcel fputs ("flags: ", stdout); 1357130812Smarcel print_fpu_flags (status); 1358130812Smarcel} 1359130812Smarcel 1360130812Smarcel/* Return the GDB type object for the "standard" data type of data in 1361130812Smarcel register N. */ 1362130812Smarcel 1363130812Smarcelstatic struct type * 1364130812Smarcelarm_register_type (struct gdbarch *gdbarch, int regnum) 1365130812Smarcel{ 1366130812Smarcel if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) 1367130812Smarcel { 1368130812Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1369130812Smarcel return builtin_type_arm_ext_big; 1370130812Smarcel else 1371130812Smarcel return builtin_type_arm_ext_littlebyte_bigword; 1372130812Smarcel } 1373130812Smarcel else 1374130812Smarcel return builtin_type_int32; 1375130812Smarcel} 1376130812Smarcel 1377130812Smarcel/* Index within `registers' of the first byte of the space for 1378130812Smarcel register N. */ 1379130812Smarcel 1380130812Smarcelstatic int 1381130812Smarcelarm_register_byte (int regnum) 1382130812Smarcel{ 1383130812Smarcel if (regnum < ARM_F0_REGNUM) 1384130812Smarcel return regnum * INT_REGISTER_SIZE; 1385130812Smarcel else if (regnum < ARM_PS_REGNUM) 1386130812Smarcel return (NUM_GREGS * INT_REGISTER_SIZE 1387130812Smarcel + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); 1388130812Smarcel else 1389130812Smarcel return (NUM_GREGS * INT_REGISTER_SIZE 1390130812Smarcel + NUM_FREGS * FP_REGISTER_SIZE 1391130812Smarcel + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); 1392130812Smarcel} 1393130812Smarcel 1394130812Smarcel/* Map GDB internal REGNUM onto the Arm simulator register numbers. */ 1395130812Smarcelstatic int 1396130812Smarcelarm_register_sim_regno (int regnum) 1397130812Smarcel{ 1398130812Smarcel int reg = regnum; 1399130812Smarcel gdb_assert (reg >= 0 && reg < NUM_REGS); 1400130812Smarcel 1401130812Smarcel if (reg < NUM_GREGS) 1402130812Smarcel return SIM_ARM_R0_REGNUM + reg; 1403130812Smarcel reg -= NUM_GREGS; 1404130812Smarcel 1405130812Smarcel if (reg < NUM_FREGS) 1406130812Smarcel return SIM_ARM_FP0_REGNUM + reg; 1407130812Smarcel reg -= NUM_FREGS; 1408130812Smarcel 1409130812Smarcel if (reg < NUM_SREGS) 1410130812Smarcel return SIM_ARM_FPS_REGNUM + reg; 1411130812Smarcel reg -= NUM_SREGS; 1412130812Smarcel 1413130812Smarcel internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); 1414130812Smarcel} 1415130812Smarcel 1416130812Smarcel/* NOTE: cagney/2001-08-20: Both convert_from_extended() and 1417130812Smarcel convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. 1418130812Smarcel It is thought that this is is the floating-point register format on 1419130812Smarcel little-endian systems. */ 1420130812Smarcel 1421130812Smarcelstatic void 1422130812Smarcelconvert_from_extended (const struct floatformat *fmt, const void *ptr, 1423130812Smarcel void *dbl) 1424130812Smarcel{ 1425130812Smarcel DOUBLEST d; 1426130812Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1427130812Smarcel floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); 1428130812Smarcel else 1429130812Smarcel floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, 1430130812Smarcel ptr, &d); 1431130812Smarcel floatformat_from_doublest (fmt, &d, dbl); 1432130812Smarcel} 1433130812Smarcel 1434130812Smarcelstatic void 1435130812Smarcelconvert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) 1436130812Smarcel{ 1437130812Smarcel DOUBLEST d; 1438130812Smarcel floatformat_to_doublest (fmt, ptr, &d); 1439130812Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1440130812Smarcel floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); 1441130812Smarcel else 1442130812Smarcel floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, 1443130812Smarcel &d, dbl); 1444130812Smarcel} 1445130812Smarcel 1446130812Smarcelstatic int 1447130812Smarcelcondition_true (unsigned long cond, unsigned long status_reg) 1448130812Smarcel{ 1449130812Smarcel if (cond == INST_AL || cond == INST_NV) 1450130812Smarcel return 1; 1451130812Smarcel 1452130812Smarcel switch (cond) 1453130812Smarcel { 1454130812Smarcel case INST_EQ: 1455130812Smarcel return ((status_reg & FLAG_Z) != 0); 1456130812Smarcel case INST_NE: 1457130812Smarcel return ((status_reg & FLAG_Z) == 0); 1458130812Smarcel case INST_CS: 1459130812Smarcel return ((status_reg & FLAG_C) != 0); 1460130812Smarcel case INST_CC: 1461130812Smarcel return ((status_reg & FLAG_C) == 0); 1462130812Smarcel case INST_MI: 1463130812Smarcel return ((status_reg & FLAG_N) != 0); 1464130812Smarcel case INST_PL: 1465130812Smarcel return ((status_reg & FLAG_N) == 0); 1466130812Smarcel case INST_VS: 1467130812Smarcel return ((status_reg & FLAG_V) != 0); 1468130812Smarcel case INST_VC: 1469130812Smarcel return ((status_reg & FLAG_V) == 0); 1470130812Smarcel case INST_HI: 1471130812Smarcel return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); 1472130812Smarcel case INST_LS: 1473130812Smarcel return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); 1474130812Smarcel case INST_GE: 1475130812Smarcel return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); 1476130812Smarcel case INST_LT: 1477130812Smarcel return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); 1478130812Smarcel case INST_GT: 1479130812Smarcel return (((status_reg & FLAG_Z) == 0) && 1480130812Smarcel (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); 1481130812Smarcel case INST_LE: 1482130812Smarcel return (((status_reg & FLAG_Z) != 0) || 1483130812Smarcel (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); 1484130812Smarcel } 1485130812Smarcel return 1; 1486130812Smarcel} 1487130812Smarcel 1488130812Smarcel/* Support routines for single stepping. Calculate the next PC value. */ 1489130812Smarcel#define submask(x) ((1L << ((x) + 1)) - 1) 1490130812Smarcel#define bit(obj,st) (((obj) >> (st)) & 1) 1491130812Smarcel#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) 1492130812Smarcel#define sbits(obj,st,fn) \ 1493130812Smarcel ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) 1494130812Smarcel#define BranchDest(addr,instr) \ 1495130812Smarcel ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) 1496130812Smarcel#define ARM_PC_32 1 1497130812Smarcel 1498130812Smarcelstatic unsigned long 1499130812Smarcelshifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, 1500130812Smarcel unsigned long status_reg) 1501130812Smarcel{ 1502130812Smarcel unsigned long res, shift; 1503130812Smarcel int rm = bits (inst, 0, 3); 1504130812Smarcel unsigned long shifttype = bits (inst, 5, 6); 1505130812Smarcel 1506130812Smarcel if (bit (inst, 4)) 1507130812Smarcel { 1508130812Smarcel int rs = bits (inst, 8, 11); 1509130812Smarcel shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; 1510130812Smarcel } 1511130812Smarcel else 1512130812Smarcel shift = bits (inst, 7, 11); 1513130812Smarcel 1514130812Smarcel res = (rm == 15 1515130812Smarcel ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) 1516130812Smarcel + (bit (inst, 4) ? 12 : 8)) 1517130812Smarcel : read_register (rm)); 1518130812Smarcel 1519130812Smarcel switch (shifttype) 1520130812Smarcel { 1521130812Smarcel case 0: /* LSL */ 1522130812Smarcel res = shift >= 32 ? 0 : res << shift; 1523130812Smarcel break; 1524130812Smarcel 1525130812Smarcel case 1: /* LSR */ 1526130812Smarcel res = shift >= 32 ? 0 : res >> shift; 1527130812Smarcel break; 1528130812Smarcel 1529130812Smarcel case 2: /* ASR */ 1530130812Smarcel if (shift >= 32) 1531130812Smarcel shift = 31; 1532130812Smarcel res = ((res & 0x80000000L) 1533130812Smarcel ? ~((~res) >> shift) : res >> shift); 1534130812Smarcel break; 1535130812Smarcel 1536130812Smarcel case 3: /* ROR/RRX */ 1537130812Smarcel shift &= 31; 1538130812Smarcel if (shift == 0) 1539130812Smarcel res = (res >> 1) | (carry ? 0x80000000L : 0); 1540130812Smarcel else 1541130812Smarcel res = (res >> shift) | (res << (32 - shift)); 1542130812Smarcel break; 1543130812Smarcel } 1544130812Smarcel 1545130812Smarcel return res & 0xffffffff; 1546130812Smarcel} 1547130812Smarcel 1548130812Smarcel/* Return number of 1-bits in VAL. */ 1549130812Smarcel 1550130812Smarcelstatic int 1551130812Smarcelbitcount (unsigned long val) 1552130812Smarcel{ 1553130812Smarcel int nbits; 1554130812Smarcel for (nbits = 0; val != 0; nbits++) 1555130812Smarcel val &= val - 1; /* delete rightmost 1-bit in val */ 1556130812Smarcel return nbits; 1557130812Smarcel} 1558130812Smarcel 1559130812SmarcelCORE_ADDR 1560130812Smarcelthumb_get_next_pc (CORE_ADDR pc) 1561130812Smarcel{ 1562130812Smarcel unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ 1563130812Smarcel unsigned short inst1 = read_memory_integer (pc, 2); 1564130812Smarcel CORE_ADDR nextpc = pc + 2; /* default is next instruction */ 1565130812Smarcel unsigned long offset; 1566130812Smarcel 1567130812Smarcel if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ 1568130812Smarcel { 1569130812Smarcel CORE_ADDR sp; 1570130812Smarcel 1571130812Smarcel /* Fetch the saved PC from the stack. It's stored above 1572130812Smarcel all of the other registers. */ 1573130812Smarcel offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; 1574130812Smarcel sp = read_register (ARM_SP_REGNUM); 1575130812Smarcel nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); 1576130812Smarcel nextpc = ADDR_BITS_REMOVE (nextpc); 1577130812Smarcel if (nextpc == pc) 1578130812Smarcel error ("Infinite loop detected"); 1579130812Smarcel } 1580130812Smarcel else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ 1581130812Smarcel { 1582130812Smarcel unsigned long status = read_register (ARM_PS_REGNUM); 1583130812Smarcel unsigned long cond = bits (inst1, 8, 11); 1584130812Smarcel if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ 1585130812Smarcel nextpc = pc_val + (sbits (inst1, 0, 7) << 1); 1586130812Smarcel } 1587130812Smarcel else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ 1588130812Smarcel { 1589130812Smarcel nextpc = pc_val + (sbits (inst1, 0, 10) << 1); 1590130812Smarcel } 1591130812Smarcel else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ 1592130812Smarcel { 1593130812Smarcel unsigned short inst2 = read_memory_integer (pc + 2, 2); 1594130812Smarcel offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); 1595130812Smarcel nextpc = pc_val + offset; 1596130812Smarcel /* For BLX make sure to clear the low bits. */ 1597130812Smarcel if (bits (inst2, 11, 12) == 1) 1598130812Smarcel nextpc = nextpc & 0xfffffffc; 1599130812Smarcel } 1600130812Smarcel else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ 1601130812Smarcel { 1602130812Smarcel if (bits (inst1, 3, 6) == 0x0f) 1603130812Smarcel nextpc = pc_val; 1604130812Smarcel else 1605130812Smarcel nextpc = read_register (bits (inst1, 3, 6)); 1606130812Smarcel 1607130812Smarcel nextpc = ADDR_BITS_REMOVE (nextpc); 1608130812Smarcel if (nextpc == pc) 1609130812Smarcel error ("Infinite loop detected"); 1610130812Smarcel } 1611130812Smarcel 1612130812Smarcel return nextpc; 1613130812Smarcel} 1614130812Smarcel 1615130812SmarcelCORE_ADDR 1616130812Smarcelarm_get_next_pc (CORE_ADDR pc) 1617130812Smarcel{ 1618130812Smarcel unsigned long pc_val; 1619130812Smarcel unsigned long this_instr; 1620130812Smarcel unsigned long status; 1621130812Smarcel CORE_ADDR nextpc; 1622130812Smarcel 1623130812Smarcel if (arm_pc_is_thumb (pc)) 1624130812Smarcel return thumb_get_next_pc (pc); 1625130812Smarcel 1626130812Smarcel pc_val = (unsigned long) pc; 1627130812Smarcel this_instr = read_memory_integer (pc, 4); 1628130812Smarcel status = read_register (ARM_PS_REGNUM); 1629130812Smarcel nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ 1630130812Smarcel 1631130812Smarcel if (condition_true (bits (this_instr, 28, 31), status)) 1632130812Smarcel { 1633130812Smarcel switch (bits (this_instr, 24, 27)) 1634130812Smarcel { 1635130812Smarcel case 0x0: 1636130812Smarcel case 0x1: /* data processing */ 1637130812Smarcel case 0x2: 1638130812Smarcel case 0x3: 1639130812Smarcel { 1640130812Smarcel unsigned long operand1, operand2, result = 0; 1641130812Smarcel unsigned long rn; 1642130812Smarcel int c; 1643130812Smarcel 1644130812Smarcel if (bits (this_instr, 12, 15) != 15) 1645130812Smarcel break; 1646130812Smarcel 1647130812Smarcel if (bits (this_instr, 22, 25) == 0 1648130812Smarcel && bits (this_instr, 4, 7) == 9) /* multiply */ 1649130812Smarcel error ("Illegal update to pc in instruction"); 1650130812Smarcel 1651130812Smarcel /* BX <reg>, BLX <reg> */ 1652130812Smarcel if (bits (this_instr, 4, 28) == 0x12fff1 1653130812Smarcel || bits (this_instr, 4, 28) == 0x12fff3) 1654130812Smarcel { 1655130812Smarcel rn = bits (this_instr, 0, 3); 1656130812Smarcel result = (rn == 15) ? pc_val + 8 : read_register (rn); 1657130812Smarcel nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); 1658130812Smarcel 1659130812Smarcel if (nextpc == pc) 1660130812Smarcel error ("Infinite loop detected"); 1661130812Smarcel 1662130812Smarcel return nextpc; 1663130812Smarcel } 1664130812Smarcel 1665130812Smarcel /* Multiply into PC */ 1666130812Smarcel c = (status & FLAG_C) ? 1 : 0; 1667130812Smarcel rn = bits (this_instr, 16, 19); 1668130812Smarcel operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); 1669130812Smarcel 1670130812Smarcel if (bit (this_instr, 25)) 1671130812Smarcel { 1672130812Smarcel unsigned long immval = bits (this_instr, 0, 7); 1673130812Smarcel unsigned long rotate = 2 * bits (this_instr, 8, 11); 1674130812Smarcel operand2 = ((immval >> rotate) | (immval << (32 - rotate))) 1675130812Smarcel & 0xffffffff; 1676130812Smarcel } 1677130812Smarcel else /* operand 2 is a shifted register */ 1678130812Smarcel operand2 = shifted_reg_val (this_instr, c, pc_val, status); 1679130812Smarcel 1680130812Smarcel switch (bits (this_instr, 21, 24)) 1681130812Smarcel { 1682130812Smarcel case 0x0: /*and */ 1683130812Smarcel result = operand1 & operand2; 1684130812Smarcel break; 1685130812Smarcel 1686130812Smarcel case 0x1: /*eor */ 1687130812Smarcel result = operand1 ^ operand2; 1688130812Smarcel break; 1689130812Smarcel 1690130812Smarcel case 0x2: /*sub */ 1691130812Smarcel result = operand1 - operand2; 1692130812Smarcel break; 1693130812Smarcel 1694130812Smarcel case 0x3: /*rsb */ 1695130812Smarcel result = operand2 - operand1; 1696130812Smarcel break; 1697130812Smarcel 1698130812Smarcel case 0x4: /*add */ 1699130812Smarcel result = operand1 + operand2; 1700130812Smarcel break; 1701130812Smarcel 1702130812Smarcel case 0x5: /*adc */ 1703130812Smarcel result = operand1 + operand2 + c; 1704130812Smarcel break; 1705130812Smarcel 1706130812Smarcel case 0x6: /*sbc */ 1707130812Smarcel result = operand1 - operand2 + c; 1708130812Smarcel break; 1709130812Smarcel 1710130812Smarcel case 0x7: /*rsc */ 1711130812Smarcel result = operand2 - operand1 + c; 1712130812Smarcel break; 1713130812Smarcel 1714130812Smarcel case 0x8: 1715130812Smarcel case 0x9: 1716130812Smarcel case 0xa: 1717130812Smarcel case 0xb: /* tst, teq, cmp, cmn */ 1718130812Smarcel result = (unsigned long) nextpc; 1719130812Smarcel break; 1720130812Smarcel 1721130812Smarcel case 0xc: /*orr */ 1722130812Smarcel result = operand1 | operand2; 1723130812Smarcel break; 1724130812Smarcel 1725130812Smarcel case 0xd: /*mov */ 1726130812Smarcel /* Always step into a function. */ 1727130812Smarcel result = operand2; 1728130812Smarcel break; 1729130812Smarcel 1730130812Smarcel case 0xe: /*bic */ 1731130812Smarcel result = operand1 & ~operand2; 1732130812Smarcel break; 1733130812Smarcel 1734130812Smarcel case 0xf: /*mvn */ 1735130812Smarcel result = ~operand2; 1736130812Smarcel break; 1737130812Smarcel } 1738130812Smarcel nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); 1739130812Smarcel 1740130812Smarcel if (nextpc == pc) 1741130812Smarcel error ("Infinite loop detected"); 1742130812Smarcel break; 1743130812Smarcel } 1744130812Smarcel 1745130812Smarcel case 0x4: 1746130812Smarcel case 0x5: /* data transfer */ 1747130812Smarcel case 0x6: 1748130812Smarcel case 0x7: 1749130812Smarcel if (bit (this_instr, 20)) 1750130812Smarcel { 1751130812Smarcel /* load */ 1752130812Smarcel if (bits (this_instr, 12, 15) == 15) 1753130812Smarcel { 1754130812Smarcel /* rd == pc */ 1755130812Smarcel unsigned long rn; 1756130812Smarcel unsigned long base; 1757130812Smarcel 1758130812Smarcel if (bit (this_instr, 22)) 1759130812Smarcel error ("Illegal update to pc in instruction"); 1760130812Smarcel 1761130812Smarcel /* byte write to PC */ 1762130812Smarcel rn = bits (this_instr, 16, 19); 1763130812Smarcel base = (rn == 15) ? pc_val + 8 : read_register (rn); 1764130812Smarcel if (bit (this_instr, 24)) 1765130812Smarcel { 1766130812Smarcel /* pre-indexed */ 1767130812Smarcel int c = (status & FLAG_C) ? 1 : 0; 1768130812Smarcel unsigned long offset = 1769130812Smarcel (bit (this_instr, 25) 1770130812Smarcel ? shifted_reg_val (this_instr, c, pc_val, status) 1771130812Smarcel : bits (this_instr, 0, 11)); 1772130812Smarcel 1773130812Smarcel if (bit (this_instr, 23)) 1774130812Smarcel base += offset; 1775130812Smarcel else 1776130812Smarcel base -= offset; 1777130812Smarcel } 1778130812Smarcel nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, 1779130812Smarcel 4); 1780130812Smarcel 1781130812Smarcel nextpc = ADDR_BITS_REMOVE (nextpc); 1782130812Smarcel 1783130812Smarcel if (nextpc == pc) 1784130812Smarcel error ("Infinite loop detected"); 1785130812Smarcel } 1786130812Smarcel } 1787130812Smarcel break; 1788130812Smarcel 1789130812Smarcel case 0x8: 1790130812Smarcel case 0x9: /* block transfer */ 1791130812Smarcel if (bit (this_instr, 20)) 1792130812Smarcel { 1793130812Smarcel /* LDM */ 1794130812Smarcel if (bit (this_instr, 15)) 1795130812Smarcel { 1796130812Smarcel /* loading pc */ 1797130812Smarcel int offset = 0; 1798130812Smarcel 1799130812Smarcel if (bit (this_instr, 23)) 1800130812Smarcel { 1801130812Smarcel /* up */ 1802130812Smarcel unsigned long reglist = bits (this_instr, 0, 14); 1803130812Smarcel offset = bitcount (reglist) * 4; 1804130812Smarcel if (bit (this_instr, 24)) /* pre */ 1805130812Smarcel offset += 4; 1806130812Smarcel } 1807130812Smarcel else if (bit (this_instr, 24)) 1808130812Smarcel offset = -4; 1809130812Smarcel 1810130812Smarcel { 1811130812Smarcel unsigned long rn_val = 1812130812Smarcel read_register (bits (this_instr, 16, 19)); 1813130812Smarcel nextpc = 1814130812Smarcel (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val 1815130812Smarcel + offset), 1816130812Smarcel 4); 1817130812Smarcel } 1818130812Smarcel nextpc = ADDR_BITS_REMOVE (nextpc); 1819130812Smarcel if (nextpc == pc) 1820130812Smarcel error ("Infinite loop detected"); 1821130812Smarcel } 1822130812Smarcel } 1823130812Smarcel break; 1824130812Smarcel 1825130812Smarcel case 0xb: /* branch & link */ 1826130812Smarcel case 0xa: /* branch */ 1827130812Smarcel { 1828130812Smarcel nextpc = BranchDest (pc, this_instr); 1829130812Smarcel 1830130812Smarcel /* BLX */ 1831130812Smarcel if (bits (this_instr, 28, 31) == INST_NV) 1832130812Smarcel nextpc |= bit (this_instr, 24) << 1; 1833130812Smarcel 1834130812Smarcel nextpc = ADDR_BITS_REMOVE (nextpc); 1835130812Smarcel if (nextpc == pc) 1836130812Smarcel error ("Infinite loop detected"); 1837130812Smarcel break; 1838130812Smarcel } 1839130812Smarcel 1840130812Smarcel case 0xc: 1841130812Smarcel case 0xd: 1842130812Smarcel case 0xe: /* coproc ops */ 1843130812Smarcel case 0xf: /* SWI */ 1844130812Smarcel break; 1845130812Smarcel 1846130812Smarcel default: 1847130812Smarcel fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); 1848130812Smarcel return (pc); 1849130812Smarcel } 1850130812Smarcel } 1851130812Smarcel 1852130812Smarcel return nextpc; 1853130812Smarcel} 1854130812Smarcel 1855130812Smarcel/* single_step() is called just before we want to resume the inferior, 1856130812Smarcel if we want to single-step it but there is no hardware or kernel 1857130812Smarcel single-step support. We find the target of the coming instruction 1858130812Smarcel and breakpoint it. 1859130812Smarcel 1860130812Smarcel single_step() is also called just after the inferior stops. If we 1861130812Smarcel had set up a simulated single-step, we undo our damage. */ 1862130812Smarcel 1863130812Smarcelstatic void 1864130812Smarcelarm_software_single_step (enum target_signal sig, int insert_bpt) 1865130812Smarcel{ 1866130812Smarcel static int next_pc; /* State between setting and unsetting. */ 1867130812Smarcel static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ 1868130812Smarcel 1869130812Smarcel if (insert_bpt) 1870130812Smarcel { 1871130812Smarcel next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); 1872130812Smarcel target_insert_breakpoint (next_pc, break_mem); 1873130812Smarcel } 1874130812Smarcel else 1875130812Smarcel target_remove_breakpoint (next_pc, break_mem); 1876130812Smarcel} 1877130812Smarcel 1878130812Smarcel#include "bfd-in2.h" 1879130812Smarcel#include "libcoff.h" 1880130812Smarcel 1881130812Smarcelstatic int 1882130812Smarcelgdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) 1883130812Smarcel{ 1884130812Smarcel if (arm_pc_is_thumb (memaddr)) 1885130812Smarcel { 1886130812Smarcel static asymbol *asym; 1887130812Smarcel static combined_entry_type ce; 1888130812Smarcel static struct coff_symbol_struct csym; 1889130812Smarcel static struct bfd fake_bfd; 1890130812Smarcel static bfd_target fake_target; 1891130812Smarcel 1892130812Smarcel if (csym.native == NULL) 1893130812Smarcel { 1894130812Smarcel /* Create a fake symbol vector containing a Thumb symbol. 1895130812Smarcel This is solely so that the code in print_insn_little_arm() 1896130812Smarcel and print_insn_big_arm() in opcodes/arm-dis.c will detect 1897130812Smarcel the presence of a Thumb symbol and switch to decoding 1898130812Smarcel Thumb instructions. */ 1899130812Smarcel 1900130812Smarcel fake_target.flavour = bfd_target_coff_flavour; 1901130812Smarcel fake_bfd.xvec = &fake_target; 1902130812Smarcel ce.u.syment.n_sclass = C_THUMBEXTFUNC; 1903130812Smarcel csym.native = &ce; 1904130812Smarcel csym.symbol.the_bfd = &fake_bfd; 1905130812Smarcel csym.symbol.name = "fake"; 1906130812Smarcel asym = (asymbol *) & csym; 1907130812Smarcel } 1908130812Smarcel 1909130812Smarcel memaddr = UNMAKE_THUMB_ADDR (memaddr); 1910130812Smarcel info->symbols = &asym; 1911130812Smarcel } 1912130812Smarcel else 1913130812Smarcel info->symbols = NULL; 1914130812Smarcel 1915130812Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1916130812Smarcel return print_insn_big_arm (memaddr, info); 1917130812Smarcel else 1918130812Smarcel return print_insn_little_arm (memaddr, info); 1919130812Smarcel} 1920130812Smarcel 1921130812Smarcel/* The following define instruction sequences that will cause ARM 1922130812Smarcel cpu's to take an undefined instruction trap. These are used to 1923130812Smarcel signal a breakpoint to GDB. 1924130812Smarcel 1925130812Smarcel The newer ARMv4T cpu's are capable of operating in ARM or Thumb 1926130812Smarcel modes. A different instruction is required for each mode. The ARM 1927130812Smarcel cpu's can also be big or little endian. Thus four different 1928130812Smarcel instructions are needed to support all cases. 1929130812Smarcel 1930130812Smarcel Note: ARMv4 defines several new instructions that will take the 1931130812Smarcel undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does 1932130812Smarcel not in fact add the new instructions. The new undefined 1933130812Smarcel instructions in ARMv4 are all instructions that had no defined 1934130812Smarcel behaviour in earlier chips. There is no guarantee that they will 1935130812Smarcel raise an exception, but may be treated as NOP's. In practice, it 1936130812Smarcel may only safe to rely on instructions matching: 1937130812Smarcel 1938130812Smarcel 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1939130812Smarcel 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1940130812Smarcel C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x 1941130812Smarcel 1942130812Smarcel Even this may only true if the condition predicate is true. The 1943130812Smarcel following use a condition predicate of ALWAYS so it is always TRUE. 1944130812Smarcel 1945130812Smarcel There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, 1946130812Smarcel and NetBSD all use a software interrupt rather than an undefined 1947130812Smarcel instruction to force a trap. This can be handled by by the 1948130812Smarcel abi-specific code during establishment of the gdbarch vector. */ 1949130812Smarcel 1950130812Smarcel 1951130812Smarcel/* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to 1952130812Smarcel override these definitions. */ 1953130812Smarcel#ifndef ARM_LE_BREAKPOINT 1954130812Smarcel#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} 1955130812Smarcel#endif 1956130812Smarcel#ifndef ARM_BE_BREAKPOINT 1957130812Smarcel#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} 1958130812Smarcel#endif 1959130812Smarcel#ifndef THUMB_LE_BREAKPOINT 1960130812Smarcel#define THUMB_LE_BREAKPOINT {0xfe,0xdf} 1961130812Smarcel#endif 1962130812Smarcel#ifndef THUMB_BE_BREAKPOINT 1963130812Smarcel#define THUMB_BE_BREAKPOINT {0xdf,0xfe} 1964130812Smarcel#endif 1965130812Smarcel 1966130812Smarcelstatic const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; 1967130812Smarcelstatic const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; 1968130812Smarcelstatic const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; 1969130812Smarcelstatic const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; 1970130812Smarcel 1971130812Smarcel/* Determine the type and size of breakpoint to insert at PCPTR. Uses 1972130812Smarcel the program counter value to determine whether a 16-bit or 32-bit 1973130812Smarcel breakpoint should be used. It returns a pointer to a string of 1974130812Smarcel bytes that encode a breakpoint instruction, stores the length of 1975130812Smarcel the string to *lenptr, and adjusts the program counter (if 1976130812Smarcel necessary) to point to the actual memory location where the 1977130812Smarcel breakpoint should be inserted. */ 1978130812Smarcel 1979130812Smarcel/* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting 1980130812Smarcel breakpoints and storing their handles instread of what was in 1981130812Smarcel memory. It is nice that this is the same size as a handle - 1982130812Smarcel otherwise remote-rdp will have to change. */ 1983130812Smarcel 1984130812Smarcelstatic const unsigned char * 1985130812Smarcelarm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 1986130812Smarcel{ 1987130812Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1988130812Smarcel 1989185024Sraj if (arm_pc_is_thumb (*pcptr)) 1990130812Smarcel { 1991130812Smarcel *pcptr = UNMAKE_THUMB_ADDR (*pcptr); 1992130812Smarcel *lenptr = tdep->thumb_breakpoint_size; 1993130812Smarcel return tdep->thumb_breakpoint; 1994130812Smarcel } 1995130812Smarcel else 1996130812Smarcel { 1997130812Smarcel *lenptr = tdep->arm_breakpoint_size; 1998130812Smarcel return tdep->arm_breakpoint; 1999130812Smarcel } 2000130812Smarcel} 2001130812Smarcel 2002130812Smarcel/* Extract from an array REGBUF containing the (raw) register state a 2003130812Smarcel function return value of type TYPE, and copy that, in virtual 2004130812Smarcel format, into VALBUF. */ 2005130812Smarcel 2006130812Smarcelstatic void 2007130812Smarcelarm_extract_return_value (struct type *type, 2008130812Smarcel struct regcache *regs, 2009130812Smarcel void *dst) 2010130812Smarcel{ 2011130812Smarcel bfd_byte *valbuf = dst; 2012130812Smarcel 2013130812Smarcel if (TYPE_CODE_FLT == TYPE_CODE (type)) 2014130812Smarcel { 2015130812Smarcel switch (arm_get_fp_model (current_gdbarch)) 2016130812Smarcel { 2017130812Smarcel case ARM_FLOAT_FPA: 2018130812Smarcel { 2019130812Smarcel /* The value is in register F0 in internal format. We need to 2020130812Smarcel extract the raw value and then convert it to the desired 2021130812Smarcel internal type. */ 2022130812Smarcel bfd_byte tmpbuf[FP_REGISTER_SIZE]; 2023130812Smarcel 2024130812Smarcel regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); 2025130812Smarcel convert_from_extended (floatformat_from_type (type), tmpbuf, 2026130812Smarcel valbuf); 2027130812Smarcel } 2028130812Smarcel break; 2029130812Smarcel 2030130812Smarcel case ARM_FLOAT_SOFT_FPA: 2031130812Smarcel case ARM_FLOAT_SOFT_VFP: 2032130812Smarcel regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); 2033130812Smarcel if (TYPE_LENGTH (type) > 4) 2034130812Smarcel regcache_cooked_read (regs, ARM_A1_REGNUM + 1, 2035130812Smarcel valbuf + INT_REGISTER_SIZE); 2036130812Smarcel break; 2037130812Smarcel 2038130812Smarcel default: 2039130812Smarcel internal_error 2040130812Smarcel (__FILE__, __LINE__, 2041130812Smarcel "arm_extract_return_value: Floating point model not supported"); 2042130812Smarcel break; 2043130812Smarcel } 2044130812Smarcel } 2045130812Smarcel else if (TYPE_CODE (type) == TYPE_CODE_INT 2046130812Smarcel || TYPE_CODE (type) == TYPE_CODE_CHAR 2047130812Smarcel || TYPE_CODE (type) == TYPE_CODE_BOOL 2048130812Smarcel || TYPE_CODE (type) == TYPE_CODE_PTR 2049130812Smarcel || TYPE_CODE (type) == TYPE_CODE_REF 2050130812Smarcel || TYPE_CODE (type) == TYPE_CODE_ENUM) 2051130812Smarcel { 2052130812Smarcel /* If the the type is a plain integer, then the access is 2053130812Smarcel straight-forward. Otherwise we have to play around a bit more. */ 2054130812Smarcel int len = TYPE_LENGTH (type); 2055130812Smarcel int regno = ARM_A1_REGNUM; 2056130812Smarcel ULONGEST tmp; 2057130812Smarcel 2058130812Smarcel while (len > 0) 2059130812Smarcel { 2060130812Smarcel /* By using store_unsigned_integer we avoid having to do 2061130812Smarcel anything special for small big-endian values. */ 2062130812Smarcel regcache_cooked_read_unsigned (regs, regno++, &tmp); 2063130812Smarcel store_unsigned_integer (valbuf, 2064130812Smarcel (len > INT_REGISTER_SIZE 2065130812Smarcel ? INT_REGISTER_SIZE : len), 2066130812Smarcel tmp); 2067130812Smarcel len -= INT_REGISTER_SIZE; 2068130812Smarcel valbuf += INT_REGISTER_SIZE; 2069130812Smarcel } 2070130812Smarcel } 2071130812Smarcel else 2072130812Smarcel { 2073130812Smarcel /* For a structure or union the behaviour is as if the value had 2074130812Smarcel been stored to word-aligned memory and then loaded into 2075130812Smarcel registers with 32-bit load instruction(s). */ 2076130812Smarcel int len = TYPE_LENGTH (type); 2077130812Smarcel int regno = ARM_A1_REGNUM; 2078130812Smarcel bfd_byte tmpbuf[INT_REGISTER_SIZE]; 2079130812Smarcel 2080130812Smarcel while (len > 0) 2081130812Smarcel { 2082130812Smarcel regcache_cooked_read (regs, regno++, tmpbuf); 2083130812Smarcel memcpy (valbuf, tmpbuf, 2084130812Smarcel len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); 2085130812Smarcel len -= INT_REGISTER_SIZE; 2086130812Smarcel valbuf += INT_REGISTER_SIZE; 2087130812Smarcel } 2088130812Smarcel } 2089130812Smarcel} 2090130812Smarcel 2091130812Smarcel/* Extract from an array REGBUF containing the (raw) register state 2092130812Smarcel the address in which a function should return its structure value. */ 2093130812Smarcel 2094130812Smarcelstatic CORE_ADDR 2095130812Smarcelarm_extract_struct_value_address (struct regcache *regcache) 2096130812Smarcel{ 2097130812Smarcel ULONGEST ret; 2098130812Smarcel 2099130812Smarcel regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); 2100130812Smarcel return ret; 2101130812Smarcel} 2102130812Smarcel 2103130812Smarcel/* Will a function return an aggregate type in memory or in a 2104130812Smarcel register? Return 0 if an aggregate type can be returned in a 2105130812Smarcel register, 1 if it must be returned in memory. */ 2106130812Smarcel 2107130812Smarcelstatic int 2108130812Smarcelarm_use_struct_convention (int gcc_p, struct type *type) 2109130812Smarcel{ 2110130812Smarcel int nRc; 2111130812Smarcel enum type_code code; 2112130812Smarcel 2113130812Smarcel CHECK_TYPEDEF (type); 2114130812Smarcel 2115130812Smarcel /* In the ARM ABI, "integer" like aggregate types are returned in 2116130812Smarcel registers. For an aggregate type to be integer like, its size 2117130812Smarcel must be less than or equal to DEPRECATED_REGISTER_SIZE and the 2118130812Smarcel offset of each addressable subfield must be zero. Note that bit 2119130812Smarcel fields are not addressable, and all addressable subfields of 2120130812Smarcel unions always start at offset zero. 2121130812Smarcel 2122130812Smarcel This function is based on the behaviour of GCC 2.95.1. 2123130812Smarcel See: gcc/arm.c: arm_return_in_memory() for details. 2124130812Smarcel 2125130812Smarcel Note: All versions of GCC before GCC 2.95.2 do not set up the 2126130812Smarcel parameters correctly for a function returning the following 2127130812Smarcel structure: struct { float f;}; This should be returned in memory, 2128130812Smarcel not a register. Richard Earnshaw sent me a patch, but I do not 2129130812Smarcel know of any way to detect if a function like the above has been 2130130812Smarcel compiled with the correct calling convention. */ 2131130812Smarcel 2132130812Smarcel /* All aggregate types that won't fit in a register must be returned 2133130812Smarcel in memory. */ 2134130812Smarcel if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) 2135130812Smarcel { 2136130812Smarcel return 1; 2137130812Smarcel } 2138130812Smarcel 2139130812Smarcel /* The only aggregate types that can be returned in a register are 2140130812Smarcel structs and unions. Arrays must be returned in memory. */ 2141130812Smarcel code = TYPE_CODE (type); 2142130812Smarcel if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) 2143130812Smarcel { 2144130812Smarcel return 1; 2145130812Smarcel } 2146130812Smarcel 2147130812Smarcel /* Assume all other aggregate types can be returned in a register. 2148130812Smarcel Run a check for structures, unions and arrays. */ 2149130812Smarcel nRc = 0; 2150130812Smarcel 2151130812Smarcel if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) 2152130812Smarcel { 2153130812Smarcel int i; 2154130812Smarcel /* Need to check if this struct/union is "integer" like. For 2155130812Smarcel this to be true, its size must be less than or equal to 2156130812Smarcel DEPRECATED_REGISTER_SIZE and the offset of each addressable 2157130812Smarcel subfield must be zero. Note that bit fields are not 2158130812Smarcel addressable, and unions always start at offset zero. If any 2159130812Smarcel of the subfields is a floating point type, the struct/union 2160130812Smarcel cannot be an integer type. */ 2161130812Smarcel 2162130812Smarcel /* For each field in the object, check: 2163130812Smarcel 1) Is it FP? --> yes, nRc = 1; 2164130812Smarcel 2) Is it addressable (bitpos != 0) and 2165130812Smarcel not packed (bitsize == 0)? 2166130812Smarcel --> yes, nRc = 1 2167130812Smarcel */ 2168130812Smarcel 2169130812Smarcel for (i = 0; i < TYPE_NFIELDS (type); i++) 2170130812Smarcel { 2171130812Smarcel enum type_code field_type_code; 2172130812Smarcel field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); 2173130812Smarcel 2174130812Smarcel /* Is it a floating point type field? */ 2175130812Smarcel if (field_type_code == TYPE_CODE_FLT) 2176130812Smarcel { 2177130812Smarcel nRc = 1; 2178130812Smarcel break; 2179130812Smarcel } 2180130812Smarcel 2181130812Smarcel /* If bitpos != 0, then we have to care about it. */ 2182130812Smarcel if (TYPE_FIELD_BITPOS (type, i) != 0) 2183130812Smarcel { 2184130812Smarcel /* Bitfields are not addressable. If the field bitsize is 2185130812Smarcel zero, then the field is not packed. Hence it cannot be 2186130812Smarcel a bitfield or any other packed type. */ 2187130812Smarcel if (TYPE_FIELD_BITSIZE (type, i) == 0) 2188130812Smarcel { 2189130812Smarcel nRc = 1; 2190130812Smarcel break; 2191130812Smarcel } 2192130812Smarcel } 2193130812Smarcel } 2194130812Smarcel } 2195130812Smarcel 2196130812Smarcel return nRc; 2197130812Smarcel} 2198130812Smarcel 2199130812Smarcel/* Write into appropriate registers a function return value of type 2200130812Smarcel TYPE, given in virtual format. */ 2201130812Smarcel 2202130812Smarcelstatic void 2203130812Smarcelarm_store_return_value (struct type *type, struct regcache *regs, 2204130812Smarcel const void *src) 2205130812Smarcel{ 2206130812Smarcel const bfd_byte *valbuf = src; 2207130812Smarcel 2208130812Smarcel if (TYPE_CODE (type) == TYPE_CODE_FLT) 2209130812Smarcel { 2210130812Smarcel char buf[MAX_REGISTER_SIZE]; 2211130812Smarcel 2212130812Smarcel switch (arm_get_fp_model (current_gdbarch)) 2213130812Smarcel { 2214130812Smarcel case ARM_FLOAT_FPA: 2215130812Smarcel 2216130812Smarcel convert_to_extended (floatformat_from_type (type), buf, valbuf); 2217130812Smarcel regcache_cooked_write (regs, ARM_F0_REGNUM, buf); 2218130812Smarcel break; 2219130812Smarcel 2220130812Smarcel case ARM_FLOAT_SOFT_FPA: 2221130812Smarcel case ARM_FLOAT_SOFT_VFP: 2222130812Smarcel regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); 2223130812Smarcel if (TYPE_LENGTH (type) > 4) 2224130812Smarcel regcache_cooked_write (regs, ARM_A1_REGNUM + 1, 2225130812Smarcel valbuf + INT_REGISTER_SIZE); 2226130812Smarcel break; 2227130812Smarcel 2228130812Smarcel default: 2229130812Smarcel internal_error 2230130812Smarcel (__FILE__, __LINE__, 2231130812Smarcel "arm_store_return_value: Floating point model not supported"); 2232130812Smarcel break; 2233130812Smarcel } 2234130812Smarcel } 2235130812Smarcel else if (TYPE_CODE (type) == TYPE_CODE_INT 2236130812Smarcel || TYPE_CODE (type) == TYPE_CODE_CHAR 2237130812Smarcel || TYPE_CODE (type) == TYPE_CODE_BOOL 2238130812Smarcel || TYPE_CODE (type) == TYPE_CODE_PTR 2239130812Smarcel || TYPE_CODE (type) == TYPE_CODE_REF 2240130812Smarcel || TYPE_CODE (type) == TYPE_CODE_ENUM) 2241130812Smarcel { 2242130812Smarcel if (TYPE_LENGTH (type) <= 4) 2243130812Smarcel { 2244130812Smarcel /* Values of one word or less are zero/sign-extended and 2245130812Smarcel returned in r0. */ 2246130812Smarcel bfd_byte tmpbuf[INT_REGISTER_SIZE]; 2247130812Smarcel LONGEST val = unpack_long (type, valbuf); 2248130812Smarcel 2249130812Smarcel store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); 2250130812Smarcel regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); 2251130812Smarcel } 2252130812Smarcel else 2253130812Smarcel { 2254130812Smarcel /* Integral values greater than one word are stored in consecutive 2255130812Smarcel registers starting with r0. This will always be a multiple of 2256130812Smarcel the regiser size. */ 2257130812Smarcel int len = TYPE_LENGTH (type); 2258130812Smarcel int regno = ARM_A1_REGNUM; 2259130812Smarcel 2260130812Smarcel while (len > 0) 2261130812Smarcel { 2262130812Smarcel regcache_cooked_write (regs, regno++, valbuf); 2263130812Smarcel len -= INT_REGISTER_SIZE; 2264130812Smarcel valbuf += INT_REGISTER_SIZE; 2265130812Smarcel } 2266130812Smarcel } 2267130812Smarcel } 2268130812Smarcel else 2269130812Smarcel { 2270130812Smarcel /* For a structure or union the behaviour is as if the value had 2271130812Smarcel been stored to word-aligned memory and then loaded into 2272130812Smarcel registers with 32-bit load instruction(s). */ 2273130812Smarcel int len = TYPE_LENGTH (type); 2274130812Smarcel int regno = ARM_A1_REGNUM; 2275130812Smarcel bfd_byte tmpbuf[INT_REGISTER_SIZE]; 2276130812Smarcel 2277130812Smarcel while (len > 0) 2278130812Smarcel { 2279130812Smarcel memcpy (tmpbuf, valbuf, 2280130812Smarcel len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); 2281130812Smarcel regcache_cooked_write (regs, regno++, tmpbuf); 2282130812Smarcel len -= INT_REGISTER_SIZE; 2283130812Smarcel valbuf += INT_REGISTER_SIZE; 2284130812Smarcel } 2285130812Smarcel } 2286130812Smarcel} 2287130812Smarcel 2288130812Smarcelstatic int 2289130812Smarcelarm_get_longjmp_target (CORE_ADDR *pc) 2290130812Smarcel{ 2291130812Smarcel CORE_ADDR jb_addr; 2292130812Smarcel char buf[INT_REGISTER_SIZE]; 2293130812Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2294130812Smarcel 2295130812Smarcel jb_addr = read_register (ARM_A1_REGNUM); 2296130812Smarcel 2297130812Smarcel if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, 2298130812Smarcel INT_REGISTER_SIZE)) 2299130812Smarcel return 0; 2300130812Smarcel 2301130812Smarcel *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); 2302130812Smarcel return 1; 2303130812Smarcel} 2304130812Smarcel 2305130812Smarcel/* Return non-zero if the PC is inside a thumb call thunk. */ 2306130812Smarcel 2307130812Smarcelint 2308130812Smarcelarm_in_call_stub (CORE_ADDR pc, char *name) 2309130812Smarcel{ 2310130812Smarcel CORE_ADDR start_addr; 2311130812Smarcel 2312130812Smarcel /* Find the starting address of the function containing the PC. If 2313130812Smarcel the caller didn't give us a name, look it up at the same time. */ 2314130812Smarcel if (0 == find_pc_partial_function (pc, name ? NULL : &name, 2315130812Smarcel &start_addr, NULL)) 2316130812Smarcel return 0; 2317130812Smarcel 2318130812Smarcel return strncmp (name, "_call_via_r", 11) == 0; 2319130812Smarcel} 2320130812Smarcel 2321130812Smarcel/* If PC is in a Thumb call or return stub, return the address of the 2322130812Smarcel target PC, which is in a register. The thunk functions are called 2323130812Smarcel _called_via_xx, where x is the register name. The possible names 2324130812Smarcel are r0-r9, sl, fp, ip, sp, and lr. */ 2325130812Smarcel 2326130812SmarcelCORE_ADDR 2327130812Smarcelarm_skip_stub (CORE_ADDR pc) 2328130812Smarcel{ 2329130812Smarcel char *name; 2330130812Smarcel CORE_ADDR start_addr; 2331130812Smarcel 2332130812Smarcel /* Find the starting address and name of the function containing the PC. */ 2333130812Smarcel if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 2334130812Smarcel return 0; 2335130812Smarcel 2336130812Smarcel /* Call thunks always start with "_call_via_". */ 2337130812Smarcel if (strncmp (name, "_call_via_", 10) == 0) 2338130812Smarcel { 2339130812Smarcel /* Use the name suffix to determine which register contains the 2340130812Smarcel target PC. */ 2341130812Smarcel static char *table[15] = 2342130812Smarcel {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 2343130812Smarcel "r8", "r9", "sl", "fp", "ip", "sp", "lr" 2344130812Smarcel }; 2345130812Smarcel int regno; 2346130812Smarcel 2347130812Smarcel for (regno = 0; regno <= 14; regno++) 2348130812Smarcel if (strcmp (&name[10], table[regno]) == 0) 2349130812Smarcel return read_register (regno); 2350130812Smarcel } 2351130812Smarcel 2352130812Smarcel return 0; /* not a stub */ 2353130812Smarcel} 2354130812Smarcel 2355130812Smarcelstatic void 2356130812Smarcelset_arm_command (char *args, int from_tty) 2357130812Smarcel{ 2358130812Smarcel printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); 2359130812Smarcel help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); 2360130812Smarcel} 2361130812Smarcel 2362130812Smarcelstatic void 2363130812Smarcelshow_arm_command (char *args, int from_tty) 2364130812Smarcel{ 2365130812Smarcel cmd_show_list (showarmcmdlist, from_tty, ""); 2366130812Smarcel} 2367130812Smarcel 2368130812Smarcelenum arm_float_model 2369130812Smarcelarm_get_fp_model (struct gdbarch *gdbarch) 2370130812Smarcel{ 2371130812Smarcel if (arm_fp_model == ARM_FLOAT_AUTO) 2372130812Smarcel return gdbarch_tdep (gdbarch)->fp_model; 2373130812Smarcel 2374130812Smarcel return arm_fp_model; 2375130812Smarcel} 2376130812Smarcel 2377130812Smarcelstatic void 2378130812Smarcelarm_set_fp (struct gdbarch *gdbarch) 2379130812Smarcel{ 2380130812Smarcel enum arm_float_model fp_model = arm_get_fp_model (gdbarch); 2381130812Smarcel 2382130812Smarcel if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 2383130812Smarcel && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) 2384130812Smarcel { 2385130812Smarcel set_gdbarch_double_format (gdbarch, 2386130812Smarcel &floatformat_ieee_double_littlebyte_bigword); 2387130812Smarcel set_gdbarch_long_double_format 2388130812Smarcel (gdbarch, &floatformat_ieee_double_littlebyte_bigword); 2389130812Smarcel } 2390130812Smarcel else 2391130812Smarcel { 2392130812Smarcel set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); 2393130812Smarcel set_gdbarch_long_double_format (gdbarch, 2394130812Smarcel &floatformat_ieee_double_little); 2395130812Smarcel } 2396130812Smarcel} 2397130812Smarcel 2398130812Smarcelstatic void 2399130812Smarcelset_fp_model_sfunc (char *args, int from_tty, 2400130812Smarcel struct cmd_list_element *c) 2401130812Smarcel{ 2402130812Smarcel enum arm_float_model fp_model; 2403130812Smarcel 2404130812Smarcel for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) 2405130812Smarcel if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) 2406130812Smarcel { 2407130812Smarcel arm_fp_model = fp_model; 2408130812Smarcel break; 2409130812Smarcel } 2410130812Smarcel 2411130812Smarcel if (fp_model == ARM_FLOAT_LAST) 2412130812Smarcel internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", 2413130812Smarcel current_fp_model); 2414130812Smarcel 2415130812Smarcel if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) 2416130812Smarcel arm_set_fp (current_gdbarch); 2417130812Smarcel} 2418130812Smarcel 2419130812Smarcelstatic void 2420130812Smarcelshow_fp_model (char *args, int from_tty, 2421130812Smarcel struct cmd_list_element *c) 2422130812Smarcel{ 2423130812Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2424130812Smarcel 2425130812Smarcel if (arm_fp_model == ARM_FLOAT_AUTO 2426130812Smarcel && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) 2427130812Smarcel printf_filtered (" - the default for the current ABI is \"%s\".\n", 2428130812Smarcel fp_model_strings[tdep->fp_model]); 2429130812Smarcel} 2430130812Smarcel 2431130812Smarcel/* If the user changes the register disassembly style used for info 2432130812Smarcel register and other commands, we have to also switch the style used 2433130812Smarcel in opcodes for disassembly output. This function is run in the "set 2434130812Smarcel arm disassembly" command, and does that. */ 2435130812Smarcel 2436130812Smarcelstatic void 2437130812Smarcelset_disassembly_style_sfunc (char *args, int from_tty, 2438130812Smarcel struct cmd_list_element *c) 2439130812Smarcel{ 2440130812Smarcel set_disassembly_style (); 2441130812Smarcel} 2442130812Smarcel 2443130812Smarcel/* Return the ARM register name corresponding to register I. */ 2444130812Smarcelstatic const char * 2445130812Smarcelarm_register_name (int i) 2446130812Smarcel{ 2447130812Smarcel return arm_register_names[i]; 2448130812Smarcel} 2449130812Smarcel 2450130812Smarcelstatic void 2451130812Smarcelset_disassembly_style (void) 2452130812Smarcel{ 2453130812Smarcel const char *setname, *setdesc, **regnames; 2454130812Smarcel int numregs, j; 2455130812Smarcel 2456130812Smarcel /* Find the style that the user wants in the opcodes table. */ 2457130812Smarcel int current = 0; 2458130812Smarcel numregs = get_arm_regnames (current, &setname, &setdesc, ®names); 2459130812Smarcel while ((disassembly_style != setname) 2460130812Smarcel && (current < num_disassembly_options)) 2461130812Smarcel get_arm_regnames (++current, &setname, &setdesc, ®names); 2462130812Smarcel current_option = current; 2463130812Smarcel 2464130812Smarcel /* Fill our copy. */ 2465130812Smarcel for (j = 0; j < numregs; j++) 2466130812Smarcel arm_register_names[j] = (char *) regnames[j]; 2467130812Smarcel 2468130812Smarcel /* Adjust case. */ 2469130812Smarcel if (isupper (*regnames[ARM_PC_REGNUM])) 2470130812Smarcel { 2471130812Smarcel arm_register_names[ARM_FPS_REGNUM] = "FPS"; 2472130812Smarcel arm_register_names[ARM_PS_REGNUM] = "CPSR"; 2473130812Smarcel } 2474130812Smarcel else 2475130812Smarcel { 2476130812Smarcel arm_register_names[ARM_FPS_REGNUM] = "fps"; 2477130812Smarcel arm_register_names[ARM_PS_REGNUM] = "cpsr"; 2478130812Smarcel } 2479130812Smarcel 2480130812Smarcel /* Synchronize the disassembler. */ 2481130812Smarcel set_arm_regname_option (current); 2482130812Smarcel} 2483130812Smarcel 2484130812Smarcel/* arm_othernames implements the "othernames" command. This is deprecated 2485130812Smarcel by the "set arm disassembly" command. */ 2486130812Smarcel 2487130812Smarcelstatic void 2488130812Smarcelarm_othernames (char *names, int n) 2489130812Smarcel{ 2490130812Smarcel /* Circle through the various flavors. */ 2491130812Smarcel current_option = (current_option + 1) % num_disassembly_options; 2492130812Smarcel 2493130812Smarcel disassembly_style = valid_disassembly_styles[current_option]; 2494130812Smarcel set_disassembly_style (); 2495130812Smarcel} 2496130812Smarcel 2497130812Smarcel/* Test whether the coff symbol specific value corresponds to a Thumb 2498130812Smarcel function. */ 2499130812Smarcel 2500130812Smarcelstatic int 2501130812Smarcelcoff_sym_is_thumb (int val) 2502130812Smarcel{ 2503130812Smarcel return (val == C_THUMBEXT || 2504130812Smarcel val == C_THUMBSTAT || 2505130812Smarcel val == C_THUMBEXTFUNC || 2506130812Smarcel val == C_THUMBSTATFUNC || 2507130812Smarcel val == C_THUMBLABEL); 2508130812Smarcel} 2509130812Smarcel 2510130812Smarcel/* arm_coff_make_msymbol_special() 2511130812Smarcel arm_elf_make_msymbol_special() 2512130812Smarcel 2513130812Smarcel These functions test whether the COFF or ELF symbol corresponds to 2514130812Smarcel an address in thumb code, and set a "special" bit in a minimal 2515130812Smarcel symbol to indicate that it does. */ 2516130812Smarcel 2517130812Smarcelstatic void 2518130812Smarcelarm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) 2519130812Smarcel{ 2520130812Smarcel /* Thumb symbols are of type STT_LOPROC, (synonymous with 2521130812Smarcel STT_ARM_TFUNC). */ 2522130812Smarcel if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) 2523130812Smarcel == STT_LOPROC) 2524130812Smarcel MSYMBOL_SET_SPECIAL (msym); 2525130812Smarcel} 2526130812Smarcel 2527130812Smarcelstatic void 2528130812Smarcelarm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) 2529130812Smarcel{ 2530130812Smarcel if (coff_sym_is_thumb (val)) 2531130812Smarcel MSYMBOL_SET_SPECIAL (msym); 2532130812Smarcel} 2533130812Smarcel 2534130812Smarcelstatic void 2535130812Smarcelarm_write_pc (CORE_ADDR pc, ptid_t ptid) 2536130812Smarcel{ 2537130812Smarcel write_register_pid (ARM_PC_REGNUM, pc, ptid); 2538130812Smarcel 2539130812Smarcel /* If necessary, set the T bit. */ 2540130812Smarcel if (arm_apcs_32) 2541130812Smarcel { 2542130812Smarcel CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); 2543130812Smarcel if (arm_pc_is_thumb (pc)) 2544130812Smarcel write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); 2545130812Smarcel else 2546130812Smarcel write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); 2547130812Smarcel } 2548130812Smarcel} 2549130812Smarcel 2550130812Smarcelstatic enum gdb_osabi 2551130812Smarcelarm_elf_osabi_sniffer (bfd *abfd) 2552130812Smarcel{ 2553130812Smarcel unsigned int elfosabi, eflags; 2554130812Smarcel enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; 2555130812Smarcel 2556130812Smarcel elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; 2557130812Smarcel 2558130812Smarcel switch (elfosabi) 2559130812Smarcel { 2560130812Smarcel case ELFOSABI_NONE: 2561130812Smarcel /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the 2562130812Smarcel file are conforming to the base specification for that machine 2563130812Smarcel (there are no OS-specific extensions). In order to determine the 2564130812Smarcel real OS in use we must look for OS notes that have been added. */ 2565130812Smarcel bfd_map_over_sections (abfd, 2566130812Smarcel generic_elf_osabi_sniff_abi_tag_sections, 2567130812Smarcel &osabi); 2568130812Smarcel if (osabi == GDB_OSABI_UNKNOWN) 2569130812Smarcel { 2570130812Smarcel /* Existing ARM tools don't set this field, so look at the EI_FLAGS 2571130812Smarcel field for more information. */ 2572130812Smarcel eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); 2573130812Smarcel switch (eflags) 2574130812Smarcel { 2575130812Smarcel case EF_ARM_EABI_VER1: 2576130812Smarcel osabi = GDB_OSABI_ARM_EABI_V1; 2577130812Smarcel break; 2578130812Smarcel 2579130812Smarcel case EF_ARM_EABI_VER2: 2580130812Smarcel osabi = GDB_OSABI_ARM_EABI_V2; 2581130812Smarcel break; 2582130812Smarcel 2583130812Smarcel case EF_ARM_EABI_UNKNOWN: 2584130812Smarcel /* Assume GNU tools. */ 2585130812Smarcel osabi = GDB_OSABI_ARM_APCS; 2586130812Smarcel break; 2587130812Smarcel 2588130812Smarcel default: 2589130812Smarcel internal_error (__FILE__, __LINE__, 2590130812Smarcel "arm_elf_osabi_sniffer: Unknown ARM EABI " 2591130812Smarcel "version 0x%x", eflags); 2592130812Smarcel } 2593130812Smarcel } 2594130812Smarcel break; 2595130812Smarcel 2596130812Smarcel case ELFOSABI_ARM: 2597130812Smarcel /* GNU tools use this value. Check note sections in this case, 2598130812Smarcel as well. */ 2599130812Smarcel bfd_map_over_sections (abfd, 2600130812Smarcel generic_elf_osabi_sniff_abi_tag_sections, 2601130812Smarcel &osabi); 2602130812Smarcel if (osabi == GDB_OSABI_UNKNOWN) 2603130812Smarcel { 2604130812Smarcel /* Assume APCS ABI. */ 2605130812Smarcel osabi = GDB_OSABI_ARM_APCS; 2606130812Smarcel } 2607130812Smarcel break; 2608130812Smarcel 2609130812Smarcel case ELFOSABI_FREEBSD: 2610130812Smarcel osabi = GDB_OSABI_FREEBSD_ELF; 2611130812Smarcel break; 2612130812Smarcel 2613130812Smarcel case ELFOSABI_NETBSD: 2614130812Smarcel osabi = GDB_OSABI_NETBSD_ELF; 2615130812Smarcel break; 2616130812Smarcel 2617130812Smarcel case ELFOSABI_LINUX: 2618130812Smarcel osabi = GDB_OSABI_LINUX; 2619130812Smarcel break; 2620130812Smarcel } 2621130812Smarcel 2622130812Smarcel return osabi; 2623130812Smarcel} 2624130812Smarcel 2625130812Smarcel 2626130812Smarcel/* Initialize the current architecture based on INFO. If possible, 2627130812Smarcel re-use an architecture from ARCHES, which is a list of 2628130812Smarcel architectures already created during this debugging session. 2629130812Smarcel 2630130812Smarcel Called e.g. at program startup, when reading a core file, and when 2631130812Smarcel reading a binary file. */ 2632130812Smarcel 2633130812Smarcelstatic struct gdbarch * 2634130812Smarcelarm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2635130812Smarcel{ 2636130812Smarcel struct gdbarch_tdep *tdep; 2637130812Smarcel struct gdbarch *gdbarch; 2638130812Smarcel 2639130812Smarcel /* Try to deterimine the ABI of the object we are loading. */ 2640130812Smarcel 2641130812Smarcel if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) 2642130812Smarcel { 2643130812Smarcel switch (bfd_get_flavour (info.abfd)) 2644130812Smarcel { 2645130812Smarcel case bfd_target_aout_flavour: 2646130812Smarcel /* Assume it's an old APCS-style ABI. */ 2647130812Smarcel info.osabi = GDB_OSABI_ARM_APCS; 2648130812Smarcel break; 2649130812Smarcel 2650130812Smarcel case bfd_target_coff_flavour: 2651130812Smarcel /* Assume it's an old APCS-style ABI. */ 2652130812Smarcel /* XXX WinCE? */ 2653130812Smarcel info.osabi = GDB_OSABI_ARM_APCS; 2654130812Smarcel break; 2655130812Smarcel 2656130812Smarcel default: 2657130812Smarcel /* Leave it as "unknown". */ 2658130812Smarcel break; 2659130812Smarcel } 2660130812Smarcel } 2661130812Smarcel 2662130812Smarcel /* If there is already a candidate, use it. */ 2663130812Smarcel arches = gdbarch_list_lookup_by_info (arches, &info); 2664130812Smarcel if (arches != NULL) 2665130812Smarcel return arches->gdbarch; 2666130812Smarcel 2667130812Smarcel tdep = xmalloc (sizeof (struct gdbarch_tdep)); 2668130812Smarcel gdbarch = gdbarch_alloc (&info, tdep); 2669130812Smarcel 2670130812Smarcel /* We used to default to FPA for generic ARM, but almost nobody uses that 2671130812Smarcel now, and we now provide a way for the user to force the model. So 2672130812Smarcel default to the most useful variant. */ 2673130812Smarcel tdep->fp_model = ARM_FLOAT_SOFT_FPA; 2674130812Smarcel 2675130812Smarcel /* Breakpoints. */ 2676130812Smarcel switch (info.byte_order) 2677130812Smarcel { 2678130812Smarcel case BFD_ENDIAN_BIG: 2679130812Smarcel tdep->arm_breakpoint = arm_default_arm_be_breakpoint; 2680130812Smarcel tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); 2681130812Smarcel tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; 2682130812Smarcel tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); 2683130812Smarcel 2684130812Smarcel break; 2685130812Smarcel 2686130812Smarcel case BFD_ENDIAN_LITTLE: 2687130812Smarcel tdep->arm_breakpoint = arm_default_arm_le_breakpoint; 2688130812Smarcel tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); 2689130812Smarcel tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; 2690130812Smarcel tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); 2691130812Smarcel 2692130812Smarcel break; 2693130812Smarcel 2694130812Smarcel default: 2695130812Smarcel internal_error (__FILE__, __LINE__, 2696130812Smarcel "arm_gdbarch_init: bad byte order for float format"); 2697130812Smarcel } 2698130812Smarcel 2699130812Smarcel /* On ARM targets char defaults to unsigned. */ 2700130812Smarcel set_gdbarch_char_signed (gdbarch, 0); 2701130812Smarcel 2702130812Smarcel /* This should be low enough for everything. */ 2703130812Smarcel tdep->lowest_pc = 0x20; 2704130812Smarcel tdep->jb_pc = -1; /* Longjump support not enabled by default. */ 2705130812Smarcel 2706130812Smarcel set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words); 2707130812Smarcel set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); 2708130812Smarcel 2709130812Smarcel set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); 2710130812Smarcel 2711130812Smarcel set_gdbarch_write_pc (gdbarch, arm_write_pc); 2712130812Smarcel 2713130812Smarcel /* Frame handling. */ 2714130812Smarcel set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); 2715130812Smarcel set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); 2716130812Smarcel set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); 2717130812Smarcel 2718130812Smarcel set_gdbarch_deprecated_frameless_function_invocation (gdbarch, arm_frameless_function_invocation); 2719130812Smarcel 2720130812Smarcel frame_base_set_default (gdbarch, &arm_normal_base); 2721130812Smarcel 2722130812Smarcel /* Address manipulation. */ 2723130812Smarcel set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); 2724130812Smarcel set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); 2725130812Smarcel 2726130812Smarcel /* Advance PC across function entry code. */ 2727130812Smarcel set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); 2728130812Smarcel 2729130812Smarcel /* Get the PC when a frame might not be available. */ 2730130812Smarcel set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); 2731130812Smarcel 2732130812Smarcel /* The stack grows downward. */ 2733130812Smarcel set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2734130812Smarcel 2735130812Smarcel /* Breakpoint manipulation. */ 2736130812Smarcel set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); 2737130812Smarcel 2738130812Smarcel /* Information about registers, etc. */ 2739130812Smarcel set_gdbarch_print_float_info (gdbarch, arm_print_float_info); 2740130812Smarcel set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ 2741130812Smarcel set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); 2742130812Smarcel set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); 2743130812Smarcel set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); 2744130812Smarcel set_gdbarch_deprecated_register_bytes (gdbarch, 2745130812Smarcel (NUM_GREGS * INT_REGISTER_SIZE 2746130812Smarcel + NUM_FREGS * FP_REGISTER_SIZE 2747130812Smarcel + NUM_SREGS * STATUS_REGISTER_SIZE)); 2748130812Smarcel set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); 2749130812Smarcel set_gdbarch_register_type (gdbarch, arm_register_type); 2750130812Smarcel 2751130812Smarcel /* Internal <-> external register number maps. */ 2752130812Smarcel set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); 2753130812Smarcel 2754130812Smarcel /* Integer registers are 4 bytes. */ 2755130812Smarcel set_gdbarch_deprecated_register_size (gdbarch, 4); 2756130812Smarcel set_gdbarch_register_name (gdbarch, arm_register_name); 2757130812Smarcel 2758130812Smarcel /* Returning results. */ 2759130812Smarcel set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); 2760130812Smarcel set_gdbarch_store_return_value (gdbarch, arm_store_return_value); 2761130812Smarcel set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); 2762130812Smarcel set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); 2763130812Smarcel 2764130812Smarcel /* Single stepping. */ 2765130812Smarcel /* XXX For an RDI target we should ask the target if it can single-step. */ 2766130812Smarcel set_gdbarch_software_single_step (gdbarch, arm_software_single_step); 2767130812Smarcel 2768130812Smarcel /* Disassembly. */ 2769130812Smarcel set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); 2770130812Smarcel 2771130812Smarcel /* Minsymbol frobbing. */ 2772130812Smarcel set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); 2773130812Smarcel set_gdbarch_coff_make_msymbol_special (gdbarch, 2774130812Smarcel arm_coff_make_msymbol_special); 2775130812Smarcel 2776130812Smarcel /* Hook in the ABI-specific overrides, if they have been registered. */ 2777130812Smarcel gdbarch_init_osabi (info, gdbarch); 2778130812Smarcel 2779130812Smarcel /* Add some default predicates. */ 2780130812Smarcel frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); 2781130812Smarcel frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); 2782130812Smarcel 2783130812Smarcel /* Now we have tuned the configuration, set a few final things, 2784130812Smarcel based on what the OS ABI has told us. */ 2785130812Smarcel 2786130812Smarcel if (tdep->jb_pc >= 0) 2787130812Smarcel set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); 2788130812Smarcel 2789130812Smarcel /* Floating point sizes and format. */ 2790130812Smarcel switch (info.byte_order) 2791130812Smarcel { 2792130812Smarcel case BFD_ENDIAN_BIG: 2793130812Smarcel set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); 2794130812Smarcel set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); 2795130812Smarcel set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); 2796130812Smarcel 2797130812Smarcel break; 2798130812Smarcel 2799130812Smarcel case BFD_ENDIAN_LITTLE: 2800130812Smarcel set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); 2801130812Smarcel arm_set_fp (gdbarch); 2802130812Smarcel break; 2803130812Smarcel 2804130812Smarcel default: 2805130812Smarcel internal_error (__FILE__, __LINE__, 2806130812Smarcel "arm_gdbarch_init: bad byte order for float format"); 2807130812Smarcel } 2808130812Smarcel 2809130812Smarcel return gdbarch; 2810130812Smarcel} 2811130812Smarcel 2812130812Smarcelstatic void 2813130812Smarcelarm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 2814130812Smarcel{ 2815130812Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2816130812Smarcel 2817130812Smarcel if (tdep == NULL) 2818130812Smarcel return; 2819130812Smarcel 2820130812Smarcel fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", 2821130812Smarcel (unsigned long) tdep->lowest_pc); 2822130812Smarcel} 2823130812Smarcel 2824130812Smarcelstatic void 2825130812Smarcelarm_init_abi_eabi_v1 (struct gdbarch_info info, 2826130812Smarcel struct gdbarch *gdbarch) 2827130812Smarcel{ 2828130812Smarcel /* Place-holder. */ 2829130812Smarcel} 2830130812Smarcel 2831130812Smarcelstatic void 2832130812Smarcelarm_init_abi_eabi_v2 (struct gdbarch_info info, 2833130812Smarcel struct gdbarch *gdbarch) 2834130812Smarcel{ 2835130812Smarcel /* Place-holder. */ 2836130812Smarcel} 2837130812Smarcel 2838130812Smarcelstatic void 2839130812Smarcelarm_init_abi_apcs (struct gdbarch_info info, 2840130812Smarcel struct gdbarch *gdbarch) 2841130812Smarcel{ 2842130812Smarcel /* Place-holder. */ 2843130812Smarcel} 2844130812Smarcel 2845130812Smarcelextern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ 2846130812Smarcel 2847130812Smarcelvoid 2848130812Smarcel_initialize_arm_tdep (void) 2849130812Smarcel{ 2850130812Smarcel struct ui_file *stb; 2851130812Smarcel long length; 2852130812Smarcel struct cmd_list_element *new_set, *new_show; 2853130812Smarcel const char *setname; 2854130812Smarcel const char *setdesc; 2855130812Smarcel const char **regnames; 2856130812Smarcel int numregs, i, j; 2857130812Smarcel static char *helptext; 2858130812Smarcel 2859130812Smarcel gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); 2860130812Smarcel 2861130812Smarcel /* Register an ELF OS ABI sniffer for ARM binaries. */ 2862130812Smarcel gdbarch_register_osabi_sniffer (bfd_arch_arm, 2863130812Smarcel bfd_target_elf_flavour, 2864130812Smarcel arm_elf_osabi_sniffer); 2865130812Smarcel 2866130812Smarcel /* Register some ABI variants for embedded systems. */ 2867130812Smarcel gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, 2868130812Smarcel arm_init_abi_eabi_v1); 2869130812Smarcel gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, 2870130812Smarcel arm_init_abi_eabi_v2); 2871130812Smarcel gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, 2872130812Smarcel arm_init_abi_apcs); 2873130812Smarcel 2874130812Smarcel /* Get the number of possible sets of register names defined in opcodes. */ 2875130812Smarcel num_disassembly_options = get_arm_regname_num_options (); 2876130812Smarcel 2877130812Smarcel /* Add root prefix command for all "set arm"/"show arm" commands. */ 2878130812Smarcel add_prefix_cmd ("arm", no_class, set_arm_command, 2879130812Smarcel "Various ARM-specific commands.", 2880130812Smarcel &setarmcmdlist, "set arm ", 0, &setlist); 2881130812Smarcel 2882130812Smarcel add_prefix_cmd ("arm", no_class, show_arm_command, 2883130812Smarcel "Various ARM-specific commands.", 2884130812Smarcel &showarmcmdlist, "show arm ", 0, &showlist); 2885130812Smarcel 2886130812Smarcel /* Sync the opcode insn printer with our register viewer. */ 2887130812Smarcel parse_arm_disassembler_option ("reg-names-std"); 2888130812Smarcel 2889130812Smarcel /* Begin creating the help text. */ 2890130812Smarcel stb = mem_fileopen (); 2891130812Smarcel fprintf_unfiltered (stb, "Set the disassembly style.\n" 2892130812Smarcel "The valid values are:\n"); 2893130812Smarcel 2894130812Smarcel /* Initialize the array that will be passed to add_set_enum_cmd(). */ 2895130812Smarcel valid_disassembly_styles 2896130812Smarcel = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); 2897130812Smarcel for (i = 0; i < num_disassembly_options; i++) 2898130812Smarcel { 2899130812Smarcel numregs = get_arm_regnames (i, &setname, &setdesc, ®names); 2900130812Smarcel valid_disassembly_styles[i] = setname; 2901130812Smarcel fprintf_unfiltered (stb, "%s - %s\n", setname, 2902130812Smarcel setdesc); 2903130812Smarcel /* Copy the default names (if found) and synchronize disassembler. */ 2904130812Smarcel if (!strcmp (setname, "std")) 2905130812Smarcel { 2906130812Smarcel disassembly_style = setname; 2907130812Smarcel current_option = i; 2908130812Smarcel for (j = 0; j < numregs; j++) 2909130812Smarcel arm_register_names[j] = (char *) regnames[j]; 2910130812Smarcel set_arm_regname_option (i); 2911130812Smarcel } 2912130812Smarcel } 2913130812Smarcel /* Mark the end of valid options. */ 2914130812Smarcel valid_disassembly_styles[num_disassembly_options] = NULL; 2915130812Smarcel 2916130812Smarcel /* Finish the creation of the help text. */ 2917130812Smarcel fprintf_unfiltered (stb, "The default is \"std\"."); 2918130812Smarcel helptext = ui_file_xstrdup (stb, &length); 2919130812Smarcel ui_file_delete (stb); 2920130812Smarcel 2921130812Smarcel /* Add the deprecated disassembly-flavor command. */ 2922130812Smarcel new_set = add_set_enum_cmd ("disassembly-flavor", no_class, 2923130812Smarcel valid_disassembly_styles, 2924130812Smarcel &disassembly_style, 2925130812Smarcel helptext, 2926130812Smarcel &setlist); 2927130812Smarcel set_cmd_sfunc (new_set, set_disassembly_style_sfunc); 2928130812Smarcel deprecate_cmd (new_set, "set arm disassembly"); 2929130812Smarcel deprecate_cmd (add_show_from_set (new_set, &showlist), 2930130812Smarcel "show arm disassembly"); 2931130812Smarcel 2932130812Smarcel /* And now add the new interface. */ 2933130812Smarcel new_set = add_set_enum_cmd ("disassembler", no_class, 2934130812Smarcel valid_disassembly_styles, &disassembly_style, 2935130812Smarcel helptext, &setarmcmdlist); 2936130812Smarcel 2937130812Smarcel set_cmd_sfunc (new_set, set_disassembly_style_sfunc); 2938130812Smarcel add_show_from_set (new_set, &showarmcmdlist); 2939130812Smarcel 2940130812Smarcel add_setshow_cmd_full ("apcs32", no_class, 2941130812Smarcel var_boolean, (char *) &arm_apcs_32, 2942130812Smarcel "Set usage of ARM 32-bit mode.", 2943130812Smarcel "Show usage of ARM 32-bit mode.", 2944130812Smarcel NULL, NULL, 2945130812Smarcel &setlist, &showlist, &new_set, &new_show); 2946130812Smarcel deprecate_cmd (new_set, "set arm apcs32"); 2947130812Smarcel deprecate_cmd (new_show, "show arm apcs32"); 2948130812Smarcel 2949130812Smarcel add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, 2950130812Smarcel "Set usage of ARM 32-bit mode. " 2951130812Smarcel "When off, a 26-bit PC will be used.", 2952130812Smarcel "Show usage of ARM 32-bit mode. " 2953130812Smarcel "When off, a 26-bit PC will be used.", 2954130812Smarcel NULL, NULL, 2955130812Smarcel &setarmcmdlist, &showarmcmdlist); 2956130812Smarcel 2957130812Smarcel /* Add a command to allow the user to force the FPU model. */ 2958130812Smarcel new_set = add_set_enum_cmd 2959130812Smarcel ("fpu", no_class, fp_model_strings, ¤t_fp_model, 2960130812Smarcel "Set the floating point type.\n" 2961130812Smarcel "auto - Determine the FP typefrom the OS-ABI.\n" 2962130812Smarcel "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" 2963130812Smarcel "fpa - FPA co-processor (GCC compiled).\n" 2964130812Smarcel "softvfp - Software FP with pure-endian doubles.\n" 2965130812Smarcel "vfp - VFP co-processor.", 2966130812Smarcel &setarmcmdlist); 2967130812Smarcel set_cmd_sfunc (new_set, set_fp_model_sfunc); 2968130812Smarcel set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model); 2969130812Smarcel 2970130812Smarcel /* Add the deprecated "othernames" command. */ 2971130812Smarcel deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, 2972130812Smarcel "Switch to the next set of register names."), 2973130812Smarcel "set arm disassembly"); 2974130812Smarcel 2975130812Smarcel /* Debugging flag. */ 2976130812Smarcel add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, 2977130812Smarcel "Set ARM debugging. " 2978130812Smarcel "When on, arm-specific debugging is enabled.", 2979130812Smarcel "Show ARM debugging. " 2980130812Smarcel "When on, arm-specific debugging is enabled.", 2981130812Smarcel NULL, NULL, 2982130812Smarcel &setdebuglist, &showdebuglist); 2983130812Smarcel} 2984