rtl.texi revision 117395
1@c Copyright (C) 1988, 1989, 1992, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003 2@c Free Software Foundation, Inc. 3@c This is part of the GCC manual. 4@c For copying conditions, see the file gcc.texi. 5 6@node RTL 7@chapter RTL Representation 8@cindex RTL representation 9@cindex representation of RTL 10@cindex Register Transfer Language (RTL) 11 12Most of the work of the compiler is done on an intermediate representation 13called register transfer language. In this language, the instructions to be 14output are described, pretty much one by one, in an algebraic form that 15describes what the instruction does. 16 17RTL is inspired by Lisp lists. It has both an internal form, made up of 18structures that point at other structures, and a textual form that is used 19in the machine description and in printed debugging dumps. The textual 20form uses nested parentheses to indicate the pointers in the internal form. 21 22@menu 23* RTL Objects:: Expressions vs vectors vs strings vs integers. 24* RTL Classes:: Categories of RTL expression objects, and their structure. 25* Accessors:: Macros to access expression operands or vector elts. 26* Flags:: Other flags in an RTL expression. 27* Machine Modes:: Describing the size and format of a datum. 28* Constants:: Expressions with constant values. 29* Regs and Memory:: Expressions representing register contents or memory. 30* Arithmetic:: Expressions representing arithmetic on other expressions. 31* Comparisons:: Expressions representing comparison of expressions. 32* Bit-Fields:: Expressions representing bit-fields in memory or reg. 33* Vector Operations:: Expressions involving vector datatypes. 34* Conversions:: Extending, truncating, floating or fixing. 35* RTL Declarations:: Declaring volatility, constancy, etc. 36* Side Effects:: Expressions for storing in registers, etc. 37* Incdec:: Embedded side-effects for autoincrement addressing. 38* Assembler:: Representing @code{asm} with operands. 39* Insns:: Expression types for entire insns. 40* Calls:: RTL representation of function call insns. 41* Sharing:: Some expressions are unique; others *must* be copied. 42* Reading RTL:: Reading textual RTL from a file. 43@end menu 44 45@node RTL Objects 46@section RTL Object Types 47@cindex RTL object types 48 49@cindex RTL integers 50@cindex RTL strings 51@cindex RTL vectors 52@cindex RTL expression 53@cindex RTX (See RTL) 54RTL uses five kinds of objects: expressions, integers, wide integers, 55strings and vectors. Expressions are the most important ones. An RTL 56expression (``RTX'', for short) is a C structure, but it is usually 57referred to with a pointer; a type that is given the typedef name 58@code{rtx}. 59 60An integer is simply an @code{int}; their written form uses decimal 61digits. A wide integer is an integral object whose type is 62@code{HOST_WIDE_INT}; their written form uses decimal digits. 63 64A string is a sequence of characters. In core it is represented as a 65@code{char *} in usual C fashion, and it is written in C syntax as well. 66However, strings in RTL may never be null. If you write an empty string in 67a machine description, it is represented in core as a null pointer rather 68than as a pointer to a null character. In certain contexts, these null 69pointers instead of strings are valid. Within RTL code, strings are most 70commonly found inside @code{symbol_ref} expressions, but they appear in 71other contexts in the RTL expressions that make up machine descriptions. 72 73In a machine description, strings are normally written with double 74quotes, as you would in C. However, strings in machine descriptions may 75extend over many lines, which is invalid C, and adjacent string 76constants are not concatenated as they are in C. Any string constant 77may be surrounded with a single set of parentheses. Sometimes this 78makes the machine description easier to read. 79 80There is also a special syntax for strings, which can be useful when C 81code is embedded in a machine description. Wherever a string can 82appear, it is also valid to write a C-style brace block. The entire 83brace block, including the outermost pair of braces, is considered to be 84the string constant. Double quote characters inside the braces are not 85special. Therefore, if you write string constants in the C code, you 86need not escape each quote character with a backslash. 87 88A vector contains an arbitrary number of pointers to expressions. The 89number of elements in the vector is explicitly present in the vector. 90The written form of a vector consists of square brackets 91(@samp{[@dots{}]}) surrounding the elements, in sequence and with 92whitespace separating them. Vectors of length zero are not created; 93null pointers are used instead. 94 95@cindex expression codes 96@cindex codes, RTL expression 97@findex GET_CODE 98@findex PUT_CODE 99Expressions are classified by @dfn{expression codes} (also called RTX 100codes). The expression code is a name defined in @file{rtl.def}, which is 101also (in upper case) a C enumeration constant. The possible expression 102codes and their meanings are machine-independent. The code of an RTX can 103be extracted with the macro @code{GET_CODE (@var{x})} and altered with 104@code{PUT_CODE (@var{x}, @var{newcode})}. 105 106The expression code determines how many operands the expression contains, 107and what kinds of objects they are. In RTL, unlike Lisp, you cannot tell 108by looking at an operand what kind of object it is. Instead, you must know 109from its context---from the expression code of the containing expression. 110For example, in an expression of code @code{subreg}, the first operand is 111to be regarded as an expression and the second operand as an integer. In 112an expression of code @code{plus}, there are two operands, both of which 113are to be regarded as expressions. In a @code{symbol_ref} expression, 114there is one operand, which is to be regarded as a string. 115 116Expressions are written as parentheses containing the name of the 117expression type, its flags and machine mode if any, and then the operands 118of the expression (separated by spaces). 119 120Expression code names in the @samp{md} file are written in lower case, 121but when they appear in C code they are written in upper case. In this 122manual, they are shown as follows: @code{const_int}. 123 124@cindex (nil) 125@cindex nil 126In a few contexts a null pointer is valid where an expression is normally 127wanted. The written form of this is @code{(nil)}. 128 129@node RTL Classes 130@section RTL Classes and Formats 131@cindex RTL classes 132@cindex classes of RTX codes 133@cindex RTX codes, classes of 134@findex GET_RTX_CLASS 135 136The various expression codes are divided into several @dfn{classes}, 137which are represented by single characters. You can determine the class 138of an RTX code with the macro @code{GET_RTX_CLASS (@var{code})}. 139Currently, @file{rtx.def} defines these classes: 140 141@table @code 142@item o 143An RTX code that represents an actual object, such as a register 144(@code{REG}) or a memory location (@code{MEM}, @code{SYMBOL_REF}). 145Constants and basic transforms on objects (@code{ADDRESSOF}, 146@code{HIGH}, @code{LO_SUM}) are also included. Note that @code{SUBREG} 147and @code{STRICT_LOW_PART} are not in this class, but in class @code{x}. 148 149@item < 150An RTX code for a comparison, such as @code{NE} or @code{LT}. 151 152@item 1 153An RTX code for a unary arithmetic operation, such as @code{NEG}, 154@code{NOT}, or @code{ABS}. This category also includes value extension 155(sign or zero) and conversions between integer and floating point. 156 157@item c 158An RTX code for a commutative binary operation, such as @code{PLUS} or 159@code{AND}. @code{NE} and @code{EQ} are comparisons, so they have class 160@code{<}. 161 162@item 2 163An RTX code for a non-commutative binary operation, such as @code{MINUS}, 164@code{DIV}, or @code{ASHIFTRT}. 165 166@item b 167An RTX code for a bit-field operation. Currently only 168@code{ZERO_EXTRACT} and @code{SIGN_EXTRACT}. These have three inputs 169and are lvalues (so they can be used for insertion as well). 170@xref{Bit-Fields}. 171 172@item 3 173An RTX code for other three input operations. Currently only 174@code{IF_THEN_ELSE}. 175 176@item i 177An RTX code for an entire instruction: @code{INSN}, @code{JUMP_INSN}, and 178@code{CALL_INSN}. @xref{Insns}. 179 180@item m 181An RTX code for something that matches in insns, such as 182@code{MATCH_DUP}. These only occur in machine descriptions. 183 184@item a 185An RTX code for an auto-increment addressing mode, such as 186@code{POST_INC}. 187 188@item x 189All other RTX codes. This category includes the remaining codes used 190only in machine descriptions (@code{DEFINE_*}, etc.). It also includes 191all the codes describing side effects (@code{SET}, @code{USE}, 192@code{CLOBBER}, etc.) and the non-insns that may appear on an insn 193chain, such as @code{NOTE}, @code{BARRIER}, and @code{CODE_LABEL}. 194@end table 195 196@cindex RTL format 197For each expression code, @file{rtl.def} specifies the number of 198contained objects and their kinds using a sequence of characters 199called the @dfn{format} of the expression code. For example, 200the format of @code{subreg} is @samp{ei}. 201 202@cindex RTL format characters 203These are the most commonly used format characters: 204 205@table @code 206@item e 207An expression (actually a pointer to an expression). 208 209@item i 210An integer. 211 212@item w 213A wide integer. 214 215@item s 216A string. 217 218@item E 219A vector of expressions. 220@end table 221 222A few other format characters are used occasionally: 223 224@table @code 225@item u 226@samp{u} is equivalent to @samp{e} except that it is printed differently 227in debugging dumps. It is used for pointers to insns. 228 229@item n 230@samp{n} is equivalent to @samp{i} except that it is printed differently 231in debugging dumps. It is used for the line number or code number of a 232@code{note} insn. 233 234@item S 235@samp{S} indicates a string which is optional. In the RTL objects in 236core, @samp{S} is equivalent to @samp{s}, but when the object is read, 237from an @samp{md} file, the string value of this operand may be omitted. 238An omitted string is taken to be the null string. 239 240@item V 241@samp{V} indicates a vector which is optional. In the RTL objects in 242core, @samp{V} is equivalent to @samp{E}, but when the object is read 243from an @samp{md} file, the vector value of this operand may be omitted. 244An omitted vector is effectively the same as a vector of no elements. 245 246@item B 247@samp{B} indicates a pointer to basic block structure. 248 249@item 0 250@samp{0} means a slot whose contents do not fit any normal category. 251@samp{0} slots are not printed at all in dumps, and are often used in 252special ways by small parts of the compiler. 253@end table 254 255There are macros to get the number of operands and the format 256of an expression code: 257 258@table @code 259@findex GET_RTX_LENGTH 260@item GET_RTX_LENGTH (@var{code}) 261Number of operands of an RTX of code @var{code}. 262 263@findex GET_RTX_FORMAT 264@item GET_RTX_FORMAT (@var{code}) 265The format of an RTX of code @var{code}, as a C string. 266@end table 267 268Some classes of RTX codes always have the same format. For example, it 269is safe to assume that all comparison operations have format @code{ee}. 270 271@table @code 272@item 1 273All codes of this class have format @code{e}. 274 275@item < 276@itemx c 277@itemx 2 278All codes of these classes have format @code{ee}. 279 280@item b 281@itemx 3 282All codes of these classes have format @code{eee}. 283 284@item i 285All codes of this class have formats that begin with @code{iuueiee}. 286@xref{Insns}. Note that not all RTL objects linked onto an insn chain 287are of class @code{i}. 288 289@item o 290@itemx m 291@itemx x 292You can make no assumptions about the format of these codes. 293@end table 294 295@node Accessors 296@section Access to Operands 297@cindex accessors 298@cindex access to operands 299@cindex operand access 300 301@findex XEXP 302@findex XINT 303@findex XWINT 304@findex XSTR 305Operands of expressions are accessed using the macros @code{XEXP}, 306@code{XINT}, @code{XWINT} and @code{XSTR}. Each of these macros takes 307two arguments: an expression-pointer (RTX) and an operand number 308(counting from zero). Thus, 309 310@example 311XEXP (@var{x}, 2) 312@end example 313 314@noindent 315accesses operand 2 of expression @var{x}, as an expression. 316 317@example 318XINT (@var{x}, 2) 319@end example 320 321@noindent 322accesses the same operand as an integer. @code{XSTR}, used in the same 323fashion, would access it as a string. 324 325Any operand can be accessed as an integer, as an expression or as a string. 326You must choose the correct method of access for the kind of value actually 327stored in the operand. You would do this based on the expression code of 328the containing expression. That is also how you would know how many 329operands there are. 330 331For example, if @var{x} is a @code{subreg} expression, you know that it has 332two operands which can be correctly accessed as @code{XEXP (@var{x}, 0)} 333and @code{XINT (@var{x}, 1)}. If you did @code{XINT (@var{x}, 0)}, you 334would get the address of the expression operand but cast as an integer; 335that might occasionally be useful, but it would be cleaner to write 336@code{(int) XEXP (@var{x}, 0)}. @code{XEXP (@var{x}, 1)} would also 337compile without error, and would return the second, integer operand cast as 338an expression pointer, which would probably result in a crash when 339accessed. Nothing stops you from writing @code{XEXP (@var{x}, 28)} either, 340but this will access memory past the end of the expression with 341unpredictable results. 342 343Access to operands which are vectors is more complicated. You can use the 344macro @code{XVEC} to get the vector-pointer itself, or the macros 345@code{XVECEXP} and @code{XVECLEN} to access the elements and length of a 346vector. 347 348@table @code 349@findex XVEC 350@item XVEC (@var{exp}, @var{idx}) 351Access the vector-pointer which is operand number @var{idx} in @var{exp}. 352 353@findex XVECLEN 354@item XVECLEN (@var{exp}, @var{idx}) 355Access the length (number of elements) in the vector which is 356in operand number @var{idx} in @var{exp}. This value is an @code{int}. 357 358@findex XVECEXP 359@item XVECEXP (@var{exp}, @var{idx}, @var{eltnum}) 360Access element number @var{eltnum} in the vector which is 361in operand number @var{idx} in @var{exp}. This value is an RTX@. 362 363It is up to you to make sure that @var{eltnum} is not negative 364and is less than @code{XVECLEN (@var{exp}, @var{idx})}. 365@end table 366 367All the macros defined in this section expand into lvalues and therefore 368can be used to assign the operands, lengths and vector elements as well as 369to access them. 370 371@node Flags 372@section Flags in an RTL Expression 373@cindex flags in RTL expression 374 375RTL expressions contain several flags (one-bit bit-fields) 376that are used in certain types of expression. Most often they 377are accessed with the following macros, which expand into lvalues. 378 379@table @code 380@findex CONSTANT_POOL_ADDRESS_P 381@cindex @code{symbol_ref} and @samp{/u} 382@cindex @code{unchanging}, in @code{symbol_ref} 383@item CONSTANT_POOL_ADDRESS_P (@var{x}) 384Nonzero in a @code{symbol_ref} if it refers to part of the current 385function's constant pool. For most targets these addresses are in a 386@code{.rodata} section entirely separate from the function, but for 387some targets the addresses are close to the beginning of the function. 388In either case GCC assumes these addresses can be addressed directly, 389perhaps with the help of base registers. 390Stored in the @code{unchanging} field and printed as @samp{/u}. 391 392@findex CONST_OR_PURE_CALL_P 393@cindex @code{call_insn} and @samp{/u} 394@cindex @code{unchanging}, in @code{call_insn} 395@item CONST_OR_PURE_CALL_P (@var{x}) 396In a @code{call_insn}, @code{note}, or an @code{expr_list} for notes, 397indicates that the insn represents a call to a const or pure function. 398Stored in the @code{unchanging} field and printed as @samp{/u}. 399 400@findex INSN_ANNULLED_BRANCH_P 401@cindex @code{jump_insn} and @samp{/u} 402@cindex @code{call_insn} and @samp{/u} 403@cindex @code{insn} and @samp{/u} 404@cindex @code{unchanging}, in @code{jump_insn}, @code{call_insn} and @code{insn} 405@item INSN_ANNULLED_BRANCH_P (@var{x}) 406In a @code{jump_insn}, @code{call_insn}, or @code{insn} indicates 407that the branch is an annulling one. See the discussion under 408@code{sequence} below. Stored in the @code{unchanging} field and 409printed as @samp{/u}. 410 411@findex INSN_DEAD_CODE_P 412@cindex @code{insn} and @samp{/s} 413@cindex @code{in_struct}, in @code{insn} 414@item INSN_DEAD_CODE_P (@var{x}) 415In an @code{insn} during the dead-code elimination pass, nonzero if the 416insn is dead. 417Stored in the @code{in_struct} field and printed as @samp{/s}. 418 419@findex INSN_DELETED_P 420@cindex @code{insn} and @samp{/v} 421@cindex @code{call_insn} and @samp{/v} 422@cindex @code{jump_insn} and @samp{/v} 423@cindex @code{code_label} and @samp{/v} 424@cindex @code{barrier} and @samp{/v} 425@cindex @code{note} and @samp{/v} 426@cindex @code{volatil}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, @code{barrier}, and @code{note} 427@item INSN_DELETED_P (@var{x}) 428In an @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, 429@code{barrier}, or @code{note}, 430nonzero if the insn has been deleted. Stored in the 431@code{volatil} field and printed as @samp{/v}. 432 433@findex INSN_FROM_TARGET_P 434@cindex @code{insn} and @samp{/s} 435@cindex @code{jump_insn} and @samp{/s} 436@cindex @code{call_insn} and @samp{/s} 437@cindex @code{in_struct}, in @code{insn} and @code{jump_insn} and @code{call_insn} 438@item INSN_FROM_TARGET_P (@var{x}) 439In an @code{insn} or @code{jump_insn} or @code{call_insn} in a delay 440slot of a branch, indicates that the insn 441is from the target of the branch. If the branch insn has 442@code{INSN_ANNULLED_BRANCH_P} set, this insn will only be executed if 443the branch is taken. For annulled branches with 444@code{INSN_FROM_TARGET_P} clear, the insn will be executed only if the 445branch is not taken. When @code{INSN_ANNULLED_BRANCH_P} is not set, 446this insn will always be executed. Stored in the @code{in_struct} 447field and printed as @samp{/s}. 448 449@findex LABEL_OUTSIDE_LOOP_P 450@cindex @code{label_ref} and @samp{/s} 451@cindex @code{in_struct}, in @code{label_ref} 452@item LABEL_OUTSIDE_LOOP_P (@var{x}) 453In @code{label_ref} expressions, nonzero if this is a reference to a 454label that is outside the innermost loop containing the reference to the 455label. Stored in the @code{in_struct} field and printed as @samp{/s}. 456 457@findex LABEL_PRESERVE_P 458@cindex @code{code_label} and @samp{/i} 459@cindex @code{note} and @samp{/i} 460@cindex @code{in_struct}, in @code{code_label} and @code{note} 461@item LABEL_PRESERVE_P (@var{x}) 462In a @code{code_label} or @code{note}, indicates that the label is referenced by 463code or data not visible to the RTL of a given function. 464Labels referenced by a non-local goto will have this bit set. Stored 465in the @code{in_struct} field and printed as @samp{/s}. 466 467@findex LABEL_REF_NONLOCAL_P 468@cindex @code{label_ref} and @samp{/v} 469@cindex @code{reg_label} and @samp{/v} 470@cindex @code{volatil}, in @code{label_ref} and @code{reg_label} 471@item LABEL_REF_NONLOCAL_P (@var{x}) 472In @code{label_ref} and @code{reg_label} expressions, nonzero if this is 473a reference to a non-local label. 474Stored in the @code{volatil} field and printed as @samp{/v}. 475 476@findex MEM_IN_STRUCT_P 477@cindex @code{mem} and @samp{/s} 478@cindex @code{in_struct}, in @code{mem} 479@item MEM_IN_STRUCT_P (@var{x}) 480In @code{mem} expressions, nonzero for reference to an entire structure, 481union or array, or to a component of one. Zero for references to a 482scalar variable or through a pointer to a scalar. If both this flag and 483@code{MEM_SCALAR_P} are clear, then we don't know whether this @code{mem} 484is in a structure or not. Both flags should never be simultaneously set. 485Stored in the @code{in_struct} field and printed as @samp{/s}. 486 487@findex MEM_KEEP_ALIAS_SET_P 488@cindex @code{mem} and @samp{/j} 489@cindex @code{jump}, in @code{mem} 490@item MEM_KEEP_ALIAS_SET_P (@var{x}) 491In @code{mem} expressions, 1 if we should keep the alias set for this 492mem unchanged when we access a component. Set to 1, for example, when we 493are already in a non-addressable component of an aggregate. 494Stored in the @code{jump} field and printed as @samp{/j}. 495 496@findex MEM_SCALAR_P 497@cindex @code{mem} and @samp{/f} 498@cindex @code{frame_related}, in @code{mem} 499@item MEM_SCALAR_P (@var{x}) 500In @code{mem} expressions, nonzero for reference to a scalar known not 501to be a member of a structure, union, or array. Zero for such 502references and for indirections through pointers, even pointers pointing 503to scalar types. If both this flag and @code{MEM_IN_STRUCT_P} are clear, 504then we don't know whether this @code{mem} is in a structure or not. 505Both flags should never be simultaneously set. 506Stored in the @code{frame_related} field and printed as @samp{/f}. 507 508@findex MEM_VOLATILE_P 509@cindex @code{mem} and @samp{/v} 510@cindex @code{asm_input} and @samp{/v} 511@cindex @code{asm_operands} and @samp{/v} 512@cindex @code{volatil}, in @code{mem}, @code{asm_operands}, and @code{asm_input} 513@item MEM_VOLATILE_P (@var{x}) 514In @code{mem}, @code{asm_operands}, and @code{asm_input} expressions, 515nonzero for volatile memory references. 516Stored in the @code{volatil} field and printed as @samp{/v}. 517 518@findex REG_FUNCTION_VALUE_P 519@cindex @code{reg} and @samp{/i} 520@cindex @code{integrated}, in @code{reg} 521@item REG_FUNCTION_VALUE_P (@var{x}) 522Nonzero in a @code{reg} if it is the place in which this function's 523value is going to be returned. (This happens only in a hard 524register.) Stored in the @code{integrated} field and printed as 525@samp{/i}. 526 527@findex REG_LOOP_TEST_P 528@cindex @code{reg} and @samp{/s} 529@cindex @code{in_struct}, in @code{reg} 530@item REG_LOOP_TEST_P (@var{x}) 531In @code{reg} expressions, nonzero if this register's entire life is 532contained in the exit test code for some loop. Stored in the 533@code{in_struct} field and printed as @samp{/s}. 534 535@findex REG_POINTER 536@cindex @code{reg} and @samp{/f} 537@cindex @code{frame_related}, in @code{reg} 538@item REG_POINTER (@var{x}) 539Nonzero in a @code{reg} if the register holds a pointer. Stored in the 540@code{frame_related} field and printed as @samp{/f}. 541 542@findex REG_USERVAR_P 543@cindex @code{reg} and @samp{/v} 544@cindex @code{volatil}, in @code{reg} 545@item REG_USERVAR_P (@var{x}) 546In a @code{reg}, nonzero if it corresponds to a variable present in 547the user's source code. Zero for temporaries generated internally by 548the compiler. Stored in the @code{volatil} field and printed as 549@samp{/v}. 550 551The same hard register may be used also for collecting the values of 552functions called by this one, but @code{REG_FUNCTION_VALUE_P} is zero 553in this kind of use. 554 555@findex RTX_FRAME_RELATED_P 556@cindex @code{insn} and @samp{/f} 557@cindex @code{call_insn} and @samp{/f} 558@cindex @code{jump_insn} and @samp{/f} 559@cindex @code{barrier} and @samp{/f} 560@cindex @code{set} and @samp{/f} 561@cindex @code{frame_related}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, and @code{set} 562@item RTX_FRAME_RELATED_P (@var{x}) 563Nonzero in an @code{insn}, @code{call_insn}, @code{jump_insn}, 564@code{barrier}, or @code{set} which is part of a function prologue 565and sets the stack pointer, sets the frame pointer, or saves a register. 566This flag should also be set on an instruction that sets up a temporary 567register to use in place of the frame pointer. 568Stored in the @code{frame_related} field and printed as @samp{/f}. 569 570In particular, on RISC targets where there are limits on the sizes of 571immediate constants, it is sometimes impossible to reach the register 572save area directly from the stack pointer. In that case, a temporary 573register is used that is near enough to the register save area, and the 574Canonical Frame Address, i.e., DWARF2's logical frame pointer, register 575must (temporarily) be changed to be this temporary register. So, the 576instruction that sets this temporary register must be marked as 577@code{RTX_FRAME_RELATED_P}. 578 579If the marked instruction is overly complex (defined in terms of what 580@code{dwarf2out_frame_debug_expr} can handle), you will also have to 581create a @code{REG_FRAME_RELATED_EXPR} note and attach it to the 582instruction. This note should contain a simple expression of the 583computation performed by this instruction, i.e., one that 584@code{dwarf2out_frame_debug_expr} can handle. 585 586This flag is required for exception handling support on targets with RTL 587prologues. 588 589@findex RTX_INTEGRATED_P 590@cindex @code{insn} and @samp{/i} 591@cindex @code{call_insn} and @samp{/i} 592@cindex @code{jump_insn} and @samp{/i} 593@cindex @code{barrier} and @samp{/i} 594@cindex @code{code_label} and @samp{/i} 595@cindex @code{insn_list} and @samp{/i} 596@cindex @code{const} and @samp{/i} 597@cindex @code{note} and @samp{/i} 598@cindex @code{integrated}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, @code{code_label}, @code{insn_list}, @code{const}, and @code{note} 599@item RTX_INTEGRATED_P (@var{x}) 600Nonzero in an @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, 601@code{code_label}, @code{insn_list}, @code{const}, or @code{note} if it 602resulted from an in-line function call. 603Stored in the @code{integrated} field and printed as @samp{/i}. 604 605@findex RTX_UNCHANGING_P 606@cindex @code{reg} and @samp{/u} 607@cindex @code{mem} and @samp{/u} 608@cindex @code{concat} and @samp{/u} 609@cindex @code{unchanging}, in @code{reg} and @code{mem} 610@item RTX_UNCHANGING_P (@var{x}) 611Nonzero in a @code{reg}, @code{mem}, or @code{concat} if the memory 612is set at most once, 613anywhere. This does not mean that it is function invariant. 614Stored in the @code{unchanging} field and printed as @samp{/u}. 615 616@findex SCHED_GROUP_P 617@cindex @code{insn} and @samp{/s} 618@cindex @code{call_insn} and @samp{/s} 619@cindex @code{jump_insn} and @samp{/s} 620@cindex @code{in_struct}, in @code{insn}, @code{jump_insn} and @code{call_insn} 621@item SCHED_GROUP_P (@var{x}) 622During instruction scheduling, in an @code{insn}, @code{call_insn} or 623@code{jump_insn}, indicates that the 624previous insn must be scheduled together with this insn. This is used to 625ensure that certain groups of instructions will not be split up by the 626instruction scheduling pass, for example, @code{use} insns before 627a @code{call_insn} may not be separated from the @code{call_insn}. 628Stored in the @code{in_struct} field and printed as @samp{/s}. 629 630@findex SET_IS_RETURN_P 631@cindex @code{insn} and @samp{/j} 632@cindex @code{jump}, in @code{insn} 633@item SET_IS_RETURN_P (@var{x}) 634For a @code{set}, nonzero if it is for a return. 635Stored in the @code{jump} field and printed as @samp{/j}. 636 637@findex SIBLING_CALL_P 638@cindex @code{call_insn} and @samp{/j} 639@cindex @code{jump}, in @code{call_insn} 640@item SIBLING_CALL_P (@var{x}) 641For a @code{call_insn}, nonzero if the insn is a sibling call. 642Stored in the @code{jump} field and printed as @samp{/j}. 643 644@findex STRING_POOL_ADDRESS_P 645@cindex @code{symbol_ref} and @samp{/f} 646@cindex @code{frame_related}, in @code{symbol_ref} 647@item STRING_POOL_ADDRESS_P (@var{x}) 648For a @code{symbol_ref} expression, nonzero if it addresses this function's 649string constant pool. 650Stored in the @code{frame_related} field and printed as @samp{/f}. 651 652@findex SUBREG_PROMOTED_UNSIGNED_P 653@cindex @code{subreg} and @samp{/u} and @samp{/v} 654@cindex @code{unchanging}, in @code{subreg} 655@cindex @code{volatil}, in @code{subreg} 656@item SUBREG_PROMOTED_UNSIGNED_P (@var{x}) 657Returns a value greater then zero for a @code{subreg} that has 658@code{SUBREG_PROMOTED_VAR_P} nonzero if the object being referenced is kept 659zero-extended, zero if it is kept sign-extended, and less then zero if it is 660extended some other way via the @code{ptr_extend} instruction. 661Stored in the @code{unchanging} 662field and @code{volatil} field, printed as @samp{/u} and @samp{/v}. 663This macro may only be used to get the value it may not be used to change 664the value. Use @code{SUBREG_PROMOTED_UNSIGNED_SET} to change the value. 665 666@findex SUBREG_PROMOTED_UNSIGNED_SET 667@cindex @code{subreg} and @samp{/u} 668@cindex @code{unchanging}, in @code{subreg} 669@cindex @code{volatil}, in @code{subreg} 670@item SUBREG_PROMOTED_UNSIGNED_SET (@var{x}) 671Set the @code{unchanging} and @code{volatil} fields in a @code{subreg} 672to reflect zero, sign, or other extension. If @code{volatil} is 673zero, then @code{unchanging} as nonzero means zero extension and as 674zero means sign extension. If @code{volatil} is nonzero then some 675other type of extension was done via the @code{ptr_extend} instruction. 676 677@findex SUBREG_PROMOTED_VAR_P 678@cindex @code{subreg} and @samp{/s} 679@cindex @code{in_struct}, in @code{subreg} 680@item SUBREG_PROMOTED_VAR_P (@var{x}) 681Nonzero in a @code{subreg} if it was made when accessing an object that 682was promoted to a wider mode in accord with the @code{PROMOTED_MODE} machine 683description macro (@pxref{Storage Layout}). In this case, the mode of 684the @code{subreg} is the declared mode of the object and the mode of 685@code{SUBREG_REG} is the mode of the register that holds the object. 686Promoted variables are always either sign- or zero-extended to the wider 687mode on every assignment. Stored in the @code{in_struct} field and 688printed as @samp{/s}. 689 690@findex SYMBOL_REF_FLAG 691@cindex @code{symbol_ref} and @samp{/v} 692@cindex @code{volatil}, in @code{symbol_ref} 693@item SYMBOL_REF_FLAG (@var{x}) 694In a @code{symbol_ref}, this is used as a flag for machine-specific purposes. 695Stored in the @code{volatil} field and printed as @samp{/v}. 696 697@findex SYMBOL_REF_USED 698@cindex @code{used}, in @code{symbol_ref} 699@item SYMBOL_REF_USED (@var{x}) 700In a @code{symbol_ref}, indicates that @var{x} has been used. This is 701normally only used to ensure that @var{x} is only declared external 702once. Stored in the @code{used} field. 703 704@findex SYMBOL_REF_WEAK 705@cindex @code{symbol_ref} and @samp{/i} 706@cindex @code{integrated}, in @code{symbol_ref} 707@item SYMBOL_REF_WEAK (@var{x}) 708In a @code{symbol_ref}, indicates that @var{x} has been declared weak. 709Stored in the @code{integrated} field and printed as @samp{/i}. 710@end table 711 712These are the fields to which the above macros refer: 713 714@table @code 715@findex call 716@cindex @samp{/c} in RTL dump 717@item call 718This flag is currently unused. 719 720In an RTL dump, this flag is represented as @samp{/c}. 721 722@findex frame_related 723@cindex @samp{/f} in RTL dump 724@item frame_related 725In an @code{insn} or @code{set} expression, 1 means that it is part of 726a function prologue and sets the stack pointer, sets the frame pointer, 727saves a register, or sets up a temporary register to use in place of the 728frame pointer. 729 730In @code{reg} expressions, 1 means that the register holds a pointer. 731 732In @code{symbol_ref} expressions, 1 means that the reference addresses 733this function's string constant pool. 734 735In @code{mem} expressions, 1 means that the reference is to a scalar. 736 737In an RTL dump, this flag is represented as @samp{/f}. 738 739@findex in_struct 740@cindex @samp{/s} in RTL dump 741@item in_struct 742In @code{mem} expressions, it is 1 if the memory datum referred to is 743all or part of a structure or array; 0 if it is (or might be) a scalar 744variable. A reference through a C pointer has 0 because the pointer 745might point to a scalar variable. This information allows the compiler 746to determine something about possible cases of aliasing. 747 748In @code{reg} expressions, it is 1 if the register has its entire life 749contained within the test expression of some loop. 750 751In @code{subreg} expressions, 1 means that the @code{subreg} is accessing 752an object that has had its mode promoted from a wider mode. 753 754In @code{label_ref} expressions, 1 means that the referenced label is 755outside the innermost loop containing the insn in which the @code{label_ref} 756was found. 757 758In @code{code_label} expressions, it is 1 if the label may never be deleted. 759This is used for labels which are the target of non-local gotos. Such a 760label that would have been deleted is replaced with a @code{note} of type 761@code{NOTE_INSN_DELETED_LABEL}. 762 763In an @code{insn} during dead-code elimination, 1 means that the insn is 764dead code. 765 766In an @code{insn} or @code{jump_insn} during reorg for an insn in the 767delay slot of a branch, 7681 means that this insn is from the target of the branch. 769 770In an @code{insn} during instruction scheduling, 1 means that this insn 771must be scheduled as part of a group together with the previous insn. 772 773In an RTL dump, this flag is represented as @samp{/s}. 774 775@findex integrated 776@cindex @samp{/i} in RTL dump 777@item integrated 778In an @code{insn}, @code{insn_list}, or @code{const}, 1 means the RTL was 779produced by procedure integration. 780 781In @code{reg} expressions, 1 means the register contains 782the value to be returned by the current function. On 783machines that pass parameters in registers, the same register number 784may be used for parameters as well, but this flag is not set on such 785uses. 786 787In @code{symbol_ref} expressions, 1 means the referenced symbol is weak. 788 789In an RTL dump, this flag is represented as @samp{/i}. 790 791@findex jump 792@cindex @samp{/j} in RTL dump 793@item jump 794In a @code{mem} expression, 1 means we should keep the alias set for this 795mem unchanged when we access a component. 796 797In a @code{set}, 1 means it is for a return. 798 799In a @code{call_insn}, 1 means it is a sibling call. 800 801In an RTL dump, this flag is represented as @samp{/j}. 802 803@findex unchanging 804@cindex @samp{/u} in RTL dump 805@item unchanging 806In @code{reg} and @code{mem} expressions, 1 means 807that the value of the expression never changes. 808 809In @code{subreg} expressions, it is 1 if the @code{subreg} references an 810unsigned object whose mode has been promoted to a wider mode. 811 812In an @code{insn} or @code{jump_insn} in the delay slot of a branch 813instruction, 1 means an annulling branch should be used. 814 815In a @code{symbol_ref} expression, 1 means that this symbol addresses 816something in the per-function constant pool. 817 818In a @code{call_insn}, @code{note}, or an @code{expr_list} of notes, 8191 means that this instruction is a call to a const or pure function. 820 821In an RTL dump, this flag is represented as @samp{/u}. 822 823@findex used 824@item used 825This flag is used directly (without an access macro) at the end of RTL 826generation for a function, to count the number of times an expression 827appears in insns. Expressions that appear more than once are copied, 828according to the rules for shared structure (@pxref{Sharing}). 829 830For a @code{reg}, it is used directly (without an access macro) by the 831leaf register renumbering code to ensure that each register is only 832renumbered once. 833 834In a @code{symbol_ref}, it indicates that an external declaration for 835the symbol has already been written. 836 837@findex volatil 838@cindex @samp{/v} in RTL dump 839@item volatil 840@cindex volatile memory references 841In a @code{mem}, @code{asm_operands}, or @code{asm_input} 842expression, it is 1 if the memory 843reference is volatile. Volatile memory references may not be deleted, 844reordered or combined. 845 846In a @code{symbol_ref} expression, it is used for machine-specific 847purposes. 848 849In a @code{reg} expression, it is 1 if the value is a user-level variable. 8500 indicates an internal compiler temporary. 851 852In an @code{insn}, 1 means the insn has been deleted. 853 854In @code{label_ref} and @code{reg_label} expressions, 1 means a reference 855to a non-local label. 856 857In an RTL dump, this flag is represented as @samp{/v}. 858@end table 859 860@node Machine Modes 861@section Machine Modes 862@cindex machine modes 863 864@findex enum machine_mode 865A machine mode describes a size of data object and the representation used 866for it. In the C code, machine modes are represented by an enumeration 867type, @code{enum machine_mode}, defined in @file{machmode.def}. Each RTL 868expression has room for a machine mode and so do certain kinds of tree 869expressions (declarations and types, to be precise). 870 871In debugging dumps and machine descriptions, the machine mode of an RTL 872expression is written after the expression code with a colon to separate 873them. The letters @samp{mode} which appear at the end of each machine mode 874name are omitted. For example, @code{(reg:SI 38)} is a @code{reg} 875expression with machine mode @code{SImode}. If the mode is 876@code{VOIDmode}, it is not written at all. 877 878Here is a table of machine modes. The term ``byte'' below refers to an 879object of @code{BITS_PER_UNIT} bits (@pxref{Storage Layout}). 880 881@table @code 882@findex BImode 883@item BImode 884``Bit'' mode represents a single bit, for predicate registers. 885 886@findex QImode 887@item QImode 888``Quarter-Integer'' mode represents a single byte treated as an integer. 889 890@findex HImode 891@item HImode 892``Half-Integer'' mode represents a two-byte integer. 893 894@findex PSImode 895@item PSImode 896``Partial Single Integer'' mode represents an integer which occupies 897four bytes but which doesn't really use all four. On some machines, 898this is the right mode to use for pointers. 899 900@findex SImode 901@item SImode 902``Single Integer'' mode represents a four-byte integer. 903 904@findex PDImode 905@item PDImode 906``Partial Double Integer'' mode represents an integer which occupies 907eight bytes but which doesn't really use all eight. On some machines, 908this is the right mode to use for certain pointers. 909 910@findex DImode 911@item DImode 912``Double Integer'' mode represents an eight-byte integer. 913 914@findex TImode 915@item TImode 916``Tetra Integer'' (?) mode represents a sixteen-byte integer. 917 918@findex OImode 919@item OImode 920``Octa Integer'' (?) mode represents a thirty-two-byte integer. 921 922@findex QFmode 923@item QFmode 924``Quarter-Floating'' mode represents a quarter-precision (single byte) 925floating point number. 926 927@findex HFmode 928@item HFmode 929``Half-Floating'' mode represents a half-precision (two byte) floating 930point number. 931 932@findex TQFmode 933@item TQFmode 934``Three-Quarter-Floating'' (?) mode represents a three-quarter-precision 935(three byte) floating point number. 936 937@findex SFmode 938@item SFmode 939``Single Floating'' mode represents a four byte floating point number. 940In the common case, of a processor with IEEE arithmetic and 8-bit bytes, 941this is a single-precision IEEE floating point number; it can also be 942used for double-precision (on processors with 16-bit bytes) and 943single-precision VAX and IBM types. 944 945@findex DFmode 946@item DFmode 947``Double Floating'' mode represents an eight byte floating point number. 948In the common case, of a processor with IEEE arithmetic and 8-bit bytes, 949this is a double-precision IEEE floating point number. 950 951@findex XFmode 952@item XFmode 953``Extended Floating'' mode represents a twelve byte floating point 954number. This mode is used for IEEE extended floating point. On some 955systems not all bits within these bytes will actually be used. 956 957@findex TFmode 958@item TFmode 959``Tetra Floating'' mode represents a sixteen byte floating point number. 960This gets used for both the 96-bit extended IEEE floating-point types 961padded to 128 bits, and true 128-bit extended IEEE floating-point types. 962 963@findex CCmode 964@item CCmode 965``Condition Code'' mode represents the value of a condition code, which 966is a machine-specific set of bits used to represent the result of a 967comparison operation. Other machine-specific modes may also be used for 968the condition code. These modes are not used on machines that use 969@code{cc0} (see @pxref{Condition Code}). 970 971@findex BLKmode 972@item BLKmode 973``Block'' mode represents values that are aggregates to which none of 974the other modes apply. In RTL, only memory references can have this mode, 975and only if they appear in string-move or vector instructions. On machines 976which have no such instructions, @code{BLKmode} will not appear in RTL@. 977 978@findex VOIDmode 979@item VOIDmode 980Void mode means the absence of a mode or an unspecified mode. 981For example, RTL expressions of code @code{const_int} have mode 982@code{VOIDmode} because they can be taken to have whatever mode the context 983requires. In debugging dumps of RTL, @code{VOIDmode} is expressed by 984the absence of any mode. 985 986@findex QCmode 987@findex HCmode 988@findex SCmode 989@findex DCmode 990@findex XCmode 991@findex TCmode 992@item QCmode, HCmode, SCmode, DCmode, XCmode, TCmode 993These modes stand for a complex number represented as a pair of floating 994point values. The floating point values are in @code{QFmode}, 995@code{HFmode}, @code{SFmode}, @code{DFmode}, @code{XFmode}, and 996@code{TFmode}, respectively. 997 998@findex CQImode 999@findex CHImode 1000@findex CSImode 1001@findex CDImode 1002@findex CTImode 1003@findex COImode 1004@item CQImode, CHImode, CSImode, CDImode, CTImode, COImode 1005These modes stand for a complex number represented as a pair of integer 1006values. The integer values are in @code{QImode}, @code{HImode}, 1007@code{SImode}, @code{DImode}, @code{TImode}, and @code{OImode}, 1008respectively. 1009@end table 1010 1011The machine description defines @code{Pmode} as a C macro which expands 1012into the machine mode used for addresses. Normally this is the mode 1013whose size is @code{BITS_PER_WORD}, @code{SImode} on 32-bit machines. 1014 1015The only modes which a machine description @i{must} support are 1016@code{QImode}, and the modes corresponding to @code{BITS_PER_WORD}, 1017@code{FLOAT_TYPE_SIZE} and @code{DOUBLE_TYPE_SIZE}. 1018The compiler will attempt to use @code{DImode} for 8-byte structures and 1019unions, but this can be prevented by overriding the definition of 1020@code{MAX_FIXED_MODE_SIZE}. Alternatively, you can have the compiler 1021use @code{TImode} for 16-byte structures and unions. Likewise, you can 1022arrange for the C type @code{short int} to avoid using @code{HImode}. 1023 1024@cindex mode classes 1025Very few explicit references to machine modes remain in the compiler and 1026these few references will soon be removed. Instead, the machine modes 1027are divided into mode classes. These are represented by the enumeration 1028type @code{enum mode_class} defined in @file{machmode.h}. The possible 1029mode classes are: 1030 1031@table @code 1032@findex MODE_INT 1033@item MODE_INT 1034Integer modes. By default these are @code{BImode}, @code{QImode}, 1035@code{HImode}, @code{SImode}, @code{DImode}, @code{TImode}, and 1036@code{OImode}. 1037 1038@findex MODE_PARTIAL_INT 1039@item MODE_PARTIAL_INT 1040The ``partial integer'' modes, @code{PQImode}, @code{PHImode}, 1041@code{PSImode} and @code{PDImode}. 1042 1043@findex MODE_FLOAT 1044@item MODE_FLOAT 1045Floating point modes. By default these are @code{QFmode}, 1046@code{HFmode}, @code{TQFmode}, @code{SFmode}, @code{DFmode}, 1047@code{XFmode} and @code{TFmode}. 1048 1049@findex MODE_COMPLEX_INT 1050@item MODE_COMPLEX_INT 1051Complex integer modes. (These are not currently implemented). 1052 1053@findex MODE_COMPLEX_FLOAT 1054@item MODE_COMPLEX_FLOAT 1055Complex floating point modes. By default these are @code{QCmode}, 1056@code{HCmode}, @code{SCmode}, @code{DCmode}, @code{XCmode}, and 1057@code{TCmode}. 1058 1059@findex MODE_FUNCTION 1060@item MODE_FUNCTION 1061Algol or Pascal function variables including a static chain. 1062(These are not currently implemented). 1063 1064@findex MODE_CC 1065@item MODE_CC 1066Modes representing condition code values. These are @code{CCmode} plus 1067any modes listed in the @code{EXTRA_CC_MODES} macro. @xref{Jump Patterns}, 1068also see @ref{Condition Code}. 1069 1070@findex MODE_RANDOM 1071@item MODE_RANDOM 1072This is a catchall mode class for modes which don't fit into the above 1073classes. Currently @code{VOIDmode} and @code{BLKmode} are in 1074@code{MODE_RANDOM}. 1075@end table 1076 1077Here are some C macros that relate to machine modes: 1078 1079@table @code 1080@findex GET_MODE 1081@item GET_MODE (@var{x}) 1082Returns the machine mode of the RTX @var{x}. 1083 1084@findex PUT_MODE 1085@item PUT_MODE (@var{x}, @var{newmode}) 1086Alters the machine mode of the RTX @var{x} to be @var{newmode}. 1087 1088@findex NUM_MACHINE_MODES 1089@item NUM_MACHINE_MODES 1090Stands for the number of machine modes available on the target 1091machine. This is one greater than the largest numeric value of any 1092machine mode. 1093 1094@findex GET_MODE_NAME 1095@item GET_MODE_NAME (@var{m}) 1096Returns the name of mode @var{m} as a string. 1097 1098@findex GET_MODE_CLASS 1099@item GET_MODE_CLASS (@var{m}) 1100Returns the mode class of mode @var{m}. 1101 1102@findex GET_MODE_WIDER_MODE 1103@item GET_MODE_WIDER_MODE (@var{m}) 1104Returns the next wider natural mode. For example, the expression 1105@code{GET_MODE_WIDER_MODE (QImode)} returns @code{HImode}. 1106 1107@findex GET_MODE_SIZE 1108@item GET_MODE_SIZE (@var{m}) 1109Returns the size in bytes of a datum of mode @var{m}. 1110 1111@findex GET_MODE_BITSIZE 1112@item GET_MODE_BITSIZE (@var{m}) 1113Returns the size in bits of a datum of mode @var{m}. 1114 1115@findex GET_MODE_MASK 1116@item GET_MODE_MASK (@var{m}) 1117Returns a bitmask containing 1 for all bits in a word that fit within 1118mode @var{m}. This macro can only be used for modes whose bitsize is 1119less than or equal to @code{HOST_BITS_PER_INT}. 1120 1121@findex GET_MODE_ALIGNMENT 1122@item GET_MODE_ALIGNMENT (@var{m}) 1123Return the required alignment, in bits, for an object of mode @var{m}. 1124 1125@findex GET_MODE_UNIT_SIZE 1126@item GET_MODE_UNIT_SIZE (@var{m}) 1127Returns the size in bytes of the subunits of a datum of mode @var{m}. 1128This is the same as @code{GET_MODE_SIZE} except in the case of complex 1129modes. For them, the unit size is the size of the real or imaginary 1130part. 1131 1132@findex GET_MODE_NUNITS 1133@item GET_MODE_NUNITS (@var{m}) 1134Returns the number of units contained in a mode, i.e., 1135@code{GET_MODE_SIZE} divided by @code{GET_MODE_UNIT_SIZE}. 1136 1137@findex GET_CLASS_NARROWEST_MODE 1138@item GET_CLASS_NARROWEST_MODE (@var{c}) 1139Returns the narrowest mode in mode class @var{c}. 1140@end table 1141 1142@findex byte_mode 1143@findex word_mode 1144The global variables @code{byte_mode} and @code{word_mode} contain modes 1145whose classes are @code{MODE_INT} and whose bitsizes are either 1146@code{BITS_PER_UNIT} or @code{BITS_PER_WORD}, respectively. On 32-bit 1147machines, these are @code{QImode} and @code{SImode}, respectively. 1148 1149@node Constants 1150@section Constant Expression Types 1151@cindex RTL constants 1152@cindex RTL constant expression types 1153 1154The simplest RTL expressions are those that represent constant values. 1155 1156@table @code 1157@findex const_int 1158@item (const_int @var{i}) 1159This type of expression represents the integer value @var{i}. @var{i} 1160is customarily accessed with the macro @code{INTVAL} as in 1161@code{INTVAL (@var{exp})}, which is equivalent to @code{XWINT (@var{exp}, 0)}. 1162 1163@findex const0_rtx 1164@findex const1_rtx 1165@findex const2_rtx 1166@findex constm1_rtx 1167There is only one expression object for the integer value zero; it is 1168the value of the variable @code{const0_rtx}. Likewise, the only 1169expression for integer value one is found in @code{const1_rtx}, the only 1170expression for integer value two is found in @code{const2_rtx}, and the 1171only expression for integer value negative one is found in 1172@code{constm1_rtx}. Any attempt to create an expression of code 1173@code{const_int} and value zero, one, two or negative one will return 1174@code{const0_rtx}, @code{const1_rtx}, @code{const2_rtx} or 1175@code{constm1_rtx} as appropriate. 1176 1177@findex const_true_rtx 1178Similarly, there is only one object for the integer whose value is 1179@code{STORE_FLAG_VALUE}. It is found in @code{const_true_rtx}. If 1180@code{STORE_FLAG_VALUE} is one, @code{const_true_rtx} and 1181@code{const1_rtx} will point to the same object. If 1182@code{STORE_FLAG_VALUE} is @minus{}1, @code{const_true_rtx} and 1183@code{constm1_rtx} will point to the same object. 1184 1185@findex const_double 1186@item (const_double:@var{m} @var{addr} @var{i0} @var{i1} @dots{}) 1187Represents either a floating-point constant of mode @var{m} or an 1188integer constant too large to fit into @code{HOST_BITS_PER_WIDE_INT} 1189bits but small enough to fit within twice that number of bits (GCC 1190does not provide a mechanism to represent even larger constants). In 1191the latter case, @var{m} will be @code{VOIDmode}. 1192 1193@findex const_vector 1194@item (const_vector:@var{m} [@var{x0} @var{x1} @dots{}]) 1195Represents a vector constant. The square brackets stand for the vector 1196containing the constant elements. @var{x0}, @var{x1} and so on are 1197the @code{const_int} or @code{const_double} elements. 1198 1199The number of units in a @code{const_vector} is obtained with the macro 1200@code{CONST_VECTOR_NUNITS} as in @code{CONST_VECTOR_NUNITS (@var{v})}. 1201 1202Individual elements in a vector constant are accessed with the macro 1203@code{CONST_VECTOR_ELT} as in @code{CONST_VECTOR_ELT (@var{v}, @var{n})} 1204where @var{v} is the vector constant and @var{n} is the element 1205desired. 1206 1207@findex CONST_DOUBLE_MEM 1208@findex CONST_DOUBLE_CHAIN 1209@var{addr} is used to contain the @code{mem} expression that corresponds 1210to the location in memory that at which the constant can be found. If 1211it has not been allocated a memory location, but is on the chain of all 1212@code{const_double} expressions in this compilation (maintained using an 1213undisplayed field), @var{addr} contains @code{const0_rtx}. If it is not 1214on the chain, @var{addr} contains @code{cc0_rtx}. @var{addr} is 1215customarily accessed with the macro @code{CONST_DOUBLE_MEM} and the 1216chain field via @code{CONST_DOUBLE_CHAIN}. 1217 1218@findex CONST_DOUBLE_LOW 1219If @var{m} is @code{VOIDmode}, the bits of the value are stored in 1220@var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro 1221@code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}. 1222 1223If the constant is floating point (regardless of its precision), then 1224the number of integers used to store the value depends on the size of 1225@code{REAL_VALUE_TYPE} (@pxref{Floating Point}). The integers 1226represent a floating point number, but not precisely in the target 1227machine's or host machine's floating point format. To convert them to 1228the precise bit pattern used by the target machine, use the macro 1229@code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}). 1230 1231@findex CONST0_RTX 1232@findex CONST1_RTX 1233@findex CONST2_RTX 1234The macro @code{CONST0_RTX (@var{mode})} refers to an expression with 1235value 0 in mode @var{mode}. If mode @var{mode} is of mode class 1236@code{MODE_INT}, it returns @code{const0_rtx}. If mode @var{mode} is of 1237mode class @code{MODE_FLOAT}, it returns a @code{CONST_DOUBLE} 1238expression in mode @var{mode}. Otherwise, it returns a 1239@code{CONST_VECTOR} expression in mode @var{mode}. Similarly, the macro 1240@code{CONST1_RTX (@var{mode})} refers to an expression with value 1 in 1241mode @var{mode} and similarly for @code{CONST2_RTX}. The 1242@code{CONST1_RTX} and @code{CONST2_RTX} macros are undefined 1243for vector modes. 1244 1245@findex const_string 1246@item (const_string @var{str}) 1247Represents a constant string with value @var{str}. Currently this is 1248used only for insn attributes (@pxref{Insn Attributes}) since constant 1249strings in C are placed in memory. 1250 1251@findex symbol_ref 1252@item (symbol_ref:@var{mode} @var{symbol}) 1253Represents the value of an assembler label for data. @var{symbol} is 1254a string that describes the name of the assembler label. If it starts 1255with a @samp{*}, the label is the rest of @var{symbol} not including 1256the @samp{*}. Otherwise, the label is @var{symbol}, usually prefixed 1257with @samp{_}. 1258 1259The @code{symbol_ref} contains a mode, which is usually @code{Pmode}. 1260Usually that is the only mode for which a symbol is directly valid. 1261 1262@findex label_ref 1263@item (label_ref @var{label}) 1264Represents the value of an assembler label for code. It contains one 1265operand, an expression, which must be a @code{code_label} or a @code{note} 1266of type @code{NOTE_INSN_DELETED_LABEL} that appears in the instruction 1267sequence to identify the place where the label should go. 1268 1269The reason for using a distinct expression type for code label 1270references is so that jump optimization can distinguish them. 1271 1272@item (const:@var{m} @var{exp}) 1273Represents a constant that is the result of an assembly-time 1274arithmetic computation. The operand, @var{exp}, is an expression that 1275contains only constants (@code{const_int}, @code{symbol_ref} and 1276@code{label_ref} expressions) combined with @code{plus} and 1277@code{minus}. However, not all combinations are valid, since the 1278assembler cannot do arbitrary arithmetic on relocatable symbols. 1279 1280@var{m} should be @code{Pmode}. 1281 1282@findex high 1283@item (high:@var{m} @var{exp}) 1284Represents the high-order bits of @var{exp}, usually a 1285@code{symbol_ref}. The number of bits is machine-dependent and is 1286normally the number of bits specified in an instruction that initializes 1287the high order bits of a register. It is used with @code{lo_sum} to 1288represent the typical two-instruction sequence used in RISC machines to 1289reference a global memory location. 1290 1291@var{m} should be @code{Pmode}. 1292@end table 1293 1294@node Regs and Memory 1295@section Registers and Memory 1296@cindex RTL register expressions 1297@cindex RTL memory expressions 1298 1299Here are the RTL expression types for describing access to machine 1300registers and to main memory. 1301 1302@table @code 1303@findex reg 1304@cindex hard registers 1305@cindex pseudo registers 1306@item (reg:@var{m} @var{n}) 1307For small values of the integer @var{n} (those that are less than 1308@code{FIRST_PSEUDO_REGISTER}), this stands for a reference to machine 1309register number @var{n}: a @dfn{hard register}. For larger values of 1310@var{n}, it stands for a temporary value or @dfn{pseudo register}. 1311The compiler's strategy is to generate code assuming an unlimited 1312number of such pseudo registers, and later convert them into hard 1313registers or into memory references. 1314 1315@var{m} is the machine mode of the reference. It is necessary because 1316machines can generally refer to each register in more than one mode. 1317For example, a register may contain a full word but there may be 1318instructions to refer to it as a half word or as a single byte, as 1319well as instructions to refer to it as a floating point number of 1320various precisions. 1321 1322Even for a register that the machine can access in only one mode, 1323the mode must always be specified. 1324 1325The symbol @code{FIRST_PSEUDO_REGISTER} is defined by the machine 1326description, since the number of hard registers on the machine is an 1327invariant characteristic of the machine. Note, however, that not 1328all of the machine registers must be general registers. All the 1329machine registers that can be used for storage of data are given 1330hard register numbers, even those that can be used only in certain 1331instructions or can hold only certain types of data. 1332 1333A hard register may be accessed in various modes throughout one 1334function, but each pseudo register is given a natural mode 1335and is accessed only in that mode. When it is necessary to describe 1336an access to a pseudo register using a nonnatural mode, a @code{subreg} 1337expression is used. 1338 1339A @code{reg} expression with a machine mode that specifies more than 1340one word of data may actually stand for several consecutive registers. 1341If in addition the register number specifies a hardware register, then 1342it actually represents several consecutive hardware registers starting 1343with the specified one. 1344 1345Each pseudo register number used in a function's RTL code is 1346represented by a unique @code{reg} expression. 1347 1348@findex FIRST_VIRTUAL_REGISTER 1349@findex LAST_VIRTUAL_REGISTER 1350Some pseudo register numbers, those within the range of 1351@code{FIRST_VIRTUAL_REGISTER} to @code{LAST_VIRTUAL_REGISTER} only 1352appear during the RTL generation phase and are eliminated before the 1353optimization phases. These represent locations in the stack frame that 1354cannot be determined until RTL generation for the function has been 1355completed. The following virtual register numbers are defined: 1356 1357@table @code 1358@findex VIRTUAL_INCOMING_ARGS_REGNUM 1359@item VIRTUAL_INCOMING_ARGS_REGNUM 1360This points to the first word of the incoming arguments passed on the 1361stack. Normally these arguments are placed there by the caller, but the 1362callee may have pushed some arguments that were previously passed in 1363registers. 1364 1365@cindex @code{FIRST_PARM_OFFSET} and virtual registers 1366@cindex @code{ARG_POINTER_REGNUM} and virtual registers 1367When RTL generation is complete, this virtual register is replaced 1368by the sum of the register given by @code{ARG_POINTER_REGNUM} and the 1369value of @code{FIRST_PARM_OFFSET}. 1370 1371@findex VIRTUAL_STACK_VARS_REGNUM 1372@cindex @code{FRAME_GROWS_DOWNWARD} and virtual registers 1373@item VIRTUAL_STACK_VARS_REGNUM 1374If @code{FRAME_GROWS_DOWNWARD} is defined, this points to immediately 1375above the first variable on the stack. Otherwise, it points to the 1376first variable on the stack. 1377 1378@cindex @code{STARTING_FRAME_OFFSET} and virtual registers 1379@cindex @code{FRAME_POINTER_REGNUM} and virtual registers 1380@code{VIRTUAL_STACK_VARS_REGNUM} is replaced with the sum of the 1381register given by @code{FRAME_POINTER_REGNUM} and the value 1382@code{STARTING_FRAME_OFFSET}. 1383 1384@findex VIRTUAL_STACK_DYNAMIC_REGNUM 1385@item VIRTUAL_STACK_DYNAMIC_REGNUM 1386This points to the location of dynamically allocated memory on the stack 1387immediately after the stack pointer has been adjusted by the amount of 1388memory desired. 1389 1390@cindex @code{STACK_DYNAMIC_OFFSET} and virtual registers 1391@cindex @code{STACK_POINTER_REGNUM} and virtual registers 1392This virtual register is replaced by the sum of the register given by 1393@code{STACK_POINTER_REGNUM} and the value @code{STACK_DYNAMIC_OFFSET}. 1394 1395@findex VIRTUAL_OUTGOING_ARGS_REGNUM 1396@item VIRTUAL_OUTGOING_ARGS_REGNUM 1397This points to the location in the stack at which outgoing arguments 1398should be written when the stack is pre-pushed (arguments pushed using 1399push insns should always use @code{STACK_POINTER_REGNUM}). 1400 1401@cindex @code{STACK_POINTER_OFFSET} and virtual registers 1402This virtual register is replaced by the sum of the register given by 1403@code{STACK_POINTER_REGNUM} and the value @code{STACK_POINTER_OFFSET}. 1404@end table 1405 1406@findex subreg 1407@item (subreg:@var{m} @var{reg} @var{bytenum}) 1408@code{subreg} expressions are used to refer to a register in a machine 1409mode other than its natural one, or to refer to one register of 1410a multi-part @code{reg} that actually refers to several registers. 1411 1412Each pseudo-register has a natural mode. If it is necessary to 1413operate on it in a different mode---for example, to perform a fullword 1414move instruction on a pseudo-register that contains a single 1415byte---the pseudo-register must be enclosed in a @code{subreg}. In 1416such a case, @var{bytenum} is zero. 1417 1418Usually @var{m} is at least as narrow as the mode of @var{reg}, in which 1419case it is restricting consideration to only the bits of @var{reg} that 1420are in @var{m}. 1421 1422Sometimes @var{m} is wider than the mode of @var{reg}. These 1423@code{subreg} expressions are often called @dfn{paradoxical}. They are 1424used in cases where we want to refer to an object in a wider mode but do 1425not care what value the additional bits have. The reload pass ensures 1426that paradoxical references are only made to hard registers. 1427 1428The other use of @code{subreg} is to extract the individual registers of 1429a multi-register value. Machine modes such as @code{DImode} and 1430@code{TImode} can indicate values longer than a word, values which 1431usually require two or more consecutive registers. To access one of the 1432registers, use a @code{subreg} with mode @code{SImode} and a 1433@var{bytenum} offset that says which register. 1434 1435Storing in a non-paradoxical @code{subreg} has undefined results for 1436bits belonging to the same word as the @code{subreg}. This laxity makes 1437it easier to generate efficient code for such instructions. To 1438represent an instruction that preserves all the bits outside of those in 1439the @code{subreg}, use @code{strict_low_part} around the @code{subreg}. 1440 1441@cindex @code{WORDS_BIG_ENDIAN}, effect on @code{subreg} 1442The compilation parameter @code{WORDS_BIG_ENDIAN}, if set to 1, says 1443that byte number zero is part of the most significant word; otherwise, 1444it is part of the least significant word. 1445 1446@cindex @code{BYTES_BIG_ENDIAN}, effect on @code{subreg} 1447The compilation parameter @code{BYTES_BIG_ENDIAN}, if set to 1, says 1448that byte number zero is the most significant byte within a word; 1449otherwise, it is the least significant byte within a word. 1450 1451@cindex @code{FLOAT_WORDS_BIG_ENDIAN}, (lack of) effect on @code{subreg} 1452On a few targets, @code{FLOAT_WORDS_BIG_ENDIAN} disagrees with 1453@code{WORDS_BIG_ENDIAN}. 1454However, most parts of the compiler treat floating point values as if 1455they had the same endianness as integer values. This works because 1456they handle them solely as a collection of integer values, with no 1457particular numerical value. Only real.c and the runtime libraries 1458care about @code{FLOAT_WORDS_BIG_ENDIAN}. 1459 1460@cindex combiner pass 1461@cindex reload pass 1462@cindex @code{subreg}, special reload handling 1463Between the combiner pass and the reload pass, it is possible to have a 1464paradoxical @code{subreg} which contains a @code{mem} instead of a 1465@code{reg} as its first operand. After the reload pass, it is also 1466possible to have a non-paradoxical @code{subreg} which contains a 1467@code{mem}; this usually occurs when the @code{mem} is a stack slot 1468which replaced a pseudo register. 1469 1470Note that it is not valid to access a @code{DFmode} value in @code{SFmode} 1471using a @code{subreg}. On some machines the most significant part of a 1472@code{DFmode} value does not have the same format as a single-precision 1473floating value. 1474 1475It is also not valid to access a single word of a multi-word value in a 1476hard register when less registers can hold the value than would be 1477expected from its size. For example, some 32-bit machines have 1478floating-point registers that can hold an entire @code{DFmode} value. 1479If register 10 were such a register @code{(subreg:SI (reg:DF 10) 1)} 1480would be invalid because there is no way to convert that reference to 1481a single machine register. The reload pass prevents @code{subreg} 1482expressions such as these from being formed. 1483 1484@findex SUBREG_REG 1485@findex SUBREG_BYTE 1486The first operand of a @code{subreg} expression is customarily accessed 1487with the @code{SUBREG_REG} macro and the second operand is customarily 1488accessed with the @code{SUBREG_BYTE} macro. 1489 1490@findex scratch 1491@cindex scratch operands 1492@item (scratch:@var{m}) 1493This represents a scratch register that will be required for the 1494execution of a single instruction and not used subsequently. It is 1495converted into a @code{reg} by either the local register allocator or 1496the reload pass. 1497 1498@code{scratch} is usually present inside a @code{clobber} operation 1499(@pxref{Side Effects}). 1500 1501@findex cc0 1502@cindex condition code register 1503@item (cc0) 1504This refers to the machine's condition code register. It has no 1505operands and may not have a machine mode. There are two ways to use it: 1506 1507@itemize @bullet 1508@item 1509To stand for a complete set of condition code flags. This is best on 1510most machines, where each comparison sets the entire series of flags. 1511 1512With this technique, @code{(cc0)} may be validly used in only two 1513contexts: as the destination of an assignment (in test and compare 1514instructions) and in comparison operators comparing against zero 1515(@code{const_int} with value zero; that is to say, @code{const0_rtx}). 1516 1517@item 1518To stand for a single flag that is the result of a single condition. 1519This is useful on machines that have only a single flag bit, and in 1520which comparison instructions must specify the condition to test. 1521 1522With this technique, @code{(cc0)} may be validly used in only two 1523contexts: as the destination of an assignment (in test and compare 1524instructions) where the source is a comparison operator, and as the 1525first operand of @code{if_then_else} (in a conditional branch). 1526@end itemize 1527 1528@findex cc0_rtx 1529There is only one expression object of code @code{cc0}; it is the 1530value of the variable @code{cc0_rtx}. Any attempt to create an 1531expression of code @code{cc0} will return @code{cc0_rtx}. 1532 1533Instructions can set the condition code implicitly. On many machines, 1534nearly all instructions set the condition code based on the value that 1535they compute or store. It is not necessary to record these actions 1536explicitly in the RTL because the machine description includes a 1537prescription for recognizing the instructions that do so (by means of 1538the macro @code{NOTICE_UPDATE_CC}). @xref{Condition Code}. Only 1539instructions whose sole purpose is to set the condition code, and 1540instructions that use the condition code, need mention @code{(cc0)}. 1541 1542On some machines, the condition code register is given a register number 1543and a @code{reg} is used instead of @code{(cc0)}. This is usually the 1544preferable approach if only a small subset of instructions modify the 1545condition code. Other machines store condition codes in general 1546registers; in such cases a pseudo register should be used. 1547 1548Some machines, such as the SPARC and RS/6000, have two sets of 1549arithmetic instructions, one that sets and one that does not set the 1550condition code. This is best handled by normally generating the 1551instruction that does not set the condition code, and making a pattern 1552that both performs the arithmetic and sets the condition code register 1553(which would not be @code{(cc0)} in this case). For examples, search 1554for @samp{addcc} and @samp{andcc} in @file{sparc.md}. 1555 1556@findex pc 1557@item (pc) 1558@cindex program counter 1559This represents the machine's program counter. It has no operands and 1560may not have a machine mode. @code{(pc)} may be validly used only in 1561certain specific contexts in jump instructions. 1562 1563@findex pc_rtx 1564There is only one expression object of code @code{pc}; it is the value 1565of the variable @code{pc_rtx}. Any attempt to create an expression of 1566code @code{pc} will return @code{pc_rtx}. 1567 1568All instructions that do not jump alter the program counter implicitly 1569by incrementing it, but there is no need to mention this in the RTL@. 1570 1571@findex mem 1572@item (mem:@var{m} @var{addr} @var{alias}) 1573This RTX represents a reference to main memory at an address 1574represented by the expression @var{addr}. @var{m} specifies how large 1575a unit of memory is accessed. @var{alias} specifies an alias set for the 1576reference. In general two items are in different alias sets if they cannot 1577reference the same memory address. 1578 1579The construct @code{(mem:BLK (scratch))} is considered to alias all 1580other memories. Thus it may be used as a memory barrier in epilogue 1581stack deallocation patterns. 1582 1583@findex addressof 1584@item (addressof:@var{m} @var{reg}) 1585This RTX represents a request for the address of register @var{reg}. Its mode 1586is always @code{Pmode}. If there are any @code{addressof} 1587expressions left in the function after CSE, @var{reg} is forced into the 1588stack and the @code{addressof} expression is replaced with a @code{plus} 1589expression for the address of its stack slot. 1590@end table 1591 1592@node Arithmetic 1593@section RTL Expressions for Arithmetic 1594@cindex arithmetic, in RTL 1595@cindex math, in RTL 1596@cindex RTL expressions for arithmetic 1597 1598Unless otherwise specified, all the operands of arithmetic expressions 1599must be valid for mode @var{m}. An operand is valid for mode @var{m} 1600if it has mode @var{m}, or if it is a @code{const_int} or 1601@code{const_double} and @var{m} is a mode of class @code{MODE_INT}. 1602 1603For commutative binary operations, constants should be placed in the 1604second operand. 1605 1606@table @code 1607@findex plus 1608@cindex RTL addition 1609@cindex RTL sum 1610@item (plus:@var{m} @var{x} @var{y}) 1611Represents the sum of the values represented by @var{x} and @var{y} 1612carried out in machine mode @var{m}. 1613 1614@findex lo_sum 1615@item (lo_sum:@var{m} @var{x} @var{y}) 1616Like @code{plus}, except that it represents that sum of @var{x} and the 1617low-order bits of @var{y}. The number of low order bits is 1618machine-dependent but is normally the number of bits in a @code{Pmode} 1619item minus the number of bits set by the @code{high} code 1620(@pxref{Constants}). 1621 1622@var{m} should be @code{Pmode}. 1623 1624@findex minus 1625@cindex RTL subtraction 1626@cindex RTL difference 1627@item (minus:@var{m} @var{x} @var{y}) 1628Like @code{plus} but represents subtraction. 1629 1630@findex ss_plus 1631@cindex RTL addition with signed saturation 1632@item (ss_plus:@var{m} @var{x} @var{y}) 1633 1634Like @code{plus}, but using signed saturation in case of an overflow. 1635 1636@findex us_plus 1637@cindex RTL addition with unsigned saturation 1638@item (us_plus:@var{m} @var{x} @var{y}) 1639 1640Like @code{plus}, but using unsigned saturation in case of an overflow. 1641 1642@findex ss_minus 1643@cindex RTL addition with signed saturation 1644@item (ss_minus:@var{m} @var{x} @var{y}) 1645 1646Like @code{minus}, but using signed saturation in case of an overflow. 1647 1648@findex us_minus 1649@cindex RTL addition with unsigned saturation 1650@item (us_minus:@var{m} @var{x} @var{y}) 1651 1652Like @code{minus}, but using unsigned saturation in case of an overflow. 1653 1654@findex compare 1655@cindex RTL comparison 1656@item (compare:@var{m} @var{x} @var{y}) 1657Represents the result of subtracting @var{y} from @var{x} for purposes 1658of comparison. The result is computed without overflow, as if with 1659infinite precision. 1660 1661Of course, machines can't really subtract with infinite precision. 1662However, they can pretend to do so when only the sign of the result will 1663be used, which is the case when the result is stored in the condition 1664code. And that is the @emph{only} way this kind of expression may 1665validly be used: as a value to be stored in the condition codes, either 1666@code{(cc0)} or a register. @xref{Comparisons}. 1667 1668The mode @var{m} is not related to the modes of @var{x} and @var{y}, but 1669instead is the mode of the condition code value. If @code{(cc0)} is 1670used, it is @code{VOIDmode}. Otherwise it is some mode in class 1671@code{MODE_CC}, often @code{CCmode}. @xref{Condition Code}. If @var{m} 1672is @code{VOIDmode} or @code{CCmode}, the operation returns sufficient 1673information (in an unspecified format) so that any comparison operator 1674can be applied to the result of the @code{COMPARE} operation. For other 1675modes in class @code{MODE_CC}, the operation only returns a subset of 1676this information. 1677 1678Normally, @var{x} and @var{y} must have the same mode. Otherwise, 1679@code{compare} is valid only if the mode of @var{x} is in class 1680@code{MODE_INT} and @var{y} is a @code{const_int} or 1681@code{const_double} with mode @code{VOIDmode}. The mode of @var{x} 1682determines what mode the comparison is to be done in; thus it must not 1683be @code{VOIDmode}. 1684 1685If one of the operands is a constant, it should be placed in the 1686second operand and the comparison code adjusted as appropriate. 1687 1688A @code{compare} specifying two @code{VOIDmode} constants is not valid 1689since there is no way to know in what mode the comparison is to be 1690performed; the comparison must either be folded during the compilation 1691or the first operand must be loaded into a register while its mode is 1692still known. 1693 1694@findex neg 1695@item (neg:@var{m} @var{x}) 1696Represents the negation (subtraction from zero) of the value represented 1697by @var{x}, carried out in mode @var{m}. 1698 1699@findex mult 1700@cindex multiplication 1701@cindex product 1702@item (mult:@var{m} @var{x} @var{y}) 1703Represents the signed product of the values represented by @var{x} and 1704@var{y} carried out in machine mode @var{m}. 1705 1706Some machines support a multiplication that generates a product wider 1707than the operands. Write the pattern for this as 1708 1709@example 1710(mult:@var{m} (sign_extend:@var{m} @var{x}) (sign_extend:@var{m} @var{y})) 1711@end example 1712 1713where @var{m} is wider than the modes of @var{x} and @var{y}, which need 1714not be the same. 1715 1716For unsigned widening multiplication, use the same idiom, but with 1717@code{zero_extend} instead of @code{sign_extend}. 1718 1719@findex div 1720@cindex division 1721@cindex signed division 1722@cindex quotient 1723@item (div:@var{m} @var{x} @var{y}) 1724Represents the quotient in signed division of @var{x} by @var{y}, 1725carried out in machine mode @var{m}. If @var{m} is a floating point 1726mode, it represents the exact quotient; otherwise, the integerized 1727quotient. 1728 1729Some machines have division instructions in which the operands and 1730quotient widths are not all the same; you should represent 1731such instructions using @code{truncate} and @code{sign_extend} as in, 1732 1733@example 1734(truncate:@var{m1} (div:@var{m2} @var{x} (sign_extend:@var{m2} @var{y}))) 1735@end example 1736 1737@findex udiv 1738@cindex unsigned division 1739@cindex division 1740@item (udiv:@var{m} @var{x} @var{y}) 1741Like @code{div} but represents unsigned division. 1742 1743@findex mod 1744@findex umod 1745@cindex remainder 1746@cindex division 1747@item (mod:@var{m} @var{x} @var{y}) 1748@itemx (umod:@var{m} @var{x} @var{y}) 1749Like @code{div} and @code{udiv} but represent the remainder instead of 1750the quotient. 1751 1752@findex smin 1753@findex smax 1754@cindex signed minimum 1755@cindex signed maximum 1756@item (smin:@var{m} @var{x} @var{y}) 1757@itemx (smax:@var{m} @var{x} @var{y}) 1758Represents the smaller (for @code{smin}) or larger (for @code{smax}) of 1759@var{x} and @var{y}, interpreted as signed integers in mode @var{m}. 1760 1761@findex umin 1762@findex umax 1763@cindex unsigned minimum and maximum 1764@item (umin:@var{m} @var{x} @var{y}) 1765@itemx (umax:@var{m} @var{x} @var{y}) 1766Like @code{smin} and @code{smax}, but the values are interpreted as unsigned 1767integers. 1768 1769@findex not 1770@cindex complement, bitwise 1771@cindex bitwise complement 1772@item (not:@var{m} @var{x}) 1773Represents the bitwise complement of the value represented by @var{x}, 1774carried out in mode @var{m}, which must be a fixed-point machine mode. 1775 1776@findex and 1777@cindex logical-and, bitwise 1778@cindex bitwise logical-and 1779@item (and:@var{m} @var{x} @var{y}) 1780Represents the bitwise logical-and of the values represented by 1781@var{x} and @var{y}, carried out in machine mode @var{m}, which must be 1782a fixed-point machine mode. 1783 1784@findex ior 1785@cindex inclusive-or, bitwise 1786@cindex bitwise inclusive-or 1787@item (ior:@var{m} @var{x} @var{y}) 1788Represents the bitwise inclusive-or of the values represented by @var{x} 1789and @var{y}, carried out in machine mode @var{m}, which must be a 1790fixed-point mode. 1791 1792@findex xor 1793@cindex exclusive-or, bitwise 1794@cindex bitwise exclusive-or 1795@item (xor:@var{m} @var{x} @var{y}) 1796Represents the bitwise exclusive-or of the values represented by @var{x} 1797and @var{y}, carried out in machine mode @var{m}, which must be a 1798fixed-point mode. 1799 1800@findex ashift 1801@cindex left shift 1802@cindex shift 1803@cindex arithmetic shift 1804@item (ashift:@var{m} @var{x} @var{c}) 1805Represents the result of arithmetically shifting @var{x} left by @var{c} 1806places. @var{x} have mode @var{m}, a fixed-point machine mode. @var{c} 1807be a fixed-point mode or be a constant with mode @code{VOIDmode}; which 1808mode is determined by the mode called for in the machine description 1809entry for the left-shift instruction. For example, on the VAX, the mode 1810of @var{c} is @code{QImode} regardless of @var{m}. 1811 1812@findex lshiftrt 1813@cindex right shift 1814@findex ashiftrt 1815@item (lshiftrt:@var{m} @var{x} @var{c}) 1816@itemx (ashiftrt:@var{m} @var{x} @var{c}) 1817Like @code{ashift} but for right shift. Unlike the case for left shift, 1818these two operations are distinct. 1819 1820@findex rotate 1821@cindex rotate 1822@cindex left rotate 1823@findex rotatert 1824@cindex right rotate 1825@item (rotate:@var{m} @var{x} @var{c}) 1826@itemx (rotatert:@var{m} @var{x} @var{c}) 1827Similar but represent left and right rotate. If @var{c} is a constant, 1828use @code{rotate}. 1829 1830@findex abs 1831@cindex absolute value 1832@item (abs:@var{m} @var{x}) 1833Represents the absolute value of @var{x}, computed in mode @var{m}. 1834 1835@findex sqrt 1836@cindex square root 1837@item (sqrt:@var{m} @var{x}) 1838Represents the square root of @var{x}, computed in mode @var{m}. 1839Most often @var{m} will be a floating point mode. 1840 1841@findex ffs 1842@item (ffs:@var{m} @var{x}) 1843Represents one plus the index of the least significant 1-bit in 1844@var{x}, represented as an integer of mode @var{m}. (The value is 1845zero if @var{x} is zero.) The mode of @var{x} need not be @var{m}; 1846depending on the target machine, various mode combinations may be 1847valid. 1848@end table 1849 1850@node Comparisons 1851@section Comparison Operations 1852@cindex RTL comparison operations 1853 1854Comparison operators test a relation on two operands and are considered 1855to represent a machine-dependent nonzero value described by, but not 1856necessarily equal to, @code{STORE_FLAG_VALUE} (@pxref{Misc}) 1857if the relation holds, or zero if it does not, for comparison operators 1858whose results have a `MODE_INT' mode, and 1859@code{FLOAT_STORE_FLAG_VALUE} (@pxref{Misc}) if the relation holds, or 1860zero if it does not, for comparison operators that return floating-point 1861values. The mode of the comparison operation is independent of the mode 1862of the data being compared. If the comparison operation is being tested 1863(e.g., the first operand of an @code{if_then_else}), the mode must be 1864@code{VOIDmode}. 1865 1866@cindex condition codes 1867There are two ways that comparison operations may be used. The 1868comparison operators may be used to compare the condition codes 1869@code{(cc0)} against zero, as in @code{(eq (cc0) (const_int 0))}. Such 1870a construct actually refers to the result of the preceding instruction 1871in which the condition codes were set. The instruction setting the 1872condition code must be adjacent to the instruction using the condition 1873code; only @code{note} insns may separate them. 1874 1875Alternatively, a comparison operation may directly compare two data 1876objects. The mode of the comparison is determined by the operands; they 1877must both be valid for a common machine mode. A comparison with both 1878operands constant would be invalid as the machine mode could not be 1879deduced from it, but such a comparison should never exist in RTL due to 1880constant folding. 1881 1882In the example above, if @code{(cc0)} were last set to 1883@code{(compare @var{x} @var{y})}, the comparison operation is 1884identical to @code{(eq @var{x} @var{y})}. Usually only one style 1885of comparisons is supported on a particular machine, but the combine 1886pass will try to merge the operations to produce the @code{eq} shown 1887in case it exists in the context of the particular insn involved. 1888 1889Inequality comparisons come in two flavors, signed and unsigned. Thus, 1890there are distinct expression codes @code{gt} and @code{gtu} for signed and 1891unsigned greater-than. These can produce different results for the same 1892pair of integer values: for example, 1 is signed greater-than @minus{}1 but not 1893unsigned greater-than, because @minus{}1 when regarded as unsigned is actually 1894@code{0xffffffff} which is greater than 1. 1895 1896The signed comparisons are also used for floating point values. Floating 1897point comparisons are distinguished by the machine modes of the operands. 1898 1899@table @code 1900@findex eq 1901@cindex equal 1902@item (eq:@var{m} @var{x} @var{y}) 1903@code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y} 1904are equal, otherwise 0. 1905 1906@findex ne 1907@cindex not equal 1908@item (ne:@var{m} @var{x} @var{y}) 1909@code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y} 1910are not equal, otherwise 0. 1911 1912@findex gt 1913@cindex greater than 1914@item (gt:@var{m} @var{x} @var{y}) 1915@code{STORE_FLAG_VALUE} if the @var{x} is greater than @var{y}. If they 1916are fixed-point, the comparison is done in a signed sense. 1917 1918@findex gtu 1919@cindex greater than 1920@cindex unsigned greater than 1921@item (gtu:@var{m} @var{x} @var{y}) 1922Like @code{gt} but does unsigned comparison, on fixed-point numbers only. 1923 1924@findex lt 1925@cindex less than 1926@findex ltu 1927@cindex unsigned less than 1928@item (lt:@var{m} @var{x} @var{y}) 1929@itemx (ltu:@var{m} @var{x} @var{y}) 1930Like @code{gt} and @code{gtu} but test for ``less than''. 1931 1932@findex ge 1933@cindex greater than 1934@findex geu 1935@cindex unsigned greater than 1936@item (ge:@var{m} @var{x} @var{y}) 1937@itemx (geu:@var{m} @var{x} @var{y}) 1938Like @code{gt} and @code{gtu} but test for ``greater than or equal''. 1939 1940@findex le 1941@cindex less than or equal 1942@findex leu 1943@cindex unsigned less than 1944@item (le:@var{m} @var{x} @var{y}) 1945@itemx (leu:@var{m} @var{x} @var{y}) 1946Like @code{gt} and @code{gtu} but test for ``less than or equal''. 1947 1948@findex if_then_else 1949@item (if_then_else @var{cond} @var{then} @var{else}) 1950This is not a comparison operation but is listed here because it is 1951always used in conjunction with a comparison operation. To be 1952precise, @var{cond} is a comparison expression. This expression 1953represents a choice, according to @var{cond}, between the value 1954represented by @var{then} and the one represented by @var{else}. 1955 1956On most machines, @code{if_then_else} expressions are valid only 1957to express conditional jumps. 1958 1959@findex cond 1960@item (cond [@var{test1} @var{value1} @var{test2} @var{value2} @dots{}] @var{default}) 1961Similar to @code{if_then_else}, but more general. Each of @var{test1}, 1962@var{test2}, @dots{} is performed in turn. The result of this expression is 1963the @var{value} corresponding to the first nonzero test, or @var{default} if 1964none of the tests are nonzero expressions. 1965 1966This is currently not valid for instruction patterns and is supported only 1967for insn attributes. @xref{Insn Attributes}. 1968@end table 1969 1970@node Bit-Fields 1971@section Bit-Fields 1972@cindex bit-fields 1973 1974Special expression codes exist to represent bit-field instructions. 1975These types of expressions are lvalues in RTL; they may appear 1976on the left side of an assignment, indicating insertion of a value 1977into the specified bit-field. 1978 1979@table @code 1980@findex sign_extract 1981@cindex @code{BITS_BIG_ENDIAN}, effect on @code{sign_extract} 1982@item (sign_extract:@var{m} @var{loc} @var{size} @var{pos}) 1983This represents a reference to a sign-extended bit-field contained or 1984starting in @var{loc} (a memory or register reference). The bit-field 1985is @var{size} bits wide and starts at bit @var{pos}. The compilation 1986option @code{BITS_BIG_ENDIAN} says which end of the memory unit 1987@var{pos} counts from. 1988 1989If @var{loc} is in memory, its mode must be a single-byte integer mode. 1990If @var{loc} is in a register, the mode to use is specified by the 1991operand of the @code{insv} or @code{extv} pattern 1992(@pxref{Standard Names}) and is usually a full-word integer mode, 1993which is the default if none is specified. 1994 1995The mode of @var{pos} is machine-specific and is also specified 1996in the @code{insv} or @code{extv} pattern. 1997 1998The mode @var{m} is the same as the mode that would be used for 1999@var{loc} if it were a register. 2000 2001@findex zero_extract 2002@item (zero_extract:@var{m} @var{loc} @var{size} @var{pos}) 2003Like @code{sign_extract} but refers to an unsigned or zero-extended 2004bit-field. The same sequence of bits are extracted, but they 2005are filled to an entire word with zeros instead of by sign-extension. 2006@end table 2007 2008@node Vector Operations 2009@section Vector Operations 2010@cindex vector operations 2011 2012All normal RTL expressions can be used with vector modes; they are 2013interpreted as operating on each part of the vector independently. 2014Additionally, there are a few new expressions to describe specific vector 2015operations. 2016 2017@table @code 2018@findex vec_merge 2019@item (vec_merge:@var{m} @var{vec1} @var{vec2} @var{items}) 2020This describes a merge operation between two vectors. The result is a vector 2021of mode @var{m}; its elements are selected from either @var{vec1} or 2022@var{vec2}. Which elements are selected is described by @var{items}, which 2023is a bit mask represented by a @code{const_int}; a zero bit indicates the 2024corresponding element in the result vector is taken from @var{vec2} while 2025a set bit indicates it is taken from @var{vec1}. 2026 2027@findex vec_select 2028@item (vec_select:@var{m} @var{vec1} @var{selection}) 2029This describes an operation that selects parts of a vector. @var{vec1} is 2030the source vector, @var{selection} is a @code{parallel} that contains a 2031@code{const_int} for each of the subparts of the result vector, giving the 2032number of the source subpart that should be stored into it. 2033 2034@findex vec_concat 2035@item (vec_concat:@var{m} @var{vec1} @var{vec2}) 2036Describes a vector concat operation. The result is a concatenation of the 2037vectors @var{vec1} and @var{vec2}; its length is the sum of the lengths of 2038the two inputs. 2039 2040@findex vec_const 2041@item (vec_const:@var{m} @var{subparts}) 2042This describes a constant vector. @var{subparts} is a @code{parallel} that 2043contains a constant for each of the subparts of the vector. 2044 2045@findex vec_duplicate 2046@item (vec_duplicate:@var{m} @var{vec}) 2047This operation converts a small vector into a larger one by duplicating the 2048input values. The output vector mode must have the same submodes as the 2049input vector mode, and the number of output parts must be an integer multiple 2050of the number of input parts. 2051 2052@end table 2053 2054@node Conversions 2055@section Conversions 2056@cindex conversions 2057@cindex machine mode conversions 2058 2059All conversions between machine modes must be represented by 2060explicit conversion operations. For example, an expression 2061which is the sum of a byte and a full word cannot be written as 2062@code{(plus:SI (reg:QI 34) (reg:SI 80))} because the @code{plus} 2063operation requires two operands of the same machine mode. 2064Therefore, the byte-sized operand is enclosed in a conversion 2065operation, as in 2066 2067@example 2068(plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80)) 2069@end example 2070 2071The conversion operation is not a mere placeholder, because there 2072may be more than one way of converting from a given starting mode 2073to the desired final mode. The conversion operation code says how 2074to do it. 2075 2076For all conversion operations, @var{x} must not be @code{VOIDmode} 2077because the mode in which to do the conversion would not be known. 2078The conversion must either be done at compile-time or @var{x} 2079must be placed into a register. 2080 2081@table @code 2082@findex sign_extend 2083@item (sign_extend:@var{m} @var{x}) 2084Represents the result of sign-extending the value @var{x} 2085to machine mode @var{m}. @var{m} must be a fixed-point mode 2086and @var{x} a fixed-point value of a mode narrower than @var{m}. 2087 2088@findex zero_extend 2089@item (zero_extend:@var{m} @var{x}) 2090Represents the result of zero-extending the value @var{x} 2091to machine mode @var{m}. @var{m} must be a fixed-point mode 2092and @var{x} a fixed-point value of a mode narrower than @var{m}. 2093 2094@findex float_extend 2095@item (float_extend:@var{m} @var{x}) 2096Represents the result of extending the value @var{x} 2097to machine mode @var{m}. @var{m} must be a floating point mode 2098and @var{x} a floating point value of a mode narrower than @var{m}. 2099 2100@findex truncate 2101@item (truncate:@var{m} @var{x}) 2102Represents the result of truncating the value @var{x} 2103to machine mode @var{m}. @var{m} must be a fixed-point mode 2104and @var{x} a fixed-point value of a mode wider than @var{m}. 2105 2106@findex ss_truncate 2107@item (ss_truncate:@var{m} @var{x}) 2108Represents the result of truncating the value @var{x} 2109to machine mode @var{m}, using signed saturation in the case of 2110overflow. Both @var{m} and the mode of @var{x} must be fixed-point 2111modes. 2112 2113@findex us_truncate 2114@item (us_truncate:@var{m} @var{x}) 2115Represents the result of truncating the value @var{x} 2116to machine mode @var{m}, using unsigned saturation in the case of 2117overflow. Both @var{m} and the mode of @var{x} must be fixed-point 2118modes. 2119 2120@findex float_truncate 2121@item (float_truncate:@var{m} @var{x}) 2122Represents the result of truncating the value @var{x} 2123to machine mode @var{m}. @var{m} must be a floating point mode 2124and @var{x} a floating point value of a mode wider than @var{m}. 2125 2126@findex float 2127@item (float:@var{m} @var{x}) 2128Represents the result of converting fixed point value @var{x}, 2129regarded as signed, to floating point mode @var{m}. 2130 2131@findex unsigned_float 2132@item (unsigned_float:@var{m} @var{x}) 2133Represents the result of converting fixed point value @var{x}, 2134regarded as unsigned, to floating point mode @var{m}. 2135 2136@findex fix 2137@item (fix:@var{m} @var{x}) 2138When @var{m} is a fixed point mode, represents the result of 2139converting floating point value @var{x} to mode @var{m}, regarded as 2140signed. How rounding is done is not specified, so this operation may 2141be used validly in compiling C code only for integer-valued operands. 2142 2143@findex unsigned_fix 2144@item (unsigned_fix:@var{m} @var{x}) 2145Represents the result of converting floating point value @var{x} to 2146fixed point mode @var{m}, regarded as unsigned. How rounding is done 2147is not specified. 2148 2149@findex fix 2150@item (fix:@var{m} @var{x}) 2151When @var{m} is a floating point mode, represents the result of 2152converting floating point value @var{x} (valid for mode @var{m}) to an 2153integer, still represented in floating point mode @var{m}, by rounding 2154towards zero. 2155@end table 2156 2157@node RTL Declarations 2158@section Declarations 2159@cindex RTL declarations 2160@cindex declarations, RTL 2161 2162Declaration expression codes do not represent arithmetic operations 2163but rather state assertions about their operands. 2164 2165@table @code 2166@findex strict_low_part 2167@cindex @code{subreg}, in @code{strict_low_part} 2168@item (strict_low_part (subreg:@var{m} (reg:@var{n} @var{r}) 0)) 2169This expression code is used in only one context: as the destination operand of a 2170@code{set} expression. In addition, the operand of this expression 2171must be a non-paradoxical @code{subreg} expression. 2172 2173The presence of @code{strict_low_part} says that the part of the 2174register which is meaningful in mode @var{n}, but is not part of 2175mode @var{m}, is not to be altered. Normally, an assignment to such 2176a subreg is allowed to have undefined effects on the rest of the 2177register when @var{m} is less than a word. 2178@end table 2179 2180@node Side Effects 2181@section Side Effect Expressions 2182@cindex RTL side effect expressions 2183 2184The expression codes described so far represent values, not actions. 2185But machine instructions never produce values; they are meaningful 2186only for their side effects on the state of the machine. Special 2187expression codes are used to represent side effects. 2188 2189The body of an instruction is always one of these side effect codes; 2190the codes described above, which represent values, appear only as 2191the operands of these. 2192 2193@table @code 2194@findex set 2195@item (set @var{lval} @var{x}) 2196Represents the action of storing the value of @var{x} into the place 2197represented by @var{lval}. @var{lval} must be an expression 2198representing a place that can be stored in: @code{reg} (or @code{subreg} 2199or @code{strict_low_part}), @code{mem}, @code{pc}, @code{parallel}, or 2200@code{cc0}. 2201 2202If @var{lval} is a @code{reg}, @code{subreg} or @code{mem}, it has a 2203machine mode; then @var{x} must be valid for that mode. 2204 2205If @var{lval} is a @code{reg} whose machine mode is less than the full 2206width of the register, then it means that the part of the register 2207specified by the machine mode is given the specified value and the 2208rest of the register receives an undefined value. Likewise, if 2209@var{lval} is a @code{subreg} whose machine mode is narrower than 2210the mode of the register, the rest of the register can be changed in 2211an undefined way. 2212 2213If @var{lval} is a @code{strict_low_part} of a @code{subreg}, then the 2214part of the register specified by the machine mode of the 2215@code{subreg} is given the value @var{x} and the rest of the register 2216is not changed. 2217 2218If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may 2219be either a @code{compare} expression or a value that may have any mode. 2220The latter case represents a ``test'' instruction. The expression 2221@code{(set (cc0) (reg:@var{m} @var{n}))} is equivalent to 2222@code{(set (cc0) (compare (reg:@var{m} @var{n}) (const_int 0)))}. 2223Use the former expression to save space during the compilation. 2224 2225If @var{lval} is a @code{parallel}, it is used to represent the case of 2226a function returning a structure in multiple registers. Each element 2227of the @code{parallel} is an @code{expr_list} whose first operand is a 2228@code{reg} and whose second operand is a @code{const_int} representing the 2229offset (in bytes) into the structure at which the data in that register 2230corresponds. The first element may be null to indicate that the structure 2231is also passed partly in memory. 2232 2233@cindex jump instructions and @code{set} 2234@cindex @code{if_then_else} usage 2235If @var{lval} is @code{(pc)}, we have a jump instruction, and the 2236possibilities for @var{x} are very limited. It may be a 2237@code{label_ref} expression (unconditional jump). It may be an 2238@code{if_then_else} (conditional jump), in which case either the 2239second or the third operand must be @code{(pc)} (for the case which 2240does not jump) and the other of the two must be a @code{label_ref} 2241(for the case which does jump). @var{x} may also be a @code{mem} or 2242@code{(plus:SI (pc) @var{y})}, where @var{y} may be a @code{reg} or a 2243@code{mem}; these unusual patterns are used to represent jumps through 2244branch tables. 2245 2246If @var{lval} is neither @code{(cc0)} nor @code{(pc)}, the mode of 2247@var{lval} must not be @code{VOIDmode} and the mode of @var{x} must be 2248valid for the mode of @var{lval}. 2249 2250@findex SET_DEST 2251@findex SET_SRC 2252@var{lval} is customarily accessed with the @code{SET_DEST} macro and 2253@var{x} with the @code{SET_SRC} macro. 2254 2255@findex return 2256@item (return) 2257As the sole expression in a pattern, represents a return from the 2258current function, on machines where this can be done with one 2259instruction, such as VAXen. On machines where a multi-instruction 2260``epilogue'' must be executed in order to return from the function, 2261returning is done by jumping to a label which precedes the epilogue, and 2262the @code{return} expression code is never used. 2263 2264Inside an @code{if_then_else} expression, represents the value to be 2265placed in @code{pc} to return to the caller. 2266 2267Note that an insn pattern of @code{(return)} is logically equivalent to 2268@code{(set (pc) (return))}, but the latter form is never used. 2269 2270@findex call 2271@item (call @var{function} @var{nargs}) 2272Represents a function call. @var{function} is a @code{mem} expression 2273whose address is the address of the function to be called. 2274@var{nargs} is an expression which can be used for two purposes: on 2275some machines it represents the number of bytes of stack argument; on 2276others, it represents the number of argument registers. 2277 2278Each machine has a standard machine mode which @var{function} must 2279have. The machine description defines macro @code{FUNCTION_MODE} to 2280expand into the requisite mode name. The purpose of this mode is to 2281specify what kind of addressing is allowed, on machines where the 2282allowed kinds of addressing depend on the machine mode being 2283addressed. 2284 2285@findex clobber 2286@item (clobber @var{x}) 2287Represents the storing or possible storing of an unpredictable, 2288undescribed value into @var{x}, which must be a @code{reg}, 2289@code{scratch}, @code{parallel} or @code{mem} expression. 2290 2291One place this is used is in string instructions that store standard 2292values into particular hard registers. It may not be worth the 2293trouble to describe the values that are stored, but it is essential to 2294inform the compiler that the registers will be altered, lest it 2295attempt to keep data in them across the string instruction. 2296 2297If @var{x} is @code{(mem:BLK (const_int 0))} or 2298@code{(mem:BLK (scratch))}, it means that all memory 2299locations must be presumed clobbered. If @var{x} is a @code{parallel}, 2300it has the same meaning as a @code{parallel} in a @code{set} expression. 2301 2302Note that the machine description classifies certain hard registers as 2303``call-clobbered''. All function call instructions are assumed by 2304default to clobber these registers, so there is no need to use 2305@code{clobber} expressions to indicate this fact. Also, each function 2306call is assumed to have the potential to alter any memory location, 2307unless the function is declared @code{const}. 2308 2309If the last group of expressions in a @code{parallel} are each a 2310@code{clobber} expression whose arguments are @code{reg} or 2311@code{match_scratch} (@pxref{RTL Template}) expressions, the combiner 2312phase can add the appropriate @code{clobber} expressions to an insn it 2313has constructed when doing so will cause a pattern to be matched. 2314 2315This feature can be used, for example, on a machine that whose multiply 2316and add instructions don't use an MQ register but which has an 2317add-accumulate instruction that does clobber the MQ register. Similarly, 2318a combined instruction might require a temporary register while the 2319constituent instructions might not. 2320 2321When a @code{clobber} expression for a register appears inside a 2322@code{parallel} with other side effects, the register allocator 2323guarantees that the register is unoccupied both before and after that 2324insn. However, the reload phase may allocate a register used for one of 2325the inputs unless the @samp{&} constraint is specified for the selected 2326alternative (@pxref{Modifiers}). You can clobber either a specific hard 2327register, a pseudo register, or a @code{scratch} expression; in the 2328latter two cases, GCC will allocate a hard register that is available 2329there for use as a temporary. 2330 2331For instructions that require a temporary register, you should use 2332@code{scratch} instead of a pseudo-register because this will allow the 2333combiner phase to add the @code{clobber} when required. You do this by 2334coding (@code{clobber} (@code{match_scratch} @dots{})). If you do 2335clobber a pseudo register, use one which appears nowhere else---generate 2336a new one each time. Otherwise, you may confuse CSE@. 2337 2338There is one other known use for clobbering a pseudo register in a 2339@code{parallel}: when one of the input operands of the insn is also 2340clobbered by the insn. In this case, using the same pseudo register in 2341the clobber and elsewhere in the insn produces the expected results. 2342 2343@findex use 2344@item (use @var{x}) 2345Represents the use of the value of @var{x}. It indicates that the 2346value in @var{x} at this point in the program is needed, even though 2347it may not be apparent why this is so. Therefore, the compiler will 2348not attempt to delete previous instructions whose only effect is to 2349store a value in @var{x}. @var{x} must be a @code{reg} expression. 2350 2351In some situations, it may be tempting to add a @code{use} of a 2352register in a @code{parallel} to describe a situation where the value 2353of a special register will modify the behavior of the instruction. 2354An hypothetical example might be a pattern for an addition that can 2355either wrap around or use saturating addition depending on the value 2356of a special control register: 2357 2358@smallexample 2359(parallel [(set (reg:SI 2) (unspec:SI [(reg:SI 3) 2360 (reg:SI 4)] 0)) 2361 (use (reg:SI 1))]) 2362@end smallexample 2363 2364@noindent 2365 2366This will not work, several of the optimizers only look at expressions 2367locally; it is very likely that if you have multiple insns with 2368identical inputs to the @code{unspec}, they will be optimized away even 2369if register 1 changes in between. 2370 2371This means that @code{use} can @emph{only} be used to describe 2372that the register is live. You should think twice before adding 2373@code{use} statements, more often you will want to use @code{unspec} 2374instead. The @code{use} RTX is most commonly useful to describe that 2375a fixed register is implicitly used in an insn. It is also safe to use 2376in patterns where the compiler knows for other reasons that the result 2377of the whole pattern is variable, such as @samp{movstr@var{m}} or 2378@samp{call} patterns. 2379 2380During the reload phase, an insn that has a @code{use} as pattern 2381can carry a reg_equal note. These @code{use} insns will be deleted 2382before the reload phase exits. 2383 2384During the delayed branch scheduling phase, @var{x} may be an insn. 2385This indicates that @var{x} previously was located at this place in the 2386code and its data dependencies need to be taken into account. These 2387@code{use} insns will be deleted before the delayed branch scheduling 2388phase exits. 2389 2390@findex parallel 2391@item (parallel [@var{x0} @var{x1} @dots{}]) 2392Represents several side effects performed in parallel. The square 2393brackets stand for a vector; the operand of @code{parallel} is a 2394vector of expressions. @var{x0}, @var{x1} and so on are individual 2395side effect expressions---expressions of code @code{set}, @code{call}, 2396@code{return}, @code{clobber} or @code{use}. 2397 2398``In parallel'' means that first all the values used in the individual 2399side-effects are computed, and second all the actual side-effects are 2400performed. For example, 2401 2402@example 2403(parallel [(set (reg:SI 1) (mem:SI (reg:SI 1))) 2404 (set (mem:SI (reg:SI 1)) (reg:SI 1))]) 2405@end example 2406 2407@noindent 2408says unambiguously that the values of hard register 1 and the memory 2409location addressed by it are interchanged. In both places where 2410@code{(reg:SI 1)} appears as a memory address it refers to the value 2411in register 1 @emph{before} the execution of the insn. 2412 2413It follows that it is @emph{incorrect} to use @code{parallel} and 2414expect the result of one @code{set} to be available for the next one. 2415For example, people sometimes attempt to represent a jump-if-zero 2416instruction this way: 2417 2418@example 2419(parallel [(set (cc0) (reg:SI 34)) 2420 (set (pc) (if_then_else 2421 (eq (cc0) (const_int 0)) 2422 (label_ref @dots{}) 2423 (pc)))]) 2424@end example 2425 2426@noindent 2427But this is incorrect, because it says that the jump condition depends 2428on the condition code value @emph{before} this instruction, not on the 2429new value that is set by this instruction. 2430 2431@cindex peephole optimization, RTL representation 2432Peephole optimization, which takes place together with final assembly 2433code output, can produce insns whose patterns consist of a @code{parallel} 2434whose elements are the operands needed to output the resulting 2435assembler code---often @code{reg}, @code{mem} or constant expressions. 2436This would not be well-formed RTL at any other stage in compilation, 2437but it is ok then because no further optimization remains to be done. 2438However, the definition of the macro @code{NOTICE_UPDATE_CC}, if 2439any, must deal with such insns if you define any peephole optimizations. 2440 2441@findex cond_exec 2442@item (cond_exec [@var{cond} @var{expr}]) 2443Represents a conditionally executed expression. The @var{expr} is 2444executed only if the @var{cond} is nonzero. The @var{cond} expression 2445must not have side-effects, but the @var{expr} may very well have 2446side-effects. 2447 2448@findex sequence 2449@item (sequence [@var{insns} @dots{}]) 2450Represents a sequence of insns. Each of the @var{insns} that appears 2451in the vector is suitable for appearing in the chain of insns, so it 2452must be an @code{insn}, @code{jump_insn}, @code{call_insn}, 2453@code{code_label}, @code{barrier} or @code{note}. 2454 2455A @code{sequence} RTX is never placed in an actual insn during RTL 2456generation. It represents the sequence of insns that result from a 2457@code{define_expand} @emph{before} those insns are passed to 2458@code{emit_insn} to insert them in the chain of insns. When actually 2459inserted, the individual sub-insns are separated out and the 2460@code{sequence} is forgotten. 2461 2462After delay-slot scheduling is completed, an insn and all the insns that 2463reside in its delay slots are grouped together into a @code{sequence}. 2464The insn requiring the delay slot is the first insn in the vector; 2465subsequent insns are to be placed in the delay slot. 2466 2467@code{INSN_ANNULLED_BRANCH_P} is set on an insn in a delay slot to 2468indicate that a branch insn should be used that will conditionally annul 2469the effect of the insns in the delay slots. In such a case, 2470@code{INSN_FROM_TARGET_P} indicates that the insn is from the target of 2471the branch and should be executed only if the branch is taken; otherwise 2472the insn should be executed only if the branch is not taken. 2473@xref{Delay Slots}. 2474@end table 2475 2476These expression codes appear in place of a side effect, as the body of 2477an insn, though strictly speaking they do not always describe side 2478effects as such: 2479 2480@table @code 2481@findex asm_input 2482@item (asm_input @var{s}) 2483Represents literal assembler code as described by the string @var{s}. 2484 2485@findex unspec 2486@findex unspec_volatile 2487@item (unspec [@var{operands} @dots{}] @var{index}) 2488@itemx (unspec_volatile [@var{operands} @dots{}] @var{index}) 2489Represents a machine-specific operation on @var{operands}. @var{index} 2490selects between multiple machine-specific operations. 2491@code{unspec_volatile} is used for volatile operations and operations 2492that may trap; @code{unspec} is used for other operations. 2493 2494These codes may appear inside a @code{pattern} of an 2495insn, inside a @code{parallel}, or inside an expression. 2496 2497@findex addr_vec 2498@item (addr_vec:@var{m} [@var{lr0} @var{lr1} @dots{}]) 2499Represents a table of jump addresses. The vector elements @var{lr0}, 2500etc., are @code{label_ref} expressions. The mode @var{m} specifies 2501how much space is given to each address; normally @var{m} would be 2502@code{Pmode}. 2503 2504@findex addr_diff_vec 2505@item (addr_diff_vec:@var{m} @var{base} [@var{lr0} @var{lr1} @dots{}] @var{min} @var{max} @var{flags}) 2506Represents a table of jump addresses expressed as offsets from 2507@var{base}. The vector elements @var{lr0}, etc., are @code{label_ref} 2508expressions and so is @var{base}. The mode @var{m} specifies how much 2509space is given to each address-difference. @var{min} and @var{max} 2510are set up by branch shortening and hold a label with a minimum and a 2511maximum address, respectively. @var{flags} indicates the relative 2512position of @var{base}, @var{min} and @var{max} to the containing insn 2513and of @var{min} and @var{max} to @var{base}. See rtl.def for details. 2514 2515@findex prefetch 2516@item (prefetch:@var{m} @var{addr} @var{rw} @var{locality}) 2517Represents prefetch of memory at address @var{addr}. 2518Operand @var{rw} is 1 if the prefetch is for data to be written, 0 otherwise; 2519targets that do not support write prefetches should treat this as a normal 2520prefetch. 2521Operand @var{locality} specifies the amount of temporal locality; 0 if there 2522is none or 1, 2, or 3 for increasing levels of temporal locality; 2523targets that do not support locality hints should ignore this. 2524 2525This insn is used to minimize cache-miss latency by moving data into a 2526cache before it is accessed. It should use only non-faulting data prefetch 2527instructions. 2528@end table 2529 2530@node Incdec 2531@section Embedded Side-Effects on Addresses 2532@cindex RTL preincrement 2533@cindex RTL postincrement 2534@cindex RTL predecrement 2535@cindex RTL postdecrement 2536 2537Six special side-effect expression codes appear as memory addresses. 2538 2539@table @code 2540@findex pre_dec 2541@item (pre_dec:@var{m} @var{x}) 2542Represents the side effect of decrementing @var{x} by a standard 2543amount and represents also the value that @var{x} has after being 2544decremented. @var{x} must be a @code{reg} or @code{mem}, but most 2545machines allow only a @code{reg}. @var{m} must be the machine mode 2546for pointers on the machine in use. The amount @var{x} is decremented 2547by is the length in bytes of the machine mode of the containing memory 2548reference of which this expression serves as the address. Here is an 2549example of its use: 2550 2551@example 2552(mem:DF (pre_dec:SI (reg:SI 39))) 2553@end example 2554 2555@noindent 2556This says to decrement pseudo register 39 by the length of a @code{DFmode} 2557value and use the result to address a @code{DFmode} value. 2558 2559@findex pre_inc 2560@item (pre_inc:@var{m} @var{x}) 2561Similar, but specifies incrementing @var{x} instead of decrementing it. 2562 2563@findex post_dec 2564@item (post_dec:@var{m} @var{x}) 2565Represents the same side effect as @code{pre_dec} but a different 2566value. The value represented here is the value @var{x} has @i{before} 2567being decremented. 2568 2569@findex post_inc 2570@item (post_inc:@var{m} @var{x}) 2571Similar, but specifies incrementing @var{x} instead of decrementing it. 2572 2573@findex post_modify 2574@item (post_modify:@var{m} @var{x} @var{y}) 2575 2576Represents the side effect of setting @var{x} to @var{y} and 2577represents @var{x} before @var{x} is modified. @var{x} must be a 2578@code{reg} or @code{mem}, but most machines allow only a @code{reg}. 2579@var{m} must be the machine mode for pointers on the machine in use. 2580 2581The expression @var{y} must be one of three forms: 2582@table @code 2583@code{(plus:@var{m} @var{x} @var{z})}, 2584@code{(minus:@var{m} @var{x} @var{z})}, or 2585@code{(plus:@var{m} @var{x} @var{i})}, 2586@end table 2587where @var{z} is an index register and @var{i} is a constant. 2588 2589Here is an example of its use: 2590 2591@smallexample 2592(mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42) 2593 (reg:SI 48)))) 2594@end smallexample 2595 2596This says to modify pseudo register 42 by adding the contents of pseudo 2597register 48 to it, after the use of what ever 42 points to. 2598 2599@findex pre_modify 2600@item (pre_modify:@var{m} @var{x} @var{expr}) 2601Similar except side effects happen before the use. 2602@end table 2603 2604These embedded side effect expressions must be used with care. Instruction 2605patterns may not use them. Until the @samp{flow} pass of the compiler, 2606they may occur only to represent pushes onto the stack. The @samp{flow} 2607pass finds cases where registers are incremented or decremented in one 2608instruction and used as an address shortly before or after; these cases are 2609then transformed to use pre- or post-increment or -decrement. 2610 2611If a register used as the operand of these expressions is used in 2612another address in an insn, the original value of the register is used. 2613Uses of the register outside of an address are not permitted within the 2614same insn as a use in an embedded side effect expression because such 2615insns behave differently on different machines and hence must be treated 2616as ambiguous and disallowed. 2617 2618An instruction that can be represented with an embedded side effect 2619could also be represented using @code{parallel} containing an additional 2620@code{set} to describe how the address register is altered. This is not 2621done because machines that allow these operations at all typically 2622allow them wherever a memory address is called for. Describing them as 2623additional parallel stores would require doubling the number of entries 2624in the machine description. 2625 2626@node Assembler 2627@section Assembler Instructions as Expressions 2628@cindex assembler instructions in RTL 2629 2630@cindex @code{asm_operands}, usage 2631The RTX code @code{asm_operands} represents a value produced by a 2632user-specified assembler instruction. It is used to represent 2633an @code{asm} statement with arguments. An @code{asm} statement with 2634a single output operand, like this: 2635 2636@smallexample 2637asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z)); 2638@end smallexample 2639 2640@noindent 2641is represented using a single @code{asm_operands} RTX which represents 2642the value that is stored in @code{outputvar}: 2643 2644@smallexample 2645(set @var{rtx-for-outputvar} 2646 (asm_operands "foo %1,%2,%0" "a" 0 2647 [@var{rtx-for-addition-result} @var{rtx-for-*z}] 2648 [(asm_input:@var{m1} "g") 2649 (asm_input:@var{m2} "di")])) 2650@end smallexample 2651 2652@noindent 2653Here the operands of the @code{asm_operands} RTX are the assembler 2654template string, the output-operand's constraint, the index-number of the 2655output operand among the output operands specified, a vector of input 2656operand RTX's, and a vector of input-operand modes and constraints. The 2657mode @var{m1} is the mode of the sum @code{x+y}; @var{m2} is that of 2658@code{*z}. 2659 2660When an @code{asm} statement has multiple output values, its insn has 2661several such @code{set} RTX's inside of a @code{parallel}. Each @code{set} 2662contains a @code{asm_operands}; all of these share the same assembler 2663template and vectors, but each contains the constraint for the respective 2664output operand. They are also distinguished by the output-operand index 2665number, which is 0, 1, @dots{} for successive output operands. 2666 2667@node Insns 2668@section Insns 2669@cindex insns 2670 2671The RTL representation of the code for a function is a doubly-linked 2672chain of objects called @dfn{insns}. Insns are expressions with 2673special codes that are used for no other purpose. Some insns are 2674actual instructions; others represent dispatch tables for @code{switch} 2675statements; others represent labels to jump to or various sorts of 2676declarative information. 2677 2678In addition to its own specific data, each insn must have a unique 2679id-number that distinguishes it from all other insns in the current 2680function (after delayed branch scheduling, copies of an insn with the 2681same id-number may be present in multiple places in a function, but 2682these copies will always be identical and will only appear inside a 2683@code{sequence}), and chain pointers to the preceding and following 2684insns. These three fields occupy the same position in every insn, 2685independent of the expression code of the insn. They could be accessed 2686with @code{XEXP} and @code{XINT}, but instead three special macros are 2687always used: 2688 2689@table @code 2690@findex INSN_UID 2691@item INSN_UID (@var{i}) 2692Accesses the unique id of insn @var{i}. 2693 2694@findex PREV_INSN 2695@item PREV_INSN (@var{i}) 2696Accesses the chain pointer to the insn preceding @var{i}. 2697If @var{i} is the first insn, this is a null pointer. 2698 2699@findex NEXT_INSN 2700@item NEXT_INSN (@var{i}) 2701Accesses the chain pointer to the insn following @var{i}. 2702If @var{i} is the last insn, this is a null pointer. 2703@end table 2704 2705@findex get_insns 2706@findex get_last_insn 2707The first insn in the chain is obtained by calling @code{get_insns}; the 2708last insn is the result of calling @code{get_last_insn}. Within the 2709chain delimited by these insns, the @code{NEXT_INSN} and 2710@code{PREV_INSN} pointers must always correspond: if @var{insn} is not 2711the first insn, 2712 2713@example 2714NEXT_INSN (PREV_INSN (@var{insn})) == @var{insn} 2715@end example 2716 2717@noindent 2718is always true and if @var{insn} is not the last insn, 2719 2720@example 2721PREV_INSN (NEXT_INSN (@var{insn})) == @var{insn} 2722@end example 2723 2724@noindent 2725is always true. 2726 2727After delay slot scheduling, some of the insns in the chain might be 2728@code{sequence} expressions, which contain a vector of insns. The value 2729of @code{NEXT_INSN} in all but the last of these insns is the next insn 2730in the vector; the value of @code{NEXT_INSN} of the last insn in the vector 2731is the same as the value of @code{NEXT_INSN} for the @code{sequence} in 2732which it is contained. Similar rules apply for @code{PREV_INSN}. 2733 2734This means that the above invariants are not necessarily true for insns 2735inside @code{sequence} expressions. Specifically, if @var{insn} is the 2736first insn in a @code{sequence}, @code{NEXT_INSN (PREV_INSN (@var{insn}))} 2737is the insn containing the @code{sequence} expression, as is the value 2738of @code{PREV_INSN (NEXT_INSN (@var{insn}))} if @var{insn} is the last 2739insn in the @code{sequence} expression. You can use these expressions 2740to find the containing @code{sequence} expression. 2741 2742Every insn has one of the following six expression codes: 2743 2744@table @code 2745@findex insn 2746@item insn 2747The expression code @code{insn} is used for instructions that do not jump 2748and do not do function calls. @code{sequence} expressions are always 2749contained in insns with code @code{insn} even if one of those insns 2750should jump or do function calls. 2751 2752Insns with code @code{insn} have four additional fields beyond the three 2753mandatory ones listed above. These four are described in a table below. 2754 2755@findex jump_insn 2756@item jump_insn 2757The expression code @code{jump_insn} is used for instructions that may 2758jump (or, more generally, may contain @code{label_ref} expressions). If 2759there is an instruction to return from the current function, it is 2760recorded as a @code{jump_insn}. 2761 2762@findex JUMP_LABEL 2763@code{jump_insn} insns have the same extra fields as @code{insn} insns, 2764accessed in the same way and in addition contain a field 2765@code{JUMP_LABEL} which is defined once jump optimization has completed. 2766 2767For simple conditional and unconditional jumps, this field contains 2768the @code{code_label} to which this insn will (possibly conditionally) 2769branch. In a more complex jump, @code{JUMP_LABEL} records one of the 2770labels that the insn refers to; the only way to find the others is to 2771scan the entire body of the insn. In an @code{addr_vec}, 2772@code{JUMP_LABEL} is @code{NULL_RTX}. 2773 2774Return insns count as jumps, but since they do not refer to any 2775labels, their @code{JUMP_LABEL} is @code{NULL_RTX}. 2776 2777@findex call_insn 2778@item call_insn 2779The expression code @code{call_insn} is used for instructions that may do 2780function calls. It is important to distinguish these instructions because 2781they imply that certain registers and memory locations may be altered 2782unpredictably. 2783 2784@findex CALL_INSN_FUNCTION_USAGE 2785@code{call_insn} insns have the same extra fields as @code{insn} insns, 2786accessed in the same way and in addition contain a field 2787@code{CALL_INSN_FUNCTION_USAGE}, which contains a list (chain of 2788@code{expr_list} expressions) containing @code{use} and @code{clobber} 2789expressions that denote hard registers and @code{MEM}s used or 2790clobbered by the called function. 2791 2792A @code{MEM} generally points to a stack slots in which arguments passed 2793to the libcall by reference (@pxref{Register Arguments, 2794FUNCTION_ARG_PASS_BY_REFERENCE}) are stored. If the argument is 2795caller-copied (@pxref{Register Arguments, FUNCTION_ARG_CALLEE_COPIES}), 2796the stack slot will be mentioned in @code{CLOBBER} and @code{USE} 2797entries; if it's callee-copied, only a @code{USE} will appear, and the 2798@code{MEM} may point to addresses that are not stack slots. These 2799@code{MEM}s are used only in libcalls, because, unlike regular function 2800calls, @code{CONST_CALL}s (which libcalls generally are, @pxref{Flags, 2801CONST_CALL_P}) aren't assumed to read and write all memory, so flow 2802would consider the stores dead and remove them. Note that, since a 2803libcall must never return values in memory (@pxref{Aggregate Return, 2804RETURN_IN_MEMORY}), there will never be a @code{CLOBBER} for a memory 2805address holding a return value. 2806 2807@code{CLOBBER}ed registers in this list augment registers specified in 2808@code{CALL_USED_REGISTERS} (@pxref{Register Basics}). 2809 2810@findex code_label 2811@findex CODE_LABEL_NUMBER 2812@item code_label 2813A @code{code_label} insn represents a label that a jump insn can jump 2814to. It contains two special fields of data in addition to the three 2815standard ones. @code{CODE_LABEL_NUMBER} is used to hold the @dfn{label 2816number}, a number that identifies this label uniquely among all the 2817labels in the compilation (not just in the current function). 2818Ultimately, the label is represented in the assembler output as an 2819assembler label, usually of the form @samp{L@var{n}} where @var{n} is 2820the label number. 2821 2822When a @code{code_label} appears in an RTL expression, it normally 2823appears within a @code{label_ref} which represents the address of 2824the label, as a number. 2825 2826Besides as a @code{code_label}, a label can also be represented as a 2827@code{note} of type @code{NOTE_INSN_DELETED_LABEL}. 2828 2829@findex LABEL_NUSES 2830The field @code{LABEL_NUSES} is only defined once the jump optimization 2831phase is completed. It contains the number of times this label is 2832referenced in the current function. 2833 2834@findex LABEL_KIND 2835@findex SET_LABEL_KIND 2836@findex LABEL_ALT_ENTRY_P 2837@cindex alternate entry points 2838The field @code{LABEL_KIND} differentiates four different types of 2839labels: @code{LABEL_NORMAL}, @code{LABEL_STATIC_ENTRY}, 2840@code{LABEL_GLOBAL_ENTRY}, and @code{LABEL_WEAK_ENTRY}. The only labels 2841that do not have type @code{LABEL_NORMAL} are @dfn{alternate entry 2842points} to the current function. These may be static (visible only in 2843the containing translation unit), global (exposed to all translation 2844units), or weak (global, but can be overridden by another symbol with the 2845same name). 2846 2847Much of the compiler treats all four kinds of label identically. Some 2848of it needs to know whether or not a label is an alternate entry point; 2849for this purpose, the macro @code{LABEL_ALT_ENTRY_P} is provided. It is 2850equivalent to testing whether @samp{LABEL_KIND (label) == LABEL_NORMAL}. 2851The only place that cares about the distinction between static, global, 2852and weak alternate entry points, besides the front-end code that creates 2853them, is the function @code{output_alternate_entry_point}, in 2854@file{final.c}. 2855 2856To set the kind of a label, use the @code{SET_LABEL_KIND} macro. 2857 2858@findex barrier 2859@item barrier 2860Barriers are placed in the instruction stream when control cannot flow 2861past them. They are placed after unconditional jump instructions to 2862indicate that the jumps are unconditional and after calls to 2863@code{volatile} functions, which do not return (e.g., @code{exit}). 2864They contain no information beyond the three standard fields. 2865 2866@findex note 2867@findex NOTE_LINE_NUMBER 2868@findex NOTE_SOURCE_FILE 2869@item note 2870@code{note} insns are used to represent additional debugging and 2871declarative information. They contain two nonstandard fields, an 2872integer which is accessed with the macro @code{NOTE_LINE_NUMBER} and a 2873string accessed with @code{NOTE_SOURCE_FILE}. 2874 2875If @code{NOTE_LINE_NUMBER} is positive, the note represents the 2876position of a source line and @code{NOTE_SOURCE_FILE} is the source file name 2877that the line came from. These notes control generation of line 2878number data in the assembler output. 2879 2880Otherwise, @code{NOTE_LINE_NUMBER} is not really a line number but a 2881code with one of the following values (and @code{NOTE_SOURCE_FILE} 2882must contain a null pointer): 2883 2884@table @code 2885@findex NOTE_INSN_DELETED 2886@item NOTE_INSN_DELETED 2887Such a note is completely ignorable. Some passes of the compiler 2888delete insns by altering them into notes of this kind. 2889 2890@findex NOTE_INSN_DELETED_LABEL 2891@item NOTE_INSN_DELETED_LABEL 2892This marks what used to be a @code{code_label}, but was not used for other 2893purposes than taking its address and was transformed to mark that no 2894code jumps to it. 2895 2896@findex NOTE_INSN_BLOCK_BEG 2897@findex NOTE_INSN_BLOCK_END 2898@item NOTE_INSN_BLOCK_BEG 2899@itemx NOTE_INSN_BLOCK_END 2900These types of notes indicate the position of the beginning and end 2901of a level of scoping of variable names. They control the output 2902of debugging information. 2903 2904@findex NOTE_INSN_EH_REGION_BEG 2905@findex NOTE_INSN_EH_REGION_END 2906@item NOTE_INSN_EH_REGION_BEG 2907@itemx NOTE_INSN_EH_REGION_END 2908These types of notes indicate the position of the beginning and end of a 2909level of scoping for exception handling. @code{NOTE_BLOCK_NUMBER} 2910identifies which @code{CODE_LABEL} or @code{note} of type 2911@code{NOTE_INSN_DELETED_LABEL} is associated with the given region. 2912 2913@findex NOTE_INSN_LOOP_BEG 2914@findex NOTE_INSN_LOOP_END 2915@item NOTE_INSN_LOOP_BEG 2916@itemx NOTE_INSN_LOOP_END 2917These types of notes indicate the position of the beginning and end 2918of a @code{while} or @code{for} loop. They enable the loop optimizer 2919to find loops quickly. 2920 2921@findex NOTE_INSN_LOOP_CONT 2922@item NOTE_INSN_LOOP_CONT 2923Appears at the place in a loop that @code{continue} statements jump to. 2924 2925@findex NOTE_INSN_LOOP_VTOP 2926@item NOTE_INSN_LOOP_VTOP 2927This note indicates the place in a loop where the exit test begins for 2928those loops in which the exit test has been duplicated. This position 2929becomes another virtual start of the loop when considering loop 2930invariants. 2931 2932@findex NOTE_INSN_FUNCTION_END 2933@item NOTE_INSN_FUNCTION_END 2934Appears near the end of the function body, just before the label that 2935@code{return} statements jump to (on machine where a single instruction 2936does not suffice for returning). This note may be deleted by jump 2937optimization. 2938 2939@findex NOTE_INSN_SETJMP 2940@item NOTE_INSN_SETJMP 2941Appears following each call to @code{setjmp} or a related function. 2942@end table 2943 2944These codes are printed symbolically when they appear in debugging dumps. 2945@end table 2946 2947@cindex @code{TImode}, in @code{insn} 2948@cindex @code{HImode}, in @code{insn} 2949@cindex @code{QImode}, in @code{insn} 2950The machine mode of an insn is normally @code{VOIDmode}, but some 2951phases use the mode for various purposes. 2952 2953The common subexpression elimination pass sets the mode of an insn to 2954@code{QImode} when it is the first insn in a block that has already 2955been processed. 2956 2957The second Haifa scheduling pass, for targets that can multiple issue, 2958sets the mode of an insn to @code{TImode} when it is believed that the 2959instruction begins an issue group. That is, when the instruction 2960cannot issue simultaneously with the previous. This may be relied on 2961by later passes, in particular machine-dependent reorg. 2962 2963Here is a table of the extra fields of @code{insn}, @code{jump_insn} 2964and @code{call_insn} insns: 2965 2966@table @code 2967@findex PATTERN 2968@item PATTERN (@var{i}) 2969An expression for the side effect performed by this insn. This must be 2970one of the following codes: @code{set}, @code{call}, @code{use}, 2971@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output}, 2972@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec}, 2973@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a @code{parallel}, 2974each element of the @code{parallel} must be one these codes, except that 2975@code{parallel} expressions cannot be nested and @code{addr_vec} and 2976@code{addr_diff_vec} are not permitted inside a @code{parallel} expression. 2977 2978@findex INSN_CODE 2979@item INSN_CODE (@var{i}) 2980An integer that says which pattern in the machine description matches 2981this insn, or @minus{}1 if the matching has not yet been attempted. 2982 2983Such matching is never attempted and this field remains @minus{}1 on an insn 2984whose pattern consists of a single @code{use}, @code{clobber}, 2985@code{asm_input}, @code{addr_vec} or @code{addr_diff_vec} expression. 2986 2987@findex asm_noperands 2988Matching is also never attempted on insns that result from an @code{asm} 2989statement. These contain at least one @code{asm_operands} expression. 2990The function @code{asm_noperands} returns a non-negative value for 2991such insns. 2992 2993In the debugging output, this field is printed as a number followed by 2994a symbolic representation that locates the pattern in the @file{md} 2995file as some small positive or negative offset from a named pattern. 2996 2997@findex LOG_LINKS 2998@item LOG_LINKS (@var{i}) 2999A list (chain of @code{insn_list} expressions) giving information about 3000dependencies between instructions within a basic block. Neither a jump 3001nor a label may come between the related insns. 3002 3003@findex REG_NOTES 3004@item REG_NOTES (@var{i}) 3005A list (chain of @code{expr_list} and @code{insn_list} expressions) 3006giving miscellaneous information about the insn. It is often 3007information pertaining to the registers used in this insn. 3008@end table 3009 3010The @code{LOG_LINKS} field of an insn is a chain of @code{insn_list} 3011expressions. Each of these has two operands: the first is an insn, 3012and the second is another @code{insn_list} expression (the next one in 3013the chain). The last @code{insn_list} in the chain has a null pointer 3014as second operand. The significant thing about the chain is which 3015insns appear in it (as first operands of @code{insn_list} 3016expressions). Their order is not significant. 3017 3018This list is originally set up by the flow analysis pass; it is a null 3019pointer until then. Flow only adds links for those data dependencies 3020which can be used for instruction combination. For each insn, the flow 3021analysis pass adds a link to insns which store into registers values 3022that are used for the first time in this insn. The instruction 3023scheduling pass adds extra links so that every dependence will be 3024represented. Links represent data dependencies, antidependencies and 3025output dependencies; the machine mode of the link distinguishes these 3026three types: antidependencies have mode @code{REG_DEP_ANTI}, output 3027dependencies have mode @code{REG_DEP_OUTPUT}, and data dependencies have 3028mode @code{VOIDmode}. 3029 3030The @code{REG_NOTES} field of an insn is a chain similar to the 3031@code{LOG_LINKS} field but it includes @code{expr_list} expressions in 3032addition to @code{insn_list} expressions. There are several kinds of 3033register notes, which are distinguished by the machine mode, which in a 3034register note is really understood as being an @code{enum reg_note}. 3035The first operand @var{op} of the note is data whose meaning depends on 3036the kind of note. 3037 3038@findex REG_NOTE_KIND 3039@findex PUT_REG_NOTE_KIND 3040The macro @code{REG_NOTE_KIND (@var{x})} returns the kind of 3041register note. Its counterpart, the macro @code{PUT_REG_NOTE_KIND 3042(@var{x}, @var{newkind})} sets the register note type of @var{x} to be 3043@var{newkind}. 3044 3045Register notes are of three classes: They may say something about an 3046input to an insn, they may say something about an output of an insn, or 3047they may create a linkage between two insns. There are also a set 3048of values that are only used in @code{LOG_LINKS}. 3049 3050These register notes annotate inputs to an insn: 3051 3052@table @code 3053@findex REG_DEAD 3054@item REG_DEAD 3055The value in @var{op} dies in this insn; that is to say, altering the 3056value immediately after this insn would not affect the future behavior 3057of the program. 3058 3059It does not follow that the register @var{op} has no useful value after 3060this insn since @var{op} is not necessarily modified by this insn. 3061Rather, no subsequent instruction uses the contents of @var{op}. 3062 3063@findex REG_UNUSED 3064@item REG_UNUSED 3065The register @var{op} being set by this insn will not be used in a 3066subsequent insn. This differs from a @code{REG_DEAD} note, which 3067indicates that the value in an input will not be used subsequently. 3068These two notes are independent; both may be present for the same 3069register. 3070 3071@findex REG_INC 3072@item REG_INC 3073The register @var{op} is incremented (or decremented; at this level 3074there is no distinction) by an embedded side effect inside this insn. 3075This means it appears in a @code{post_inc}, @code{pre_inc}, 3076@code{post_dec} or @code{pre_dec} expression. 3077 3078@findex REG_NONNEG 3079@item REG_NONNEG 3080The register @var{op} is known to have a nonnegative value when this 3081insn is reached. This is used so that decrement and branch until zero 3082instructions, such as the m68k dbra, can be matched. 3083 3084The @code{REG_NONNEG} note is added to insns only if the machine 3085description has a @samp{decrement_and_branch_until_zero} pattern. 3086 3087@findex REG_NO_CONFLICT 3088@item REG_NO_CONFLICT 3089This insn does not cause a conflict between @var{op} and the item 3090being set by this insn even though it might appear that it does. 3091In other words, if the destination register and @var{op} could 3092otherwise be assigned the same register, this insn does not 3093prevent that assignment. 3094 3095Insns with this note are usually part of a block that begins with a 3096@code{clobber} insn specifying a multi-word pseudo register (which will 3097be the output of the block), a group of insns that each set one word of 3098the value and have the @code{REG_NO_CONFLICT} note attached, and a final 3099insn that copies the output to itself with an attached @code{REG_EQUAL} 3100note giving the expression being computed. This block is encapsulated 3101with @code{REG_LIBCALL} and @code{REG_RETVAL} notes on the first and 3102last insns, respectively. 3103 3104@findex REG_LABEL 3105@item REG_LABEL 3106This insn uses @var{op}, a @code{code_label} or a @code{note} of type 3107@code{NOTE_INSN_DELETED_LABEL}, but is not a 3108@code{jump_insn}, or it is a @code{jump_insn} that required the label to 3109be held in a register. The presence of this note allows jump 3110optimization to be aware that @var{op} is, in fact, being used, and flow 3111optimization to build an accurate flow graph. 3112@end table 3113 3114The following notes describe attributes of outputs of an insn: 3115 3116@table @code 3117@findex REG_EQUIV 3118@findex REG_EQUAL 3119@item REG_EQUIV 3120@itemx REG_EQUAL 3121This note is only valid on an insn that sets only one register and 3122indicates that that register will be equal to @var{op} at run time; the 3123scope of this equivalence differs between the two types of notes. The 3124value which the insn explicitly copies into the register may look 3125different from @var{op}, but they will be equal at run time. If the 3126output of the single @code{set} is a @code{strict_low_part} expression, 3127the note refers to the register that is contained in @code{SUBREG_REG} 3128of the @code{subreg} expression. 3129 3130For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout 3131the entire function, and could validly be replaced in all its 3132occurrences by @var{op}. (``Validly'' here refers to the data flow of 3133the program; simple replacement may make some insns invalid.) For 3134example, when a constant is loaded into a register that is never 3135assigned any other value, this kind of note is used. 3136 3137When a parameter is copied into a pseudo-register at entry to a function, 3138a note of this kind records that the register is equivalent to the stack 3139slot where the parameter was passed. Although in this case the register 3140may be set by other insns, it is still valid to replace the register 3141by the stack slot throughout the function. 3142 3143A @code{REG_EQUIV} note is also used on an instruction which copies a 3144register parameter into a pseudo-register at entry to a function, if 3145there is a stack slot where that parameter could be stored. Although 3146other insns may set the pseudo-register, it is valid for the compiler to 3147replace the pseudo-register by stack slot throughout the function, 3148provided the compiler ensures that the stack slot is properly 3149initialized by making the replacement in the initial copy instruction as 3150well. This is used on machines for which the calling convention 3151allocates stack space for register parameters. See 3152@code{REG_PARM_STACK_SPACE} in @ref{Stack Arguments}. 3153 3154In the case of @code{REG_EQUAL}, the register that is set by this insn 3155will be equal to @var{op} at run time at the end of this insn but not 3156necessarily elsewhere in the function. In this case, @var{op} 3157is typically an arithmetic expression. For example, when a sequence of 3158insns such as a library call is used to perform an arithmetic operation, 3159this kind of note is attached to the insn that produces or copies the 3160final value. 3161 3162These two notes are used in different ways by the compiler passes. 3163@code{REG_EQUAL} is used by passes prior to register allocation (such as 3164common subexpression elimination and loop optimization) to tell them how 3165to think of that value. @code{REG_EQUIV} notes are used by register 3166allocation to indicate that there is an available substitute expression 3167(either a constant or a @code{mem} expression for the location of a 3168parameter on the stack) that may be used in place of a register if 3169insufficient registers are available. 3170 3171Except for stack homes for parameters, which are indicated by a 3172@code{REG_EQUIV} note and are not useful to the early optimization 3173passes and pseudo registers that are equivalent to a memory location 3174throughout their entire life, which is not detected until later in 3175the compilation, all equivalences are initially indicated by an attached 3176@code{REG_EQUAL} note. In the early stages of register allocation, a 3177@code{REG_EQUAL} note is changed into a @code{REG_EQUIV} note if 3178@var{op} is a constant and the insn represents the only set of its 3179destination register. 3180 3181Thus, compiler passes prior to register allocation need only check for 3182@code{REG_EQUAL} notes and passes subsequent to register allocation 3183need only check for @code{REG_EQUIV} notes. 3184 3185@findex REG_WAS_0 3186@item REG_WAS_0 3187The single output of this insn contained zero before this insn. 3188@var{op} is the insn that set it to zero. You can rely on this note if 3189it is present and @var{op} has not been deleted or turned into a @code{note}; 3190its absence implies nothing. 3191@end table 3192 3193These notes describe linkages between insns. They occur in pairs: one 3194insn has one of a pair of notes that points to a second insn, which has 3195the inverse note pointing back to the first insn. 3196 3197@table @code 3198@findex REG_RETVAL 3199@item REG_RETVAL 3200This insn copies the value of a multi-insn sequence (for example, a 3201library call), and @var{op} is the first insn of the sequence (for a 3202library call, the first insn that was generated to set up the arguments 3203for the library call). 3204 3205Loop optimization uses this note to treat such a sequence as a single 3206operation for code motion purposes and flow analysis uses this note to 3207delete such sequences whose results are dead. 3208 3209A @code{REG_EQUAL} note will also usually be attached to this insn to 3210provide the expression being computed by the sequence. 3211 3212These notes will be deleted after reload, since they are no longer 3213accurate or useful. 3214 3215@findex REG_LIBCALL 3216@item REG_LIBCALL 3217This is the inverse of @code{REG_RETVAL}: it is placed on the first 3218insn of a multi-insn sequence, and it points to the last one. 3219 3220These notes are deleted after reload, since they are no longer useful or 3221accurate. 3222 3223@findex REG_CC_SETTER 3224@findex REG_CC_USER 3225@item REG_CC_SETTER 3226@itemx REG_CC_USER 3227On machines that use @code{cc0}, the insns which set and use @code{cc0} 3228set and use @code{cc0} are adjacent. However, when branch delay slot 3229filling is done, this may no longer be true. In this case a 3230@code{REG_CC_USER} note will be placed on the insn setting @code{cc0} to 3231point to the insn using @code{cc0} and a @code{REG_CC_SETTER} note will 3232be placed on the insn using @code{cc0} to point to the insn setting 3233@code{cc0}. 3234@end table 3235 3236These values are only used in the @code{LOG_LINKS} field, and indicate 3237the type of dependency that each link represents. Links which indicate 3238a data dependence (a read after write dependence) do not use any code, 3239they simply have mode @code{VOIDmode}, and are printed without any 3240descriptive text. 3241 3242@table @code 3243@findex REG_DEP_ANTI 3244@item REG_DEP_ANTI 3245This indicates an anti dependence (a write after read dependence). 3246 3247@findex REG_DEP_OUTPUT 3248@item REG_DEP_OUTPUT 3249This indicates an output dependence (a write after write dependence). 3250@end table 3251 3252These notes describe information gathered from gcov profile data. They 3253are stored in the @code{REG_NOTES} field of an insn as an 3254@code{expr_list}. 3255 3256@table @code 3257@findex REG_BR_PROB 3258@item REG_BR_PROB 3259This is used to specify the ratio of branches to non-branches of a 3260branch insn according to the profile data. The value is stored as a 3261value between 0 and REG_BR_PROB_BASE; larger values indicate a higher 3262probability that the branch will be taken. 3263 3264@findex REG_BR_PRED 3265@item REG_BR_PRED 3266These notes are found in JUMP insns after delayed branch scheduling 3267has taken place. They indicate both the direction and the likelihood 3268of the JUMP@. The format is a bitmask of ATTR_FLAG_* values. 3269 3270@findex REG_FRAME_RELATED_EXPR 3271@item REG_FRAME_RELATED_EXPR 3272This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression 3273is used in place of the actual insn pattern. This is done in cases where 3274the pattern is either complex or misleading. 3275@end table 3276 3277For convenience, the machine mode in an @code{insn_list} or 3278@code{expr_list} is printed using these symbolic codes in debugging dumps. 3279 3280@findex insn_list 3281@findex expr_list 3282The only difference between the expression codes @code{insn_list} and 3283@code{expr_list} is that the first operand of an @code{insn_list} is 3284assumed to be an insn and is printed in debugging dumps as the insn's 3285unique id; the first operand of an @code{expr_list} is printed in the 3286ordinary way as an expression. 3287 3288@node Calls 3289@section RTL Representation of Function-Call Insns 3290@cindex calling functions in RTL 3291@cindex RTL function-call insns 3292@cindex function-call insns 3293 3294Insns that call subroutines have the RTL expression code @code{call_insn}. 3295These insns must satisfy special rules, and their bodies must use a special 3296RTL expression code, @code{call}. 3297 3298@cindex @code{call} usage 3299A @code{call} expression has two operands, as follows: 3300 3301@example 3302(call (mem:@var{fm} @var{addr}) @var{nbytes}) 3303@end example 3304 3305@noindent 3306Here @var{nbytes} is an operand that represents the number of bytes of 3307argument data being passed to the subroutine, @var{fm} is a machine mode 3308(which must equal as the definition of the @code{FUNCTION_MODE} macro in 3309the machine description) and @var{addr} represents the address of the 3310subroutine. 3311 3312For a subroutine that returns no value, the @code{call} expression as 3313shown above is the entire body of the insn, except that the insn might 3314also contain @code{use} or @code{clobber} expressions. 3315 3316@cindex @code{BLKmode}, and function return values 3317For a subroutine that returns a value whose mode is not @code{BLKmode}, 3318the value is returned in a hard register. If this register's number is 3319@var{r}, then the body of the call insn looks like this: 3320 3321@example 3322(set (reg:@var{m} @var{r}) 3323 (call (mem:@var{fm} @var{addr}) @var{nbytes})) 3324@end example 3325 3326@noindent 3327This RTL expression makes it clear (to the optimizer passes) that the 3328appropriate register receives a useful value in this insn. 3329 3330When a subroutine returns a @code{BLKmode} value, it is handled by 3331passing to the subroutine the address of a place to store the value. 3332So the call insn itself does not ``return'' any value, and it has the 3333same RTL form as a call that returns nothing. 3334 3335On some machines, the call instruction itself clobbers some register, 3336for example to contain the return address. @code{call_insn} insns 3337on these machines should have a body which is a @code{parallel} 3338that contains both the @code{call} expression and @code{clobber} 3339expressions that indicate which registers are destroyed. Similarly, 3340if the call instruction requires some register other than the stack 3341pointer that is not explicitly mentioned it its RTL, a @code{use} 3342subexpression should mention that register. 3343 3344Functions that are called are assumed to modify all registers listed in 3345the configuration macro @code{CALL_USED_REGISTERS} (@pxref{Register 3346Basics}) and, with the exception of @code{const} functions and library 3347calls, to modify all of memory. 3348 3349Insns containing just @code{use} expressions directly precede the 3350@code{call_insn} insn to indicate which registers contain inputs to the 3351function. Similarly, if registers other than those in 3352@code{CALL_USED_REGISTERS} are clobbered by the called function, insns 3353containing a single @code{clobber} follow immediately after the call to 3354indicate which registers. 3355 3356@node Sharing 3357@section Structure Sharing Assumptions 3358@cindex sharing of RTL components 3359@cindex RTL structure sharing assumptions 3360 3361The compiler assumes that certain kinds of RTL expressions are unique; 3362there do not exist two distinct objects representing the same value. 3363In other cases, it makes an opposite assumption: that no RTL expression 3364object of a certain kind appears in more than one place in the 3365containing structure. 3366 3367These assumptions refer to a single function; except for the RTL 3368objects that describe global variables and external functions, 3369and a few standard objects such as small integer constants, 3370no RTL objects are common to two functions. 3371 3372@itemize @bullet 3373@cindex @code{reg}, RTL sharing 3374@item 3375Each pseudo-register has only a single @code{reg} object to represent it, 3376and therefore only a single machine mode. 3377 3378@cindex symbolic label 3379@cindex @code{symbol_ref}, RTL sharing 3380@item 3381For any symbolic label, there is only one @code{symbol_ref} object 3382referring to it. 3383 3384@cindex @code{const_int}, RTL sharing 3385@item 3386All @code{const_int} expressions with equal values are shared. 3387 3388@cindex @code{pc}, RTL sharing 3389@item 3390There is only one @code{pc} expression. 3391 3392@cindex @code{cc0}, RTL sharing 3393@item 3394There is only one @code{cc0} expression. 3395 3396@cindex @code{const_double}, RTL sharing 3397@item 3398There is only one @code{const_double} expression with value 0 for 3399each floating point mode. Likewise for values 1 and 2. 3400 3401@cindex @code{const_vector}, RTL sharing 3402@item 3403There is only one @code{const_vector} expression with value 0 for 3404each vector mode, be it an integer or a double constant vector. 3405 3406@cindex @code{label_ref}, RTL sharing 3407@cindex @code{scratch}, RTL sharing 3408@item 3409No @code{label_ref} or @code{scratch} appears in more than one place in 3410the RTL structure; in other words, it is safe to do a tree-walk of all 3411the insns in the function and assume that each time a @code{label_ref} 3412or @code{scratch} is seen it is distinct from all others that are seen. 3413 3414@cindex @code{mem}, RTL sharing 3415@item 3416Only one @code{mem} object is normally created for each static 3417variable or stack slot, so these objects are frequently shared in all 3418the places they appear. However, separate but equal objects for these 3419variables are occasionally made. 3420 3421@cindex @code{asm_operands}, RTL sharing 3422@item 3423When a single @code{asm} statement has multiple output operands, a 3424distinct @code{asm_operands} expression is made for each output operand. 3425However, these all share the vector which contains the sequence of input 3426operands. This sharing is used later on to test whether two 3427@code{asm_operands} expressions come from the same statement, so all 3428optimizations must carefully preserve the sharing if they copy the 3429vector at all. 3430 3431@item 3432No RTL object appears in more than one place in the RTL structure 3433except as described above. Many passes of the compiler rely on this 3434by assuming that they can modify RTL objects in place without unwanted 3435side-effects on other insns. 3436 3437@findex unshare_all_rtl 3438@item 3439During initial RTL generation, shared structure is freely introduced. 3440After all the RTL for a function has been generated, all shared 3441structure is copied by @code{unshare_all_rtl} in @file{emit-rtl.c}, 3442after which the above rules are guaranteed to be followed. 3443 3444@findex copy_rtx_if_shared 3445@item 3446During the combiner pass, shared structure within an insn can exist 3447temporarily. However, the shared structure is copied before the 3448combiner is finished with the insn. This is done by calling 3449@code{copy_rtx_if_shared}, which is a subroutine of 3450@code{unshare_all_rtl}. 3451@end itemize 3452 3453@node Reading RTL 3454@section Reading RTL 3455 3456To read an RTL object from a file, call @code{read_rtx}. It takes one 3457argument, a stdio stream, and returns a single RTL object. This routine 3458is defined in @file{read-rtl.c}. It is not available in the compiler 3459itself, only the various programs that generate the compiler back end 3460from the machine description. 3461 3462People frequently have the idea of using RTL stored as text in a file as 3463an interface between a language front end and the bulk of GCC@. This 3464idea is not feasible. 3465 3466GCC was designed to use RTL internally only. Correct RTL for a given 3467program is very dependent on the particular target machine. And the RTL 3468does not contain all the information about the program. 3469 3470The proper way to interface GCC to a new language front end is with 3471the ``tree'' data structure, described in the files @file{tree.h} and 3472@file{tree.def}. The documentation for this structure (@pxref{Trees}) 3473is incomplete. 3474